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ath9k: fix sifs time for half/quarter and remove some unnecessary defines
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27565 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -1,6 +1,20 @@
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--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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@@ -951,25 +951,60 @@ static bool ath9k_hw_set_global_txtimeou
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@@ -914,6 +914,13 @@ static void ath9k_hw_init_interrupt_mask
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}
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}
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+static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
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+{
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+ u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
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+ val = min(val, (u32) 0xFFFF);
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+ REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
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+}
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+
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static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
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{
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u32 val = ath9k_hw_mac_to_clks(ah, us);
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@@ -951,25 +958,60 @@ static bool ath9k_hw_set_global_txtimeou
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void ath9k_hw_init_global_settings(struct ath_hw *ah)
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{
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@ -68,11 +82,12 @@
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/*
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* Workaround for early ACK timeouts, add an offset to match the
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@@ -981,11 +1016,19 @@ void ath9k_hw_init_global_settings(struc
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@@ -981,11 +1023,20 @@ void ath9k_hw_init_global_settings(struc
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if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
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acktimeout += 64 - sifstime - ah->slottime;
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- ath9k_hw_setslottime(ah, ah->slottime);
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+ ath9k_hw_set_sifs_time(ah, sifstime);
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+ ath9k_hw_setslottime(ah, slottime);
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ath9k_hw_set_ack_timeout(ah, acktimeout);
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ath9k_hw_set_cts_timeout(ah, acktimeout);
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@ -48,7 +48,7 @@
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{
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--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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@@ -1633,9 +1633,13 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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@@ -1641,9 +1641,13 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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ath9k_hw_init_global_settings(ah);
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@ -76,3 +76,42 @@
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/*
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* Code specific to AR9003, we stuff these here to avoid callbacks
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--- a/drivers/net/wireless/ath/ath9k/reg.h
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+++ b/drivers/net/wireless/ath/ath9k/reg.h
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@@ -600,7 +600,6 @@
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#define AR_D_GBL_IFS_SIFS 0x1030
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#define AR_D_GBL_IFS_SIFS_M 0x0000FFFF
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-#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB
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#define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF
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#define AR_D_TXBLK_BASE 0x1038
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@@ -616,12 +615,10 @@
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#define AR_D_GBL_IFS_SLOT 0x1070
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#define AR_D_GBL_IFS_SLOT_M 0x0000FFFF
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#define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000
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-#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420
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#define AR_D_GBL_IFS_EIFS 0x10b0
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#define AR_D_GBL_IFS_EIFS_M 0x0000FFFF
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#define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000
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-#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB
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#define AR_D_GBL_IFS_MISC 0x10f0
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#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007
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@@ -1477,7 +1474,6 @@ enum {
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#define AR_TIME_OUT_ACK_S 0
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#define AR_TIME_OUT_CTS 0x3FFF0000
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#define AR_TIME_OUT_CTS_S 16
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-#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56
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#define AR_RSSI_THR 0x8018
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#define AR_RSSI_THR_MASK 0x000000FF
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@@ -1493,7 +1489,6 @@ enum {
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#define AR_USEC_TX_LAT_S 14
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#define AR_USEC_RX_LAT 0x1F800000
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#define AR_USEC_RX_LAT_S 23
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-#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074
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#define AR_RESET_TSF 0x8020
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#define AR_RESET_TSF_ONCE 0x01000000
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