Merge branch 'xburst' of projects.qi-hardware.com:openwrt-xburst into xburst

Config.in

@@ -25,6 +25,7 @@ menu "Target Images"
 		depends TARGET_ROOTFS_INITRAMFS
 		depends !LINUX_2_6_25
 		default TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_ar71xx
+		default TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_ramips
 		default TARGET_INITRAMFS_COMPRESSION_NONE
 		help
 		  Select ramdisk compression.

include/download.mk

@@ -104,10 +104,10 @@ define DownloadMethod/bzr
 		cd $(TMP_DIR)/dl && \
 		rm -rf $(SUBDIR) && \
 		[ \! -d $(SUBDIR) ] && \
-		bzr export -r$(VERSION) $(URL) $(SUBDIR) && \
+		bzr export -r$(VERSION) $(SUBDIR) $(URL) && \
 		echo "Packing checkout..." && \
 		$(call dl_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \
-		mv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ &&
+		mv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \
 		rm -rf $(SUBDIR); \
 	)
 endef

package/base-files/files/sbin/hotplug-call

@@ -10,7 +10,7 @@ export HOTPLUG_TYPE="$1"
 		echo 1 > "/sys$DEVPATH/loading"
 		dd if="/lib/firmware/$FIRMWARE" of="/sys$DEVPATH/data" bs=64k
 		echo 0 > "/sys$DEVPATH/loading"
-	}
+	} || echo -1 > "/sys$DEVPATH/loading"
 	exit 0
 }
 

package/ep80579-drivers/Makefile

@@ -0,0 +1,80 @@
+#
+# Copyright (C) 2010 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=ep80579-drivers
+PKG_VERSION:=1.0.34
+PKG_RELEASE:=1
+
+PKG_SOURCE:=Embedded.L.1.0.34.ADI.R100.tar.gz
+PKG_SOURCE_URL:=ftp://ftp.adiengineering.com/Archive/OcracokeIsland/Drivers/Linux/1.0.34/
+PKG_MD5SUM:=61df9778f8c1f919257d2f48a0bcb000
+
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)
+
+include $(INCLUDE_DIR)/package.mk
+
+define KernelPackage/ep80579-drivers/Default
+  DEPENDS:=@TARGET_x86
+endef
+
+define KernelPackage/ep80579-eth
+$(call KernelPackage/ep80579-drivers/Default)
+  SUBMENU:=Network Devices
+  TITLE:=Intel EP80579 ethernet driver
+  FILES:= \
+	$(PKG_BUILD_DIR)/Embedded/build/gcu.$(LINUX_KMOD_SUFFIX) \
+	$(PKG_BUILD_DIR)/Embedded/build/iegbe.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,40,gcu iegbe)
+endef
+
+define KernelPackage/ep80579-misc
+$(call KernelPackage/ep80579-drivers/Default)
+  SUBMENU:=Other modules
+  TITLE:=Misc. Intel EP80579 drivers (DMA,, gpio)
+  FILES:= \
+	$(PKG_BUILD_DIR)/Embedded/build/dma.$(LINUX_KMOD_SUFFIX) \
+	$(PKG_BUILD_DIR)/Embedded/build/gpio.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,40,gpio dma)
+endef
+
+define KernelPackage/ep80579-can
+$(call KernelPackage/ep80579-drivers/Default)
+  SUBMENU:=Other modules
+  TITLE:=Intel EP80579 CAN driver
+  FILES:= \
+	$(PKG_BUILD_DIR)/Embedded/build/timesync.$(LINUX_KMOD_SUFFIX) \
+	$(PKG_BUILD_DIR)/Embedded/build/can.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,40,timesync can)
+endef
+
+define Build/Prepare
+	rm -rf $(PKG_BUILD_DIR)
+	mkdir -p $(PKG_BUILD_DIR)
+	tar xzvf $(DL_DIR)/$(PKG_SOURCE) -C $(PKG_BUILD_DIR)/
+	$(Build/Patch)
+endef
+
+define Build/Compile
+	(cd $(PKG_BUILD_DIR)/Embedded; \
+		$(MAKE) KERNEL_SOURCE_ROOT=$(LINUX_DIR) \
+		KSRC=$(LINUX_DIR) \
+		KOBJ=$(LINUX_DIR) \
+		ENV_DIR=$(PKG_BUILD_DIR)/Embedded \
+		all \
+	)
+endef
+
+define KernelPackage/ep80579-eth/install
+endef
+
+$(eval $(call KernelPackage,ep80579-can))
+$(eval $(call KernelPackage,ep80579-eth))
+$(eval $(call KernelPackage,ep80579-misc))
+

package/ep80579-drivers/patches/002-cflags_cleanup.patch

@@ -0,0 +1,22 @@
+--- a/build_system/build_files/common.mk
++++ b/build_system/build_files/common.mk
+@@ -122,7 +122,7 @@ CC=$(COMPILER)
+ LD=$(LINKER)
+ AR=$(ARCHIVER)
+ 
+-CFLAGS+=-O2
++#CFLAGS+=-O2
+ 
+ 
+ PWD= $(shell pwd)
+--- a/build_system/build_files/OS/linux_2.6.mk
++++ b/build_system/build_files/OS/linux_2.6.mk
+@@ -80,7 +80,7 @@ endif
+ 
+ 
+ ifeq ($(OS_LEVEL), kernel_space)
+-CFLAGS+= 
++#CFLAGS+= 
+ endif
+ 
+ 

package/ep80579-drivers/patches/003-new_irqf_constants.patch

@@ -0,0 +1,53 @@
+--- a/Embedded/src/1588/1588.c
++++ b/Embedded/src/1588/1588.c
+@@ -291,7 +291,7 @@ int pci_probe(struct pci_dev *dev, const
+ 
+     }
+ 
+-    if ( request_irq(dev->irq, &timesync_isr, SA_SHIRQ, DRIVERNAME,
++    if ( request_irq(dev->irq, &timesync_isr, IRQF_SHARED, DRIVERNAME,
+          &g_drvr_data) )
+     {
+       printk("%s-pci_probe: irq\n", DRIVERNAME);
+--- a/Embedded/src/CAN/can_main.c
++++ b/Embedded/src/CAN/can_main.c
+@@ -424,7 +424,7 @@ int can_open(struct inode *inode, struct
+     err = request_irq(
+         can_os->irq,
+         can_irq_handler,
+-        SA_SHIRQ,
++        IRQF_SHARED,
+         iminor(can_os->inode) ? CAN_PROC_1 : CAN_PROC_0,
+         &(g_can_os[iminor(can_os->inode)])
+         );
+--- a/Embedded/src/EDMA/dma_linux.c
++++ b/Embedded/src/EDMA/dma_linux.c
+@@ -367,7 +367,7 @@ int32_t edma_resume(struct pci_dev *dev)
+         return -ENODEV;
+     }
+ 
+-    if (request_irq(dev->irq, &edma_irq_handler, SA_SHIRQ,
++    if (request_irq(dev->irq, &edma_irq_handler, IRQF_SHARED,
+                         g_char_drvr_name, dev) )
+     {
+ 
+@@ -829,7 +829,7 @@ int32_t edma_probe(struct pci_dev * dev,
+     /*
+     * Obtain a (shared) Interrupt Request (IRQ) Line from the OS.
+     */
+-    if (request_irq(dev->irq, &edma_irq_handler, SA_SHIRQ,
++    if (request_irq(dev->irq, &edma_irq_handler, IRQF_SHARED,
+                         g_char_drvr_name, dev) )
+     {
+ 
+--- a/Embedded/src/WDT/iwdt.c
++++ b/Embedded/src/WDT/iwdt.c
+@@ -1461,7 +1461,7 @@ static int __init wdt_init_one(struct pc
+ 
+      /* Request irq only if wdt_irq is other than 0 */
+      if (wdt_irq) {
+-        if (request_irq(wdt_irq, wdt_isr, SA_INTERRUPT | SA_SHIRQ,
++        if (request_irq(wdt_irq, wdt_isr, IRQF_DISABLED | IRQF_SHARED,
+            "iwdt", &wdt_miscdev)) {
+            printk("IRQ %d is not free.\n", wdt_irq);
+            return -EIO;

package/ep80579-drivers/patches/100-iegbe_netdev_ops.patch

@@ -0,0 +1,56 @@
+--- a/Embedded/src/GbE/iegbe_main.c
++++ b/Embedded/src/GbE/iegbe_main.c
+@@ -724,6 +724,26 @@ static void iegbe_dump_eeprom(struct ieg
+ 	kfree(data);
+ }
+ 
++static const struct net_device_ops iegbe_netdev_ops = {
++	.ndo_open		= iegbe_open,
++	.ndo_stop		= iegbe_close,
++	.ndo_start_xmit		= iegbe_xmit_frame,
++	.ndo_get_stats		= iegbe_get_stats,
++	.ndo_set_rx_mode	= iegbe_set_rx_mode,
++	.ndo_set_mac_address	= iegbe_set_mac,
++	.ndo_tx_timeout		= iegbe_tx_timeout,
++	.ndo_change_mtu		= iegbe_change_mtu,
++	.ndo_do_ioctl		= iegbe_ioctl,
++	.ndo_validate_addr	= eth_validate_addr,
++
++	.ndo_vlan_rx_register	= iegbe_vlan_rx_register,
++	.ndo_vlan_rx_add_vid	= iegbe_vlan_rx_add_vid,
++	.ndo_vlan_rx_kill_vid	= iegbe_vlan_rx_kill_vid,
++#ifdef CONFIG_NET_POLL_CONTROLLER
++	.ndo_poll_controller	= iegbe_netpoll,
++#endif
++};
++
+ /**
+  * iegbe_probe - Device Initialization Routine
+  * @pdev: PCI device information struct
+@@ -800,24 +820,11 @@ static int __devinit iegbe_probe(struct 
+ 	if (!hw->hw_addr)
+         goto err_ioremap;
+ 
+-    netdev->open = &iegbe_open;
+-    netdev->stop = &iegbe_close;
+-    netdev->hard_start_xmit = &iegbe_xmit_frame;
+-    netdev->get_stats = &iegbe_get_stats;
+-	netdev->set_rx_mode = &iegbe_set_rx_mode;
+-	netdev->set_mac_address = &iegbe_set_mac;
+-    netdev->change_mtu = &iegbe_change_mtu;
+-    netdev->do_ioctl = &iegbe_ioctl;
++	netdev->netdev_ops = &iegbe_netdev_ops;
+ 	set_ethtool_ops(netdev);
+-    netdev->tx_timeout = &iegbe_tx_timeout;
+ 	netdev->watchdog_timeo = 5 * HZ;
+ 	netif_napi_add(netdev, &adapter->napi, iegbe_clean, 64);
+-    netdev->vlan_rx_register = iegbe_vlan_rx_register;
+-    netdev->vlan_rx_add_vid = iegbe_vlan_rx_add_vid;
+-    netdev->vlan_rx_kill_vid = iegbe_vlan_rx_kill_vid;
+-#ifdef CONFIG_NET_POLL_CONTROLLER
+-    netdev->poll_controller = iegbe_netpoll;
+-#endif
++
+ 	strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
+ 
+ 

package/ep80579-drivers/patches/101-iegbe_fix_napi_interface.patch

@@ -0,0 +1,41 @@
+--- a/Embedded/src/GbE/iegbe_main.c
++++ b/Embedded/src/GbE/iegbe_main.c
+@@ -3465,12 +3465,12 @@ static irqreturn_t iegbe_intr_msi(int ir
+ 	    printk("Critical error! ICR = 0x%x\n", icr);
+ 	    return IRQ_HANDLED;
+ 	}
+-	if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) {
++	if (likely(napi_schedule_prep(&adapter->napi))) {
+ 		adapter->total_tx_bytes = 0;
+ 		adapter->total_tx_packets = 0;
+ 		adapter->total_rx_bytes = 0;
+ 		adapter->total_rx_packets = 0;
+-		__netif_rx_schedule(netdev, &adapter->napi);
++		__napi_schedule(&adapter->napi);
+ 	} else
+ 		iegbe_irq_enable(adapter);
+ 
+@@ -3527,12 +3527,12 @@ iegbe_intr(int irq, void *data)
+ 		E1000_WRITE_REG(&adapter->hw, IMC, ~0);
+ 		E1000_WRITE_FLUSH(&adapter->hw);
+ 	}
+-	if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) {
++	if (likely(napi_schedule_prep(&adapter->napi))) {
+ 		adapter->total_tx_bytes = 0;
+ 		adapter->total_tx_packets = 0;
+ 		adapter->total_rx_bytes = 0;
+ 		adapter->total_rx_packets = 0;
+-		__netif_rx_schedule(netdev, &adapter->napi);
++		__napi_schedule(&adapter->napi);
+ 	} else
+ 		/* this really should not happen! if it does it is basically a
+ 		 * bug, but not a hard error, so enable ints and continue */
+@@ -3574,7 +3574,7 @@ static int iegbe_clean(struct napi_struc
+ 	if (work_done < budget) {
+ 		if (likely(adapter->itr_setting & 3))
+ 			iegbe_set_itr(adapter);
+-		netif_rx_complete(poll_dev, napi);
++		napi_complete(napi);
+ 		iegbe_irq_enable(adapter);
+ 	}
+ 

package/ep80579-drivers/patches/102-iegbe_nuke_polling_netdev.patch

@@ -0,0 +1,103 @@
+--- a/Embedded/src/GbE/iegbe.h
++++ b/Embedded/src/GbE/iegbe.h
+@@ -316,7 +316,6 @@ struct iegbe_adapter {
+ 				int cleaned_count);
+ 	struct iegbe_rx_ring *rx_ring;      /* One per active queue */
+ 	struct napi_struct napi;
+-	struct net_device *polling_netdev;  /* One per active queue */
+ 
+ 	int num_tx_queues;
+ 	int num_rx_queues;
+--- a/Embedded/src/GbE/iegbe_main.c
++++ b/Embedded/src/GbE/iegbe_main.c
+@@ -763,7 +763,7 @@ static int __devinit iegbe_probe(struct 
+ 	struct iegbe_hw *hw;
+ 
+ 	static int cards_found = 0;
+-    int i, err, pci_using_dac;
++	int err, pci_using_dac;
+ 	u16 eeprom_data = 0;
+ 	u16 eeprom_apme_mask = E1000_EEPROM_APME;
+ 	int bars; 
+@@ -984,11 +984,8 @@ err_eeprom:
+ 		iegbe_phy_hw_reset(hw);
+ 	if (hw->flash_address)
+ 		iounmap(hw->flash_address);
+-	for (i = 0; i < adapter->num_rx_queues; i++)
+-		dev_put(&adapter->polling_netdev[i]);
+ 	kfree(adapter->tx_ring);
+ 	kfree(adapter->rx_ring);
+-	kfree(adapter->polling_netdev);
+ err_sw_init:
+ 	iounmap(hw->hw_addr);
+ err_ioremap:
+@@ -1017,7 +1014,6 @@ iegbe_remove(struct pci_dev *pdev)
+     struct net_device *netdev = pci_get_drvdata(pdev);
+     struct iegbe_adapter *adapter = netdev_priv(netdev);
+     uint32_t manc;
+-    int i;
+ 
+     if(adapter->hw.mac_type >= iegbe_82540
+        && adapter->hw.mac_type != iegbe_icp_xxxx
+@@ -1030,15 +1026,11 @@ iegbe_remove(struct pci_dev *pdev)
+     }
+ 
+     unregister_netdev(netdev);
+-    for (i = 0x0; i < adapter->num_rx_queues; i++)
+-		dev_put(&adapter->polling_netdev[i]);
+-
+     if(!iegbe_check_phy_reset_block(&adapter->hw)) {
+         iegbe_phy_hw_reset(&adapter->hw);
+     }
+     kfree(adapter->tx_ring);
+     kfree(adapter->rx_ring);
+-    kfree(adapter->polling_netdev);
+ 
+     iounmap(adapter->hw.hw_addr);
+     pci_release_regions(pdev);
+@@ -1061,7 +1053,6 @@ iegbe_sw_init(struct iegbe_adapter *adap
+     struct iegbe_hw *hw = &adapter->hw;
+     struct net_device *netdev = adapter->netdev;
+     struct pci_dev *pdev = adapter->pdev;
+-    int i;
+ 
+     /* PCI config space info */
+ 
+@@ -1111,11 +1102,6 @@ iegbe_sw_init(struct iegbe_adapter *adap
+ 		return -ENOMEM;
+ 	}
+ 
+-	for (i = 0; i < adapter->num_rx_queues; i++) {
+-		adapter->polling_netdev[i].priv = adapter;
+-		dev_hold(&adapter->polling_netdev[i]);
+-		set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
+-	}
+ 	spin_lock_init(&adapter->tx_queue_lock);
+ 
+         /*
+@@ -1137,8 +1123,7 @@ iegbe_sw_init(struct iegbe_adapter *adap
+  * @adapter: board private structure to initialize
+  *
+  * We allocate one ring per queue at run-time since we don't know the
+- * number of queues at compile-time.  The polling_netdev array is
+- * intended for Multiqueue, but should work fine with a single queue.
++ * number of queues at compile-time.
+  **/
+ 
+ static int __devinit
+@@ -1158,15 +1143,6 @@ iegbe_alloc_queues(struct iegbe_adapter 
+ 		return -ENOMEM;
+ 	}
+ 
+-	adapter->polling_netdev = kcalloc(adapter->num_rx_queues,
+-	                                  sizeof(struct net_device),
+-	                                  GFP_KERNEL);
+-	if (!adapter->polling_netdev) {
+-		kfree(adapter->tx_ring);
+-		kfree(adapter->rx_ring);
+-		return -ENOMEM;
+-	}
+-
+     return E1000_SUCCESS;
+ }
+ 

package/ep80579-drivers/patches/103-iegbe_convert_unicast_addr_list.patch

@@ -0,0 +1,60 @@
+--- a/Embedded/src/GbE/iegbe_main.c
++++ b/Embedded/src/GbE/iegbe_main.c
+@@ -2161,7 +2161,8 @@ static void iegbe_set_rx_mode(struct net
+ {
+ 	struct iegbe_adapter *adapter = netdev_priv(netdev);
+ 	struct iegbe_hw *hw = &adapter->hw;
+-	struct dev_addr_list *uc_ptr;
++	struct netdev_hw_addr *ha;
++	bool use_uc = false;
+ 	struct dev_addr_list *mc_ptr;
+ 	u32 rctl;
+ 	u32 hash_value;
+@@ -2187,12 +2188,11 @@ int mta_reg_count = E1000_NUM_MTA_REGIST
+ 		}
+ 	}
+ 
+-	uc_ptr = NULL;
+ 	if (netdev->uc_count > rar_entries - 1) {
+ 		rctl |= E1000_RCTL_UPE;
+ 	} else if (!(netdev->flags & IFF_PROMISC)) {
+ 		rctl &= ~E1000_RCTL_UPE;
+-		uc_ptr = netdev->uc_list;
++		use_uc = true;
+ 	}
+ 
+ 	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
+@@ -2210,13 +2210,20 @@ int mta_reg_count = E1000_NUM_MTA_REGIST
+ 	 * if there are not 14 addresses, go ahead and clear the filters
+ 	 * -- with 82571 controllers only 0-13 entries are filled here
+ 	 */
++	i = 1;
++	if (use_uc)
++		list_for_each_entry(ha, &netdev->uc_list, list) {
++			if (i == rar_entries)
++				break;
++			iegbe_rar_set(hw, ha->addr, i++);
++		}
++
++	WARN_ON(i == rar_entries);
++
+ 	mc_ptr = netdev->mc_list;
+ 
+-	for (i = 1; i < rar_entries; i++) {
+-		if (uc_ptr) {
+-			iegbe_rar_set(hw, uc_ptr->da_addr, i);
+-			uc_ptr = uc_ptr->next;
+-		} else if (mc_ptr) {		
++	for (; i < rar_entries; i++) {
++		if (mc_ptr) {
+ 			iegbe_rar_set(hw, mc_ptr->da_addr, i);
+ 			mc_ptr = mc_ptr->next;
+ 		} else {
+@@ -2226,7 +2233,6 @@ int mta_reg_count = E1000_NUM_MTA_REGIST
+ 			E1000_WRITE_FLUSH(&adapter->hw);
+ 		}
+ 	}
+-	WARN_ON(uc_ptr != NULL);
+ 
+ 	/* clear the old settings from the multicast hash table */
+ 

package/ep80579-drivers/patches/104-iegbe_group_address_list_and_its_count.patch

@@ -0,0 +1,20 @@
+--- a/Embedded/src/GbE/iegbe_main.c
++++ b/Embedded/src/GbE/iegbe_main.c
+@@ -2188,7 +2188,7 @@ int mta_reg_count = E1000_NUM_MTA_REGIST
+ 		}
+ 	}
+ 
+-	if (netdev->uc_count > rar_entries - 1) {
++	if (netdev->uc.count > rar_entries - 1) {
+ 		rctl |= E1000_RCTL_UPE;
+ 	} else if (!(netdev->flags & IFF_PROMISC)) {
+ 		rctl &= ~E1000_RCTL_UPE;
+@@ -2212,7 +2212,7 @@ int mta_reg_count = E1000_NUM_MTA_REGIST
+ 	 */
+ 	i = 1;
+ 	if (use_uc)
+-		list_for_each_entry(ha, &netdev->uc_list, list) {
++		list_for_each_entry(ha, &netdev->uc.list, list) {
+ 			if (i == rar_entries)
+ 				break;
+ 			iegbe_rar_set(hw, ha->addr, i++);

package/ep80579-drivers/patches/105-iegbe_new_dma_masks.patch

@@ -0,0 +1,20 @@
+--- a/Embedded/src/GbE/iegbe_main.c
++++ b/Embedded/src/GbE/iegbe_main.c
+@@ -775,13 +775,13 @@ static int __devinit iegbe_probe(struct 
+ 	if (err)
+         return err;
+ 
+-	if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
+-	    !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
++	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
++	    !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
+ 		pci_using_dac = 1;
+         } else {
+-             err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
++             err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
+    	     if (err) {
+-			err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
++			err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
+ 			if (err) {
+ 				E1000_ERR("No usable DMA configuration, "
+ 					  "aborting\n");

package/ep80579-drivers/patches/106-iegbe_new_irqf_constant.patch

@@ -0,0 +1,12 @@
+--- a/Embedded/src/GbE/iegbe_ethtool.c
++++ b/Embedded/src/GbE/iegbe_ethtool.c
+@@ -944,7 +944,8 @@ iegbe_intr_test(struct iegbe_adapter *ad
+     *data = 0;
+ 
+     /* Hook up test interrupt handler just for this test */
+-     if(!request_irq(irq, &iegbe_test_intr, 0, netdev->name, netdev)) {
++     if(!request_irq(irq, &iegbe_test_intr, IRQF_PROBE_SHARED, netdev->name,
++			netdev)) {
+          shared_int = FALSE;
+      } else if(request_irq(irq, &iegbe_test_intr, IRQF_SHARED,
+                   netdev->name, netdev)){

package/ep80579-drivers/patches/150-ocracoke_island.patch

@@ -0,0 +1,747 @@
+--- a/Embedded/src/GbE/iegbe_oem_phy.c
++++ b/Embedded/src/GbE/iegbe_oem_phy.c
+@@ -65,6 +65,10 @@ static int32_t iegbe_oem_link_m88_setup(
+ static int32_t iegbe_oem_set_phy_mode(struct iegbe_hw *hw);
+ static int32_t iegbe_oem_detect_phy(struct iegbe_hw *hw);
+ 
++static int32_t iegbe_oem_link_bcm5481_setup(struct iegbe_hw *hw);
++static int32_t bcm5481_read_18sv (struct iegbe_hw *hw, int sv, uint16_t *data);
++static int32_t oi_phy_setup (struct iegbe_hw *hw);
++
+ /**
+  * iegbe_oem_setup_link
+  * @hw: iegbe_hw struct containing device specific information
+@@ -114,6 +118,10 @@ iegbe_oem_setup_link(struct iegbe_hw *hw
+     }
+ 
+     switch (hw->phy_id) {
++	case BCM5395S_PHY_ID:
++		return E1000_SUCCESS;
++		break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
+             ret_val = iegbe_oem_link_m88_setup(hw);
+@@ -121,6 +129,12 @@ iegbe_oem_setup_link(struct iegbe_hw *hw
+                 return ret_val; 
+             }
+         break; 
++	case BCM5481_PHY_ID:
++		ret_val = iegbe_oem_link_bcm5481_setup(hw);
++		if(ret_val) { 
++			return ret_val; 
++		}
++		break; 
+         default:
+             DEBUGOUT("Invalid PHY ID\n");
+             return -E1000_ERR_PHY_TYPE;
+@@ -179,6 +193,51 @@ iegbe_oem_setup_link(struct iegbe_hw *hw
+ #endif /* ifdef EXTERNAL_MDIO */
+ }
+ 
++/**
++ * iegbe_oem_link_bcm5481_setup
++ * @hw: iegbe_hw struct containing device specific information
++ *
++ * Returns E1000_SUCCESS, negative E1000 error code on failure
++ *
++ * copied verbatim from iegbe_oem_link_m88_setup
++ **/
++static int32_t
++iegbe_oem_link_bcm5481_setup(struct iegbe_hw *hw)
++{
++	int32_t ret_val;
++	uint16_t phy_data;
++
++	//DEBUGFUNC(__func__);
++
++	if(!hw)
++		return -1;
++
++	/* phy_reset_disable is set in iegbe_oem_set_phy_mode */
++	if(hw->phy_reset_disable)
++		return E1000_SUCCESS;
++
++	// Enable MDIX in extended control reg.
++	ret_val = iegbe_oem_read_phy_reg_ex(hw, BCM5481_ECTRL, &phy_data);
++	if(ret_val)
++	{
++		DEBUGOUT("Unable to read BCM5481_ECTRL register\n");
++		return ret_val;
++	}
++
++	phy_data &= ~BCM5481_ECTRL_DISMDIX;
++	ret_val = iegbe_oem_write_phy_reg_ex(hw, BCM5481_ECTRL, phy_data);
++	if(ret_val)
++	{
++		DEBUGOUT("Unable to write BCM5481_ECTRL register\n");
++		return ret_val;
++	}
++
++	ret_val = oi_phy_setup (hw);
++	if (ret_val)
++		return ret_val;
++
++	return E1000_SUCCESS;
++}
+ 
+ /**
+  * iegbe_oem_link_m88_setup
+@@ -340,6 +399,11 @@ iegbe_oem_force_mdi(struct iegbe_hw *hw,
+      * see iegbe_phy_force_speed_duplex, which does the following for M88
+      */
+       switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++		case BCM5481_PHY_ID:
++			DEBUGOUT("WARNING: An empty iegbe_oem_force_mdi() has been called!\n");
++			break;
++
+           case M88E1000_I_PHY_ID:
+           case M88E1141_E_PHY_ID:
+               ret_val = iegbe_oem_read_phy_reg_ex(hw, 
+@@ -415,6 +479,8 @@ iegbe_oem_phy_reset_dsp(struct iegbe_hw 
+      switch (hw->phy_id) {
+          case M88E1000_I_PHY_ID:
+          case M88E1141_E_PHY_ID:
++		case BCM5481_PHY_ID:
++		case BCM5395S_PHY_ID:
+              DEBUGOUT("No DSP to reset on OEM PHY\n");
+          break;
+          default:
+@@ -460,6 +526,11 @@ iegbe_oem_cleanup_after_phy_reset(struct
+      * see iegbe_phy_force_speed_duplex, which does the following for M88
+      */
+     switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++		case BCM5481_PHY_ID:
++            DEBUGOUT("WARNING: An empty iegbe_oem_cleanup_after_phy_reset() has been called!\n");
++        break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
+             /*
+@@ -573,6 +644,11 @@ iegbe_oem_set_phy_mode(struct iegbe_hw *
+      * use iegbe_set_phy_mode as example
+      */
+     switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++		case BCM5481_PHY_ID:
++             DEBUGOUT("WARNING: An empty iegbe_oem_set_phy_mode() has been called!\n");
++         break;
++
+          case M88E1000_I_PHY_ID:
+          case M88E1141_E_PHY_ID:
+              ret_val = iegbe_read_eeprom(hw, 
+@@ -641,6 +717,19 @@ iegbe_oem_detect_phy(struct iegbe_hw *hw
+     }
+     hw->phy_type = iegbe_phy_oem;
+ 
++{
++	// If MAC2 (BCM5395 switch), manually detect the phy
++	struct iegbe_adapter *adapter;
++	uint32_t device_number;
++	adapter = (struct iegbe_adapter *) hw->back;
++	device_number = PCI_SLOT(adapter->pdev->devfn);
++	if (device_number == ICP_XXXX_MAC_2) {
++		hw->phy_id = BCM5395S_PHY_ID;
++		hw->phy_revision = 0;
++		return E1000_SUCCESS;
++	}
++}
++
+     ret_val = iegbe_oem_read_phy_reg_ex(hw, PHY_ID1, &phy_id_high);
+     if(ret_val) {
+         DEBUGOUT("Unable to read PHY register PHY_ID1\n");
+@@ -690,6 +779,8 @@ iegbe_oem_get_tipg(struct iegbe_hw *hw)
+     switch (hw->phy_id) {
+          case M88E1000_I_PHY_ID:
+          case M88E1141_E_PHY_ID:
++		case BCM5481_PHY_ID:
++		case BCM5395S_PHY_ID:
+              phy_num = DEFAULT_ICP_XXXX_TIPG_IPGT;
+          break;
+          default:
+@@ -738,6 +829,8 @@ iegbe_oem_phy_is_copper(struct iegbe_hw 
+     switch (hw->phy_id) {
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
++		case BCM5481_PHY_ID:
++		case BCM5395S_PHY_ID:
+             isCopper = TRUE;
+         break;
+         default:
+@@ -796,13 +889,13 @@ iegbe_oem_get_phy_dev_number(struct iegb
+ 	switch(device_number)
+     {
+       case ICP_XXXX_MAC_0: 
+-	      hw->phy_addr = 0x00;
++	      hw->phy_addr = 0x01;
+ 	  break;
+       case ICP_XXXX_MAC_1: 
+-	      hw->phy_addr = 0x01;
++	      hw->phy_addr = 0x02;
+ 	  break;
+       case ICP_XXXX_MAC_2: 
+-	      hw->phy_addr = 0x02;
++	      hw->phy_addr = 0x00;
+ 	  break;
+ 	  default:  hw->phy_addr = 0x00;
+     }
+@@ -851,6 +944,12 @@ iegbe_oem_mii_ioctl(struct iegbe_adapter
+     if(!adapter || !ifr) {
+         return -1;
+     }
++
++	// If MAC2 (BCM5395 switch) then leave now
++	if ((PCI_SLOT(adapter->pdev->devfn)) == ICP_XXXX_MAC_2) {
++			return -1;
++	}
++
+     switch (data->reg_num) {
+         case PHY_CTRL:
+             if(mii_reg & MII_CR_POWER_DOWN) {
+@@ -987,6 +1086,11 @@ void iegbe_oem_get_phy_regs(struct iegbe
+      * [10] = mdix mode
+      */
+     switch (adapter->hw.phy_id) {
++	case BCM5395S_PHY_ID:
++	case BCM5481_PHY_ID:
++		DEBUGOUT("WARNING: An empty iegbe_oem_get_phy_regs() has been called!\n");
++	break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
+             if(corrected_len > 0) {
+@@ -1068,8 +1172,13 @@ iegbe_oem_phy_loopback(struct iegbe_adap
+      * Loopback configuration is the same for each of the supported PHYs.
+      */
+     switch (adapter->hw.phy_id) {
++		case BCM5395S_PHY_ID:
++			DEBUGOUT("WARNING: An empty iegbe_oem_phy_loopback() has been called!\n");
++			break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
++		case BCM5481_PHY_ID:
+ 
+           adapter->hw.autoneg = FALSE;
+ 
+@@ -1182,8 +1291,14 @@ iegbe_oem_loopback_cleanup(struct iegbe_
+     }
+ 
+     switch (adapter->hw.phy_id) {
++		case BCM5395S_PHY_ID:
++		DEBUGOUT("WARNING: An empty iegbe_oem_loopback_cleanup() has been called!\n");
++		return;
++		break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
++		case BCM5481_PHY_ID:
+         default:
+             adapter->hw.autoneg = TRUE;
+         
+@@ -1243,6 +1358,11 @@ iegbe_oem_phy_speed_downgraded(struct ie
+      */
+ 
+     switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++		case BCM5481_PHY_ID:
++			*isDowngraded = 0;
++			break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
+             ret_val = iegbe_oem_read_phy_reg_ex(hw, M88E1000_PHY_SPEC_STATUS, 
+@@ -1305,6 +1425,11 @@ iegbe_oem_check_polarity(struct iegbe_hw
+      */
+ 
+     switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++		case BCM5481_PHY_ID:
++			*polarity = 0;
++			break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
+             /* return the Polarity bit in the Status register. */
+@@ -1367,6 +1492,25 @@ iegbe_oem_phy_is_full_duplex(struct iegb
+      */
+         
+       switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++			/* Always full duplex */
++			*isFD = 1;
++			break;
++
++		case BCM5481_PHY_ID:
++			ret_val = iegbe_read_phy_reg(hw, BCM5481_ASTAT, &phy_data);
++			if(ret_val) return ret_val;
++
++				switch (BCM5481_ASTAT_HCD(phy_data)) {
++					case BCM5481_ASTAT_1KBTFD:
++					case BCM5481_ASTAT_100BTXFD:
++						*isFD = 1;
++						break;
++					default:
++						*isFD = 0;
++				}
++			break;
++
+           case M88E1000_I_PHY_ID:
+           case M88E1141_E_PHY_ID:
+              ret_val = iegbe_oem_read_phy_reg_ex(hw, M88E1000_PHY_SPEC_STATUS,
+@@ -1423,6 +1567,25 @@ iegbe_oem_phy_is_speed_1000(struct iegbe
+      */
+ 
+     switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++			/* Always 1000mb */
++			*is1000 = 1;
++			break;
++
++		case BCM5481_PHY_ID:
++			ret_val = iegbe_read_phy_reg(hw, BCM5481_ASTAT, &phy_data);
++			if(ret_val) return ret_val;
++
++				switch (BCM5481_ASTAT_HCD(phy_data)) {
++					case BCM5481_ASTAT_1KBTFD:
++					case BCM5481_ASTAT_1KBTHD:
++						*is1000 = 1;
++					break;
++				default:
++					*is1000 = 0;
++				}
++			break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
+             ret_val = iegbe_oem_read_phy_reg_ex(hw, M88E1000_PHY_SPEC_STATUS, 
+@@ -1478,6 +1641,25 @@ iegbe_oem_phy_is_speed_100(struct iegbe_
+      * see iegbe_config_mac_to_phy
+      */
+     switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++			/* Always 1000Mb, never 100mb */
++			*is100 = 0;
++			break;
++
++		case BCM5481_PHY_ID:
++			ret_val = iegbe_read_phy_reg(hw, BCM5481_ASTAT, &phy_data);
++			if(ret_val) return ret_val;
++
++			switch (BCM5481_ASTAT_HCD(phy_data)) {
++				case BCM5481_ASTAT_100BTXFD:
++				case BCM5481_ASTAT_100BTXHD:
++					*is100 = 1;
++					break;
++				default:
++					*is100 = 0;
++			}
++			break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
+             ret_val = iegbe_oem_read_phy_reg_ex(hw, 
+@@ -1535,6 +1717,11 @@ iegbe_oem_phy_get_info(struct iegbe_hw *
+      * see iegbe_phy_m88_get_info
+      */
+     switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++		case BCM5481_PHY_ID:
++			DEBUGOUT("WARNING: An empty iegbe_oem_phy_get_info() has been called!\n");
++			break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
+   /* The downshift status is checked only once, after link is
+@@ -1636,8 +1823,13 @@ iegbe_oem_phy_hw_reset(struct iegbe_hw *
+      * the M88 used in truxton. 
+      */
+     switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++			DEBUGOUT("WARNING: An empty iegbe_oem_phy_hw_reset() has been called!\n");
++			break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
++		case BCM5481_PHY_ID:
+             ret_val = iegbe_oem_read_phy_reg_ex(hw, PHY_CTRL, &phy_data);
+             if(ret_val) {
+                 DEBUGOUT("Unable to read register PHY_CTRL\n");
+@@ -1699,6 +1891,8 @@ iegbe_oem_phy_init_script(struct iegbe_h
+     switch (hw->phy_id) {
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
++		case BCM5481_PHY_ID:
++		case BCM5395S_PHY_ID:
+             DEBUGOUT("Nothing to do for OEM PHY Init");
+         break;
+         default:
+@@ -1735,6 +1929,11 @@ iegbe_oem_read_phy_reg_ex(struct iegbe_h
+         return -1;
+     }
+ 
++	if (hw->phy_id == BCM5395S_PHY_ID) {
++		DEBUGOUT("WARNING: iegbe_oem_read_phy_reg_ex() has been unexpectedly called!\n");
++		return -1;
++	}
++
+     /* call the GCU func that will read the phy
+      * 
+      * Make note that the M88 phy is what'll be used on Truxton.
+@@ -1782,6 +1981,11 @@ iegbe_oem_set_trans_gasket(struct iegbe_
+     }
+ 
+      switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++		case BCM5481_PHY_ID:
++			DEBUGOUT("WARNING: An empty iegbe_oem_set_trans_gasket() has been called!\n");
++			break;
++
+          case M88E1000_I_PHY_ID:
+          case M88E1141_E_PHY_ID:
+          /* Gasket set correctly for Marvell Phys, so nothing to do */
+@@ -1886,6 +2090,8 @@ iegbe_oem_phy_needs_reset_with_mac(struc
+     switch (hw->phy_id) {
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
++		case BCM5481_PHY_ID:
++		case BCM5395S_PHY_ID:
+             ret_val = FALSE;
+         break;
+         default:
+@@ -1935,6 +2141,8 @@ iegbe_oem_config_dsp_after_link_change(s
+     switch (hw->phy_id) {
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
++		case BCM5481_PHY_ID:
++		case BCM5395S_PHY_ID:
+             DEBUGOUT("No DSP to configure on OEM PHY");
+         break;
+         default:
+@@ -1978,6 +2186,12 @@ iegbe_oem_get_cable_length(struct iegbe_
+     }
+ 
+     switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++		case BCM5481_PHY_ID:
++			*min_length = 0;
++			*max_length = iegbe_igp_cable_length_150;
++			break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
+             ret_val = iegbe_oem_read_phy_reg_ex(hw, 
+@@ -2061,6 +2275,23 @@ iegbe_oem_phy_is_link_up(struct iegbe_hw
+      */
+ 
+     switch (hw->phy_id) {
++		case BCM5395S_PHY_ID:
++			/* Link always up */
++			*isUp = TRUE;
++			return E1000_SUCCESS;
++			break;
++
++		case BCM5481_PHY_ID:
++			iegbe_oem_read_phy_reg_ex(hw, BCM5481_ESTAT, &phy_data);
++			ret_val = iegbe_oem_read_phy_reg_ex(hw, BCM5481_ESTAT, &phy_data);
++			if(ret_val)
++			{
++				DEBUGOUT("Unable to read PHY register BCM5481_ESTAT\n");
++				return ret_val;
++			}
++			statusMask = BCM5481_ESTAT_LINK;
++			break;
++
+         case M88E1000_I_PHY_ID:
+         case M88E1141_E_PHY_ID:
+             iegbe_oem_read_phy_reg_ex(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 
+@@ -2092,3 +2323,210 @@ iegbe_oem_phy_is_link_up(struct iegbe_hw
+ #endif /* ifdef EXTERNAL_MDIO */
+ }
+ 
++
++
++//-----
++// Read BCM5481 expansion register
++//
++int32_t
++bcm5481_read_ex (struct iegbe_hw *hw, uint16_t reg, uint16_t *data)
++{
++	int ret;
++	uint16_t selector;
++	uint16_t reg_data;
++
++	// Get the current value of bits 15:12
++	ret = iegbe_oem_read_phy_reg_ex (hw, 0x15, &selector);
++	if (ret)
++		return ret;
++
++	// Select the expansion register
++	selector &= 0xf000;
++	selector |= (0xf << 8) | (reg);
++	iegbe_oem_write_phy_reg_ex (hw, 0x17, selector);
++
++	// Read the expansion register
++	ret = iegbe_oem_read_phy_reg_ex (hw, 0x15, &reg_data);
++
++	// De-select the expansion registers.
++	selector &= 0xf000;
++	iegbe_oem_write_phy_reg_ex (hw, 0x17, selector);
++
++	if (ret)
++		return ret;
++
++	*data = reg_data;
++	return ret;
++}
++
++//-----
++//	Read reg 0x18 sub-register
++//
++static int32_t
++bcm5481_read_18sv (struct iegbe_hw *hw, int sv, uint16_t *data)
++{
++	int	ret;
++	uint16_t	tmp_data;
++
++	// Select reg 0x18, sv
++	tmp_data = ((sv & BCM5481_R18H_SV_MASK) << 12) | BCM5481_R18H_SV_MCTRL;
++	ret = iegbe_oem_write_phy_reg_ex (hw, BCM5481_R18H, tmp_data);
++	if(ret)
++		return ret;
++
++	// Read reg 0x18, sv
++	ret = iegbe_oem_read_phy_reg_ex (hw, BCM5481_R18H, &tmp_data);
++	if(ret)
++		return ret;
++
++	*data = tmp_data;
++	return ret;
++}
++
++//-----
++//	Read reg 0x1C sub-register
++//
++int32_t
++bcm5481_read_1csv (struct iegbe_hw *hw, int sv, uint16_t *data)
++{
++	int ret;
++	uint16_t tmp_data;
++
++	// Select reg 0x1c, sv
++	tmp_data = ((sv & BCM5481_R1CH_SV_MASK) << BCM5481_R1CH_SV_SHIFT);
++
++	ret = iegbe_oem_write_phy_reg_ex (hw, BCM5481_R1CH, tmp_data);
++	if(ret)
++		return ret;
++
++	// Read reg 0x1c, sv
++	ret = iegbe_oem_read_phy_reg_ex (hw, BCM5481_R1CH, &tmp_data);
++	if(ret)
++		return ret;
++
++	*data = tmp_data;
++	return ret;
++}
++
++//-----
++//	Read-modify-write a 0x1C register.
++//
++//	hw   - hardware access info.
++//	reg  - 0x1C register to modify.
++//	data - bits which should be set.
++//	mask - the '1' bits in this argument will be cleared in the data
++//         read from 'reg' then 'data' will be or'd in and the result
++//         will be written to 'reg'.
++
++int32_t
++bcm5481_rmw_1csv (struct iegbe_hw *hw, uint16_t reg, uint16_t data, uint16_t mask)
++{
++	int32_t		ret;
++	uint16_t	reg_data;
++
++	ret = 0;
++
++	ret = bcm5481_read_1csv (hw, reg, &reg_data);
++	if (ret)
++	{
++		DEBUGOUT("Unable to read BCM5481 1CH register\n");
++		printk (KERN_ERR "Unable to read BCM5481 1CH register [0x%x]\n", reg);
++		return ret;
++	}
++
++	reg_data &= ~mask;
++	reg_data |= (BCM5481_R1CH_WE | data);
++
++	ret = iegbe_oem_write_phy_reg_ex (hw, BCM5481_R1CH, reg_data);
++	if(ret)
++	{
++		DEBUGOUT("Unable to write BCM5481 1CH register\n");
++		printk (KERN_ERR "Unable to write BCM5481 1CH register\n");
++		return ret;
++	}
++
++	return ret;
++}
++
++int32_t
++oi_phy_setup (struct iegbe_hw *hw)
++{
++	int	ret;
++	uint16_t	pmii_data;
++	uint16_t	mctrl_data;
++	uint16_t	cacr_data;
++
++	ret = 0;
++
++	// Set low power mode via reg 0x18, sv010, bit 6
++	// Do a read-modify-write on reg 0x18, sv010 register to preserve existing bits.
++	ret = bcm5481_read_18sv (hw, BCM5481_R18H_SV_PMII, &pmii_data);
++	if (ret)
++	{
++		DEBUGOUT("Unable to read BCM5481_R18H_SV_PMII register\n");
++		printk (KERN_ERR "Unable to read BCM5481_R18H_SV_PMII register\n");
++		return ret;
++	}
++
++	// Set the LPM bit in the data just read and write back to sv010
++	// The shadow register select bits [2:0] are set by reading the sv010
++	// register.
++	pmii_data |= BCM5481_R18H_SV010_LPM;
++	ret = iegbe_oem_write_phy_reg_ex (hw, BCM5481_R18H, pmii_data);
++	if(ret)
++	{
++		DEBUGOUT("Unable to write BCM5481_R18H register\n");
++		printk (KERN_ERR "Unable to write BCM5481_R18H register\n");
++		return ret;
++	}
++
++
++	// Set the RGMII RXD to RXC skew bit in reg 0x18, sv111
++
++	if (bcm5481_read_18sv (hw, BCM5481_R18H_SV_MCTRL, &mctrl_data))
++	{
++		DEBUGOUT("Unable to read BCM5481_R18H_SV_MCTRL register\n");
++		printk (KERN_ERR "Unable to read BCM5481_R18H_SV_MCTRL register\n");
++		return ret;
++	}
++	mctrl_data |= (BCM5481_R18H_WE | BCM5481_R18H_SV111_SKEW);
++
++	ret = iegbe_oem_write_phy_reg_ex (hw, BCM5481_R18H, mctrl_data);
++	if(ret)
++	{
++		DEBUGOUT("Unable to write BCM5481_R18H register\n");
++		printk (KERN_ERR "Unable to write BCM5481_R18H register\n");
++		return ret;
++	}
++
++	// Enable RGMII transmit clock delay in reg 0x1c, sv00011
++	ret = bcm5481_read_1csv (hw, BCM5481_R1CH_CACR, &cacr_data);
++	if (ret)
++	{
++		DEBUGOUT("Unable to read BCM5481_R1CH_CACR register\n");
++		printk (KERN_ERR "Unable to read BCM5481_R1CH_CACR register\n");
++		return ret;
++	}
++
++	cacr_data |= (BCM5481_R1CH_WE | BCM5481_R1CH_CACR_TCD);
++
++	ret = iegbe_oem_write_phy_reg_ex (hw, BCM5481_R1CH, cacr_data);
++	if(ret)
++	{
++		DEBUGOUT("Unable to write BCM5481_R1CH register\n");
++		printk (KERN_ERR "Unable to write BCM5481_R1CH register\n");
++		return ret;
++	}
++
++	// Enable dual link speed indication (0x1c, sv 00010, bit 2)
++	ret = bcm5481_rmw_1csv (hw, BCM5481_R1CH_SC1, BCM5481_R1CH_SC1_LINK, BCM5481_R1CH_SC1_LINK);
++	if (ret)
++		return ret;
++
++	// Enable link and activity on ACTIVITY LED (0x1c, sv 01001, bit 4=1, bit 3=0)
++	ret = bcm5481_rmw_1csv (hw, BCM5481_R1CH_LCTRL, BCM5481_R1CH_LCTRL_ALEN, BCM5481_R1CH_LCTRL_ALEN | BCM5481_R1CH_LCTRL_AEN);
++	if (ret)
++		return ret;
++
++	return ret;
++}
+--- a/Embedded/src/GbE/iegbe_oem_phy.h
++++ b/Embedded/src/GbE/iegbe_oem_phy.h
+@@ -95,6 +95,8 @@ int32_t iegbe_oem_phy_is_link_up(struct 
+ 
+ #define DEFAULT_ICP_XXXX_TIPG_IPGT 8      /* Inter Packet Gap Transmit Time */
+ #define ICP_XXXX_TIPG_IPGT_MASK 0x000003FFUL 
++#define BCM5481_PHY_ID		0x0143BCA0
++#define BCM5395S_PHY_ID		0x0143BCF0
+ 
+ /* Miscellaneous defines */
+ #ifdef IEGBE_10_100_ONLY
+@@ -103,5 +105,65 @@ int32_t iegbe_oem_phy_is_link_up(struct 
+     #define ICP_XXXX_AUTONEG_ADV_DEFAULT	0x2F
+ #endif
+ 
++/* BCM5481 specifics */
++
++#define BCM5481_ECTRL		(0x10)
++#define BCM5481_ESTAT		(0x11)
++#define BCM5481_RXERR		(0x12)
++#define BCM5481_EXPRW		(0x15)
++#define BCM5481_EXPACC		(0x17)
++#define BCM5481_ASTAT		(0x19)
++#define BCM5481_R18H		(0x18)
++#define BCM5481_R1CH		(0x1c)
++
++/* indirect register access via register 18h */
++
++#define BCM5481_R18H_SV_MASK	(7) // Mask for SV bits.
++#define BCM5481_R18H_SV_ACTRL	(0) // SV000 Aux. control
++#define BCM5481_R18H_SV_10BT	(1) // SV001 10Base-T
++#define BCM5481_R18H_SV_PMII	(2) // SV010 Power/MII control
++#define BCM5481_R18H_SV_MTEST	(4) // SV100 Misc. test
++#define BCM5481_R18H_SV_MCTRL	(7) // SV111 Misc. control
++
++#define BCM5481_R18H_SV001_POL	(1 << 13) // Polarity
++#define BCM5481_R18H_SV010_LPM	(1 << 6)
++#define BCM5481_R18H_SV111_SKEW	(1 << 8)
++#define BCM5481_R18H_WE		(1 << 15) // Write enable
++
++// 0x1c registers
++#define BCM5481_R1CH_SV_SHIFT	(10)
++#define BCM5481_R1CH_SV_MASK	(0x1f)
++#define BCM5481_R1CH_SC1	(0x02) // sv00010 Spare control 1
++#define BCM5481_R1CH_CACR	(0x03) // sv00011 Clock alignment control
++#define BCM5481_R1CH_LCTRL	(0x09) // sv01001 LED control
++#define BCM5481_R1CH_LEDS1	(0x0d) // sv01101 LED selector 1
++
++// 0x1c common
++#define BCM5481_R1CH_WE		(1 << 15) // Write enable
++
++// 0x1c, sv 00010
++#define BCM5481_R1CH_SC1_LINK	(1 << 2) // sv00010 Linkspeed
++
++// 0x1c, sv 00011
++#define BCM5481_R1CH_CACR_TCD	(1 << 9) // sv00011 RGMII tx clock delay
++
++// 0x1c, sv 01001
++#define BCM5481_R1CH_LCTRL_ALEN	(1 << 4) // Activity/Link enable on ACTIVITY LED
++#define BCM5481_R1CH_LCTRL_AEN	(1 << 3) // Activity enable on ACTIVITY LED
++
++#define BCM5481_ECTRL_DISMDIX	(1 <<14)
++
++#define BCM5481_MCTRL_AUTOMDIX	(1 <<9)
++
++#define BCM5481_ESTAT_LINK	(1 << 8)
++
++#define BCM5481_ASTAT_ANC	(1 << 15)
++#define BCM5481_ASTAT_ANHCD	(7 << 8)
++#define BCM5481_ASTAT_HCD(x)	((x >> 8) & 7)
++#define BCM5481_ASTAT_1KBTFD	(0x7)
++#define BCM5481_ASTAT_1KBTHD	(0x6)
++#define BCM5481_ASTAT_100BTXFD	(0x5)
++#define BCM5481_ASTAT_100BTXHD	(0x3)
++
+ #endif /* ifndef _IEGBE_OEM_PHY_H_ */
+  

package/ep80579-drivers/patches/200-can_fix_ioctl_numbers.patch

@@ -0,0 +1,11 @@
+--- a/Embedded/src/CAN/icp_can_user.h
++++ b/Embedded/src/CAN/icp_can_user.h
+@@ -63,6 +63,8 @@
+ #ifndef __ICP_CAN_USER_H__
+ #define __ICP_CAN_USER_H__
+ 
++#include <linux/ioctl.h>
++
+ /*****************************************************************************
+  * Device IO control codes.
+  *****************************************************************************/

package/ep80579-drivers/patches/210-can_include_linux_fs_h.patch

@@ -0,0 +1,11 @@
+--- a/Embedded/src/CAN/can_main.c
++++ b/Embedded/src/CAN/can_main.c
+@@ -70,6 +70,8 @@
+ 
+ #include "can_main.h"
+ #include "can_ioctl.h"
++#include <linux/fs.h>
++
+ 
+ MODULE_AUTHOR("Intel(R) Corporation");
+ MODULE_DESCRIPTION("Controller Area Network Driver");

package/ep80579-drivers/patches/220-can_fix_irq_request.patch

@@ -0,0 +1,23 @@
+--- a/Embedded/src/CAN/can_main.c
++++ b/Embedded/src/CAN/can_main.c
+@@ -654,7 +654,7 @@ int can_dev_io(struct inode *inode, stru
+ /*****************************************************************************
+  * Interrupt handler.
+  *****************************************************************************/
+-irqreturn_t can_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
++irqreturn_t can_irq_handler(int irq, void *dev_id)
+ {
+     can_os_t *can_os = (can_os_t *) dev_id;
+     unsigned int int_status;
+--- a/Embedded/src/CAN/can_main.h
++++ b/Embedded/src/CAN/can_main.h
+@@ -165,8 +165,7 @@ int can_dev_io(
+ 
+ irqreturn_t can_irq_handler(
+     int irq, 
+-    void *dev_id, 
+-    struct pt_regs *regs);
++    void *dev_id);
+ 
+ void can_tasklet(
+     unsigned long arg

package/ep80579-drivers/patches/230-can_remove_driver_data_direct_access.patch

@@ -0,0 +1,41 @@
+diff -Nur a/Embedded/src/CAN/can_main.c b/Embedded/src/CAN/can_main.c
+--- a/Embedded/src/CAN/can_main.c	2009-11-30 10:44:39.044269751 +0100
++++ b/Embedded/src/CAN/can_main.c	2009-11-30 10:54:41.434355642 +0100
+@@ -213,8 +213,8 @@
+     spin_lock_init(&(g_can_os[can_num].int_spinlock));
+     spin_lock_init(&(g_can_os[can_num].open_spinlock));
+ 
+-    dev->dev.driver_data = (void *) &(g_can_os[can_num]);
+-    if (!dev->dev.driver_data)
++    dev_set_drvdata(&dev->dev, (void *) &(g_can_os[can_num]));
++    if (!dev_get_drvdata(&dev->dev))
+     {
+         printk("Couldn't create CAN device %d. Exiting.\n",
+             dev->device);
+@@ -236,7 +236,7 @@
+  *****************************************************************************/
+ void can_pci_remove(struct pci_dev *dev)
+ {
+-    can_os_t *can_os = dev->dev.driver_data;
++    can_os_t *can_os = dev_get_drvdata(&dev->dev);
+ 
+     iounmap(can_os->pci_remap);
+     icp_can_destroy(can_os->can);
+@@ -250,7 +250,7 @@
+ {
+     unsigned int i;
+     unsigned int int_status;
+-    can_os_t *can_os = dev->dev.driver_data;
++    can_os_t *can_os = dev_get_drvdata(&dev->dev);
+     int err;
+ 
+ 	/* Indicate that we are suspending */
+@@ -321,7 +321,7 @@
+ int can_pci_resume(struct pci_dev *dev)
+ {
+     unsigned int i;
+-    can_os_t *can_os = dev->dev.driver_data;
++    can_os_t *can_os = dev_get_drvdata(&dev->dev);
+ 
+ 	/* Restore PCI CFG space */
+ 	pci_restore_state(dev);

package/ep80579-drivers/patches/300-wdt_compile_fix.patch

@@ -0,0 +1,59 @@
+--- a/Embedded/src/WDT/iwdt.c
++++ b/Embedded/src/WDT/iwdt.c
+@@ -180,19 +180,19 @@ MODULE_PARM_DESC(wdt_scale, "Intel WDT s
+ module_param(wdt_intr_type, byte, WDT_INT_TYPE_IRQ);
+ MODULE_PARM_DESC(wdt_intr_type, "Intel WDT interrupt type (default SERIRQ).");
+ 
+-module_param(wdt_margin1, uint, TIMER_MARGIN);
++module_param(wdt_margin1, uint, 0);
+ MODULE_PARM_DESC(wdt_margin1, "First stage Intel WDT timeout in steps of 1 ms by default.");
+ 
+-module_param(wdt_margin2, uint, TIMER_MARGIN);
++module_param(wdt_margin2, uint, 0);
+ MODULE_PARM_DESC(wdt_margin2, "Second stage Intel WDT timeout in steps of 1 ms by default.");
+ 
+ module_param(nowayout, int, 0);
+ MODULE_PARM_DESC(nowayout, "Intel WDT can't be stopped once started (default=0)");
+ 
+-module_param(wdt_index_port, int, 0x4E);
++module_param(wdt_index_port, int, 0);
+ MODULE_PARM_DESC(wdt_index_port, "WDT Index Port (default 0x4e)");
+ 
+-module_param(wdt_data_port, int, 0x4E);
++module_param(wdt_data_port, int, 0);
+ MODULE_PARM_DESC(wdt_data_port, "WDT Data Port (default 0x4f)");
+ 
+ static int wdt_get_iobase(struct pci_dev *dev, u16 *iobase, int *irq);
+@@ -218,7 +218,7 @@ static ssize_t wdt_write(struct file *fi
+                      size_t count, loff_t * pos);
+ static int wdt_ioctl(struct inode *inode, struct file *file,
+                     unsigned int cmd, unsigned long arg);
+-static irqreturn_t wdt_isr(int irq, void *dev_id, struct pt_regs *regs);
++static irqreturn_t wdt_isr(int irq, void *dev_id);
+ static void __exit wdt_cleanup(void);
+ static int __init wdt_init(void);
+ static int __init wdt_init_one(struct pci_dev *dev,
+@@ -255,7 +255,7 @@ static struct pci_driver wdt_driver = {
+      name:        "iwdt",
+      id_table:     lpc_pci_tbl,
+      probe:        wdt_init_one,
+-     remove:        __devexit(wdt_remove_one),
++     remove:        __devexit_p(wdt_remove_one),
+      suspend:      wdt_pci_suspend,
+      resume:       wdt_pci_resume,
+ };
+@@ -1393,12 +1393,12 @@ static int wdt_ioctl(struct inode *inode
+ 
+ /*
+  * Function Name:   wdt_isr()
+- * Parameter:    int irq - irq number, void *dev_id, struct pt_regs *regs
++ * Parameter:    int irq - irq number, void *dev_id
+  * Return Value::   IRQ_NONE -  if the interrupt is not for wdt.
+  *           IRQ_HANDLED - if it is for wdt.
+  * Description:     This is the interrupt service routine of the WDT.
+  */
+-static irqreturn_t wdt_isr(int irq, void *dev_id, struct pt_regs *regs)
++static irqreturn_t wdt_isr(int irq, void *dev_id)
+ {
+      u8 val;
+ 

package/ep80579-drivers/patches/400-edma_fix_irq_request_warning.patch

@@ -0,0 +1,22 @@
+--- a/Embedded/src/EDMA/dma_linux.c
++++ b/Embedded/src/EDMA/dma_linux.c
+@@ -149,8 +149,7 @@ int32_t edma_suspend (struct pci_dev *de
+ int32_t edma_resume(struct pci_dev *dev);
+ int32_t initialize_edma_device(struct edma_device *device);
+ 
+-static irqreturn_t edma_irq_handler(int32_t irq, void * dev_id,
+-                                    struct pt_regs * regs);
++static irqreturn_t edma_irq_handler(int32_t irq, void * dev_id);
+ 
+ /* Prototypes - Misc. */
+ 
+@@ -429,8 +428,7 @@ int32_t edma_release(struct inode * inod
+  * Return Values: HANDLED = 1, NOT_HANDLED = 0
+  *****************************************************************************/
+ 
+-static irqreturn_t edma_irq_handler(int32_t irq, void * dev_id,
+-                                    struct pt_regs * regs)
++static irqreturn_t edma_irq_handler(int32_t irq, void * dev_id)
+ {
+ 
+     uint32_t clear_bits;

package/ep80579-drivers/patches/500-1588_fix_irq_request_warning.patch

@@ -0,0 +1,22 @@
+--- a/Embedded/src/1588/1588.c
++++ b/Embedded/src/1588/1588.c
+@@ -631,7 +631,7 @@ int restore_interrupts(void)
+       IRQ_NONE => this device did not interrupt
+ 
+ ******************************************************************************/
+-irqreturn_t timesync_isr(int irq, void *dev_id, struct pt_regs *regs)
++irqreturn_t timesync_isr(int irq, void *dev_id)
+ {
+     if ( !ixTimeSyncAccEventAmmsFlagGet() && !ixTimeSyncAccEventAsmsFlagGet()&&
+        !ixTimeSyncAccEventAtmFlagGet() && !ixTimeSyncAccEventPpsmFlagGet()&&
+--- a/Embedded/src/1588/1588.h
++++ b/Embedded/src/1588/1588.h
+@@ -128,7 +128,7 @@ int pci_suspend(struct pci_dev *dev, pm_
+ int pci_resume(struct pci_dev *dev);
+ int pci_probe(struct pci_dev *dev, const struct pci_device_id *id);
+ void pci_remove(struct pci_dev *dev);
+-irqreturn_t timesync_isr(int irq, void *dev_id, struct pt_regs *regs);
++irqreturn_t timesync_isr(int irq, void *dev_id);
+ 
+ // private functions
+ int save_reg_state(void);

package/ep80579-drivers/patches/600-2.6.27_includes.patch

@@ -0,0 +1,22 @@
+--- a/Embedded/src/CAN/can_main.h
++++ b/Embedded/src/CAN/can_main.h
+@@ -65,7 +65,7 @@
+ 
+ #include <linux/interrupt.h>
+ #include <linux/pci.h>
+-#include <asm/semaphore.h>
++#include <linux/semaphore.h>
+ #include <linux/spinlock.h>
+ #include <linux/cdev.h>
+ #include <asm/uaccess.h>
+--- a/Embedded/src/EDMA/dma_linux.c
++++ b/Embedded/src/EDMA/dma_linux.c
+@@ -87,7 +87,7 @@
+ #include <linux/fcntl.h>   /* O_ACCMODE */
+ #include <asm/system.h>    /* cli, *_flags */
+ #include <asm/uaccess.h>   /* copy_to_user */
+-#include <asm/semaphore.h>
++#include <linux/semaphore.h>
+ #include <asm/io.h>        /* inb(), outb() */
+ #include <linux/kmod.h>
+ #include <linux/ioport.h>  /* request_region */

package/ep80579-drivers/patches/601-2.6.32_includes.patch

@@ -0,0 +1,33 @@
+diff -Nur a/Embedded/src/1588/1588.c b/Embedded/src/1588/1588.c
+--- a/Embedded/src/1588/1588.c	2009-11-10 14:20:46.563322192 +0100
++++ b/Embedded/src/1588/1588.c	2009-11-30 10:44:22.144270452 +0100
+@@ -72,6 +72,7 @@
+  *
+  ****************************************************************************/
+ 
++#include <linux/sched.h>
+ #include "1588.h"
+ 
+ MODULE_AUTHOR("Intel(R) Corporation");
+diff -Nur a/Embedded/src/CAN/can_main.c b/Embedded/src/CAN/can_main.c
+--- a/Embedded/src/CAN/can_main.c	2009-11-10 14:20:46.563322192 +0100
++++ b/Embedded/src/CAN/can_main.c	2009-11-30 10:44:39.044269751 +0100
+@@ -68,6 +68,7 @@
+  *
+  **************************************************************************/
+ 
++#include <linux/sched.h>
+ #include "can_main.h"
+ #include "can_ioctl.h"
+ 
+diff -Nur a/Embedded/src/WDT/iwdt.c b/Embedded/src/WDT/iwdt.c
+--- a/Embedded/src/WDT/iwdt.c	2009-11-10 14:20:46.563322192 +0100
++++ b/Embedded/src/WDT/iwdt.c	2009-11-30 10:44:54.024262744 +0100
+@@ -137,6 +137,7 @@
+ #include <linux/watchdog.h>
+ #include <linux/miscdevice.h>
+ #include <linux/interrupt.h>
++#include <linux/sched.h>
+ #include "iwdt.h"
+ 
+ MODULE_AUTHOR("Intel(R) Corporation");

package/ep80579-drivers/patches/700-iegbe_kcompat_2.6.30.patch

@@ -0,0 +1,31 @@
+--- a/Embedded/src/GbE/kcompat.h
++++ b/Embedded/src/GbE/kcompat.h
+@@ -46,12 +46,6 @@ GPL LICENSE SUMMARY
+ #include <linux/sched.h>
+ #include <asm/io.h>
+ 
+-#ifndef IRQ_HANDLED
+-#define irqreturn_t void
+-#define IRQ_HANDLED
+-#define IRQ_NONE
+-#endif
+-
+ #ifndef SET_NETDEV_DEV
+ #define SET_NETDEV_DEV(net, pdev)
+ #endif
+@@ -748,6 +742,15 @@ extern void dump_stack(void);
+ 
+ #endif /* 2.4.24 */
+ 
++/*****************************************************************************/
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) )
++#ifndef IRQ_HANDLED
++#define irqreturn_t void
++#define IRQ_HANDLED
++#define IRQ_NONE
++#endif
++#endif /* < 2.6.30 */
++
+ #endif /* _KCOMPAT_H_ */
+ 
+  

package/ep80579-drivers/patches/701-iegbe_poll_dev.patch

@@ -0,0 +1,11 @@
+--- a/Embedded/src/GbE/iegbe_main.c
++++ b/Embedded/src/GbE/iegbe_main.c
+@@ -3534,7 +3534,7 @@ static int iegbe_clean(struct napi_struc
+ 	int tx_cleaned = 0, work_done = 0;
+ 
+ 	/* Must NOT use netdev_priv macro here. */
+-	adapter = poll_dev->priv;
++	adapter = netdev_priv(poll_dev);
+ 
+ 	/* iegbe_clean is called per-cpu.  This lock protects
+ 	 * tx_ring[0] from being cleaned by multiple cpus

package/hostapd/Makefile

@@ -25,6 +25,7 @@ PKG_BUILD_DEPENDS:= \
 PKG_CONFIG_DEPENDS:= \
 	CONFIG_WPA_SUPPLICANT_NO_TIMESTAMP_CHECK \
 	CONFIG_PACKAGE_kmod-ath9k \
+	CONFIG_PACKAGE_kmod-rt2800-lib \
 	CONFIG_PACKAGE_kmod-mac80211 \
 	CONFIG_PACKAGE_kmod-madwifi \
 	CONFIG_PACKAGE_hostapd \
@@ -50,11 +51,19 @@ PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSI
 
 include $(INCLUDE_DIR)/package.mk
 
+ifneq ($(CONFIG_PACKAGE_kmod-rt2800-lib),)
+  HOSTAPD_IEEE80211N:=y
+endif
+
+ifneq ($(CONFIG_PACKAGE_kmod-ath9k),)
+  HOSTAPD_IEEE80211N:=y
+endif
+
 DRIVER_MAKEOPTS= \
 	CONFIG_DRIVER_NL80211=$(CONFIG_PACKAGE_kmod-mac80211) \
 	CONFIG_DRIVER_MADWIFI=$(CONFIG_PACKAGE_kmod-madwifi) \
 	CONFIG_DRIVER_HOSTAP=$(CONFIG_PACKAGE_kmod-hostap) \
-	CONFIG_IEEE80211N=$(CONFIG_PACKAGE_kmod-ath9k) \
+	CONFIG_IEEE80211N=$(HOSTAPD_IEEE80211N) \
 	CONFIG_IEEE80211W=$(CONFIG_PACKAGE_kmod-ath9k)
 
 ifneq ($(LOCAL_TYPE),hostapd)

package/ifx-tapi/Config.in

@@ -0,0 +1,71 @@
+config VOICE_CPE_TAPI_FAX
+	bool "fax relay and modem support"
+	default n
+	help
+		Option to enable fax/modem support in TAPI.
+		Note: Newer platforms as AR9 and VR9 support a T.38 fax relay stack
+		in FW while older platforms like Danube or VINETIC-CPE require a
+		separate SW stack executed as an application.
+
+config VOICE_CPE_TAPI_CID
+	bool "CID support"
+	default y
+	help
+		Option to enable Caller ID support.
+
+config VOICE_CPE_TAPI_LT_GR909
+	bool "Linetesting GR-909 support"
+	default y
+		help
+			Option to enable linetesting GR-909.
+
+config VOICE_CPE_TAPI_DECT
+	bool "DECT encoding for COSIC modem"
+	default n
+		help
+			Option to enable DECT encoding for COSIC modem.
+
+config VOICE_CPE_TAPI_KPI
+	bool "KPI (Kernel Packet Interface)"
+	default y
+	help
+		Option to enable the generic kernel level packet interface
+		which allows accelerated packet transfer for various purposes.
+		The most important example is the QOS option, which allows
+		to redirect RTP packets directly into the IP stack.
+		Other options relying on KPI are DECT and HDLC.
+
+config VOICE_CPE_TAPI_QOS
+	bool "QOS for accelerated RTP packet handling"
+	default y
+	help
+		Option to enable an accelerated RTP packet transfer inside
+		the LINUX kernel space. This option requires the KPI2UDP
+		packet, which actually provides the OS specific hooks in
+		the IP stack.
+
+config VOICE_CPE_TAPI_STATISTICS
+	bool "TAPI statistics via /proc fs"
+	default y
+	help
+		Option to enable /proc fs statistics for packet counts etc.
+
+config VOICE_CPE_TAPI_METERING
+	bool "Metering (TTX) support"
+	default n
+	help
+		Option to enable metering (TTX) support.
+
+config VOICE_CPE_TAPI_HDLC
+	bool "PCM HDLC support, evaluation"
+	default n
+	help
+		Option to enable PCM HDLC framing inside the firmware, e.g. for
+		ISDN D-Channel access.
+
+config VOICE_CPE_TAPI_TRACES
+	bool "enable driver traces"
+	default y
+	help
+		enable driver traces with different trace levels to be
+		configured dynamically from the application or during insmod

package/ifx-tapi/Makefile

@@ -0,0 +1,70 @@
+#
+# Copyright (C) 2008 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=drv_tapi
+PKG_VERSION:=3.11.0
+PKG_RELEASE:=1
+
+PKG_SOURCE:=drv_tapi-$(PKG_VERSION).tar.gz
+PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
+PKG_MD5SUM:=1ffee83ce69f55915468c309d8ae2138
+
+include $(INCLUDE_DIR)/package.mk
+
+define KernelPackage/ifx-tapi
+  SUBMENU:=Voice over IP
+  TITLE:=Lantiq TAPI subsystem
+  URL:=http://www.lantiq.com/
+  MAINTAINER:=Lantiq
+  DEPENDS:=+kmod-ifxos @BROKEN
+  FILES:=$(PKG_BUILD_DIR)/src/drv_tapi.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,20,drv_tapi)
+endef
+
+define KernelPackage/ifx-tapi/description
+	Voice Subsystem Telephony API High Level Driver
+endef
+
+define KernelPackage/ifx-tapi/config
+	if PACKAGE_kmod-ifx-tapi
+		source "$(SOURCE)/Config.in"
+	endif
+endef
+
+CONFIGURE_ARGS += \
+	ARCH=$(LINUX_KARCH) \
+	--enable-linux-26 \
+	--enable-kernelbuild="$(LINUX_DIR)" \
+	--enable-kernelincl="$(LINUX_DIR)/include" \
+	--with-ifxos-incl=$(STAGING_DIR)/usr/include/ifxos \
+	$(call autoconf_bool,CONFIG_IFX_DRV_TAPI_EVENT_LOGGER,el-debug) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_FAX,fax t38) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_CID,cid) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_DECT,dect) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_KPI,kpi) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_QOS,qos) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_LT_GR909,lt) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_STATISTICS,statistics) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_METERING,metering) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_HDLC,hdlc) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_TRACES,trace)
+
+define Build/Configure
+	(cd $(PKG_BUILD_DIR); aclocal && autoconf && automake)
+	$(call Build/Configure/Default)
+endef
+
+define Build/InstallDev
+	$(INSTALL_DIR) $(1)/usr/include/drv_tapi
+	$(CP) --dereference $(PKG_BUILD_DIR)/include/* $(1)/usr/include/drv_tapi
+	(cd $(1)/usr/include/drv_tapi && ln -s . include && ln -s ../ifxos/ifx_types.h .)
+endef
+
+$(eval $(call KernelPackage,ifx-tapi))

package/ifx-tapi/patches/001-portability.patch

@@ -0,0 +1,26 @@
+--- a/src/Makefile.am
++++ b/src/Makefile.am
+@@ -149,7 +149,7 @@ if KERNEL_2_6
+ drv_tapi_OBJS = "$(subst .c,.o, $(drv_tapi_SOURCES))"
+ 
+ drv_tapi.ko: $(drv_tapi_SOURCES) $(EXTRA_DIST)
+-	@echo -e "Making Linux 2.6.x kernel object"
++	@echo "Making Linux 2.6.x kernel object"
+ 	@for f in $(drv_tapi_SOURCES) ; do \
+ 		if test ! -e $(PWD)/$$f; then \
+ 			echo "  LN      $$f" ; \
+@@ -157,10 +157,10 @@ drv_tapi.ko: $(drv_tapi_SOURCES) $(EXTRA
+ 			ln -s @abs_srcdir@/$$f $(PWD)/$$f; \
+ 		fi; \
+ 	done;
+-	@echo -e "# drv_tapi: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
+-	@echo -e "obj-m := $(subst .ko,.o,$@)"			>> $(PWD)/Kbuild
+-	@echo -e "$(subst .ko,,$@)-y := $(drv_tapi_OBJS)"	>> $(PWD)/Kbuild
+-	@echo -e "EXTRA_CFLAGS := -DHAVE_CONFIG_H  $(CFLAGS) $(drv_tapi_CFLAGS) $(INCLUDES)"	>> $(PWD)/Kbuild
++	@echo "# drv_tapi: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
++	@echo "obj-m := $(subst .ko,.o,$@)"			>> $(PWD)/Kbuild
++	@echo "$(subst .ko,,$@)-y := $(drv_tapi_OBJS)"	>> $(PWD)/Kbuild
++	@echo "EXTRA_CFLAGS := -DHAVE_CONFIG_H  $(CFLAGS) $(drv_tapi_CFLAGS) $(INCLUDES)"	>> $(PWD)/Kbuild
+ 	$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules
+ 
+ clean-generic:

package/ifx-tapi/patches/100-ifxmips.patch

@@ -0,0 +1,108 @@
+--- a/src/drv_tapi_linux.c
++++ b/src/drv_tapi_linux.c
+@@ -544,7 +544,7 @@ static ssize_t ifx_tapi_write (struct fi
+    IFX_uint8_t         *pData;
+    IFX_size_t           buf_size;
+ #endif /* TAPI_PACKET */
+-   IFX_ssize_t          size = 0;
++   ssize_t          size = 0;
+ 
+ #ifdef TAPI_PACKET
+    if (pTapiDev->bInitialized == IFX_FALSE)
+@@ -3600,7 +3600,11 @@ IFX_void_t TAPI_OS_ThreadKill(IFXOS_Thre
+             flag and released after the down() call. */
+          lock_kernel();
+          mb();
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
+          kill_proc(pThrCntrl->tid, SIGKILL, 1);
++#else
++         kill_pid(find_vpid(pThrCntrl->tid), SIGKILL, 1);
++#endif
+          /* release the big kernel lock */
+          unlock_kernel();
+          wait_for_completion (&pThrCntrl->thrCompletion);
+--- a/src/drv_tapi_osmap.h
++++ b/src/drv_tapi_osmap.h
+@@ -17,39 +17,6 @@
+ */
+ 
+ #include "ifx_types.h"     /* ifx type definitions */
+-
+-#ifndef HAVE_IFX_ULONG_T
+-   #warning please update your ifx_types.h, using local definition of IFX_ulong_t
+-   /* unsigned long type - valid for 32bit systems only */
+-   typedef unsigned long               IFX_ulong_t;
+-   #define HAVE_IFX_ULONG_T
+-#endif /* HAVE_IFX_ULONG_T */
+-
+-#ifndef HAVE_IFX_LONG_T
+-   #warning please update your ifx_types.h, using local definition of IFX_long_t
+-   /* long type - valid for 32bit systems only */
+-   typedef long                        IFX_long_t;
+-   #define HAVE_IFX_LONG_T
+-#endif /* HAVE_IFX_LONG_T */
+-
+-#ifndef HAVE_IFX_INTPTR_T
+-   #warning please update your ifx_types.h, using local definition of IFX_intptr_t
+-   typedef IFX_long_t                  IFX_intptr_t;
+-   #define HAVE_IFX_INTPTR_T
+-#endif /* HAVE_IFX_INTPTR_T */
+-
+-#ifndef HAVE_IFX_SIZE_T
+-   #warning please update your ifx_types.h, using local definition of IFX_size_t
+-   typedef IFX_ulong_t                 IFX_size_t;
+-   #define HAVE_IFX_SIZE_T
+-#endif /* HAVE_IFX_SIZE_T */
+-
+-#ifndef HAVE_IFX_SSIZE_T
+-   #warning please update your ifx_types.h, using local definition of IFX_ssize_t
+-   typedef IFX_long_t                  IFX_ssize_t;
+-   #define HAVE_IFX_SSIZE_T
+-#endif /* HAVE_IFX_SSIZE_T */
+-
+ #include "ifxos_interrupt.h"
+ #include "ifxos_memory_alloc.h"
+ #include "ifxos_copy_user_space.h"
+--- a/include/drv_tapi_ll_interface.h
++++ b/include/drv_tapi_ll_interface.h
+@@ -40,13 +40,6 @@
+ #include "ifxos_select.h"
+ #endif /* TAPI_PACKET */
+ 
+-#ifndef HAVE_IFX_ULONG_T
+-   #warning please update your ifx_types.h, using local definition of IFX_ulong_t
+-   /* unsigned long type - valid for 32bit systems only */
+-   typedef unsigned long               IFX_ulong_t;
+-   #define HAVE_IFX_ULONG_T
+-#endif /* HAVE_IFX_ULONG_T */
+-
+ /* ============================= */
+ /* Local Macros  Definitions    */
+ /* ============================= */
+--- a/src/lib/lib_bufferpool/lib_bufferpool.c
++++ b/src/lib/lib_bufferpool/lib_bufferpool.c
+@@ -80,24 +80,6 @@
+ #include <linux/slab.h>
+ #endif /* LINUX */
+ 
+-
+-/* ============================= */
+-/* Extra type definitions        */
+-/* ============================= */
+-#ifndef HAVE_IFX_ULONG_T
+-   #warning please update your ifx_types.h, using local definition of IFX_ulong_t
+-   /* unsigned long type - valid for 32bit systems only */
+-   typedef unsigned long               IFX_ulong_t;
+-   #define HAVE_IFX_ULONG_T
+-#endif /* HAVE_IFX_ULONG_T */
+-
+-#ifndef HAVE_IFX_UINTPTR_T
+-   #warning please update your ifx_types.h, using local definition of IFX_uintptr_t
+-   typedef IFX_ulong_t                 IFX_uintptr_t;
+-   #define HAVE_IFX_UINTPTR_T
+-#endif /* HAVE_IFX_UINTPTR_T */
+-
+-
+ /* ============================= */
+ /* Local Macros & Definitions    */
+ /* ============================= */

package/ifx-tapidemo/Config.in

@@ -0,0 +1,36 @@
+choice
+	prompt "board selection"
+	default VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3  if TARGET_ifxmips_platform_danube
+	default VOICE_CPE_TAPIDEMO_BOARD_EASY508xx     if TARGET_ifxmips_platform_ar9
+	default VOICE_CPE_TAPIDEMO_BOARD_EASY80910     if TARGET_ifxmips_platform_vr9
+	default VOICE_CPE_TAPIDEMO_BOARD_EASY50812
+	help
+		Select the target platform.
+
+	config VOICE_CPE_TAPIDEMO_BOARD_EASY50712
+		bool "Danube reference board"
+
+	config VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3
+		bool "Danube reference board V3"
+
+	config VOICE_CPE_TAPIDEMO_BOARD_EASY508xx
+		bool "AR9/GR9 reference board"
+
+	config VOICE_CPE_TAPIDEMO_BOARD_EASY80910
+		bool "VR9 reference board"
+endchoice
+
+config VOICE_CPE_TAPIDEMO_QOS
+	bool "enable QOS support"
+	default n
+	help
+		Option to enable the KPI2UDP RTP packet acceleration path
+		(highly recommended for VoIP).
+
+config  VOICE_CPE_TAPIDEMO_FAX_T.38_FW
+	bool "enable T.38 fax relay"
+	depends on (TARGET_ifxmips_platform_ar9 || TARGET_ifxmips_platform_vr9)
+	default n
+	help
+		enable T.38 fax relay demo.
+

package/ifx-tapidemo/Makefile

@@ -0,0 +1,70 @@
+#
+# Copyright (C) 2008 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+# $Id: $
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=tapidemo
+PKG_VERSION:=5.0.1.27
+PKG_RELEASE:=1
+
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
+PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
+PKG_MD5SUM:=a38a7bf3242aad607f50f57b988bc87c
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/ifx-tapidemo
+  SECTION:=utils
+  CATEGORY:=Utilities
+  TITLE:=TAPIdemo application for Lantiq boards
+  URL:=http://www.lantiq.com/
+  MAINTAINER:=Lantiq
+  DEPENDS:=+kmod-ifx-tapi +kmod-ifx-vmmc @BROKEN
+endef
+
+define Package/ifx-tapidemo/description
+	Voice Access mini-PBX Demo Application
+endef
+
+define Package/ifx-tapidemo/config
+	if PACKAGE_ifx-tapidemo
+		source "$(SOURCE)/Config.in"
+	endif
+endef
+
+CONFIGURE_ARGS += \
+	ARCH=$(LINUX_KARCH) \
+	--enable-linux-26 \
+	--enable-kernelincl="$(LINUX_DIR)/include" \
+	--with-drvincl="$(STAGING_DIR)/usr/include" \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_QOS,qos) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPIDEMO_FAX_T,fax-t38) \
+	--enable-trace \
+	--enable-fs
+
+ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY50712),y)
+  CONFIGURE_ARGS += --enable-boardname=EASY50712
+endif
+ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3),y)
+  CONFIGURE_ARGS += --enable-boardname=EASY50712_V3
+endif
+ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY508xx),y)
+  CONFIGURE_ARGS += --enable-boardname=EASY508XX
+endif
+ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY80910),y)
+  CONFIGURE_ARGS += --enable-boardname=EASY508XX
+endif
+
+define Package/ifx-tapidemo/install
+	$(INSTALL_DIR) $(1)/usr/sbin $(1)/etc/init.d/
+	$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/tapidemo $(1)/usr/sbin
+	$(INSTALL_BIN) ./files/bringup_tapidemo $(1)/etc/init.d/tapidemo
+endef
+
+$(eval $(call BuildPackage,ifx-tapidemo))

package/ifx-tapidemo/files/bringup_tapidemo

@@ -0,0 +1,89 @@
+#!/bin/sh /etc/rc.common
+# (C) 2008 openwrt.org
+
+START=96
+
+[ ! -f /dev/vmmc10 ] && {
+	mknod /dev/vmmc10 c 122 10
+	mknod /dev/vmmc11 c 122 11
+	mknod /dev/vmmc12 c 122 12
+	mknod /dev/vmmc13 c 122 13
+	mknod /dev/vmmc14 c 122 14
+	mknod /dev/vmmc15 c 122 15
+	mknod /dev/vmmc16 c 122 16
+	mknod /dev/vmmc17 c 122 17
+	mknod /dev/vmmc18 c 122 18
+}
+
+TD_EXTRA_FLAGS_FXO=
+TD_EXTRA_FLAGS_KPI2UDP=
+TD_DOWNLOAD_PATH=/lib/firmware/
+DEV_NODE_TERIDIAN=ter10
+
+ # Show help
+help()
+{
+	 echo "Usage:"
+	 echo " - $0 WAN-IF-NAME - start TAPIDEMO without FXO support"
+	 echo " - $0 WAN-IF-NAME fxo - start TAPIDEMO with FXO support."
+	 echo " - $0 stop - stop TAPIDEMO"
+}
+
+# Check if device node for Teridian exists
+checkFxoSupport()
+{
+	if [ ! -e /dev/$DEV_NODE_TERIDIAN ];then
+		echo "FXO support is disabled. Can not find required driver's device node."
+	else
+		TD_EXTRA_FLAGS_FXO="-x"
+	fi
+}
+
+# Check if module drv_kpi2udp is loaded
+checkKpi2UdpSupport()
+{
+	tmp=`cat /proc/modules | grep 'drv_kpi2udp '`
+	if [ "$tmp" != "" ]; then
+		TD_EXTRA_FLAGS_KPI2UDP="-q"
+	fi
+}
+
+start()
+{
+	TD_WANIF=$1
+
+	TD_WANIF_IP=`ifconfig $TD_WANIF | grep 'inet addr:' | cut -f2 -d: | cut -f1 -d' '`
+	if [ "$TD_WANIF_IP" = "" ]; then
+		echo "Error, getting IP address for network device $TD_WANIF failed."
+		exit 1
+	fi
+
+	if [ "$2" = "" ];then
+		# FXO support is disabled.
+	  continue
+	elif [ "$2" = "fxo" ];then
+	  checkFxoSupport
+	else
+	  echo "Error, unknown second parameter."
+	  help
+	  exit 1
+	fi
+
+	checkKpi2UdpSupport
+
+	if [ -r /etc/rc.conf ]; then
+		. /etc/rc.conf
+	fi
+
+	TD_DEBUG_LEVEL=$tapiDebugLevel
+	if [ "$TD_DEBUG_LEVEL" = "" ]; then
+		TD_DEBUG_LEVEL=3
+	fi
+
+	/usr/sbin/tapidemo -d $TD_DEBUG_LEVEL $TD_EXTRA_FLAGS_FXO $TD_EXTRA_FLAGS_KPI2UDP -i $TD_WANIF_IP -l $TD_DOWNLOAD_PATH &
+}
+
+stop()
+{
+	 killall tapidemo > /dev/null 2> /dev/null
+}

package/ifx-tapidemo/patches/100-ifxmips.patch

@@ -0,0 +1,78 @@
+--- a/src/board_easy50712.c	Mon Mar 15 14:47:53 2010 +0300
++++ b/src/board_easy50712.c	Tue Mar 16 17:25:55 2010 +0300
+@@ -40,7 +40,9 @@
+    #endif /* DUSLIC_FXO */
+ #endif /* EASY50712_V3 */
+ 
+-#include "asm/ifx/ifx_gpio.h"
++#ifdef FXO
++#  include "asm/ifx/ifx_gpio.h"
++#endif
+ 
+ /* ============================= */
+ /* Defines                       */
+@@ -896,6 +898,7 @@
+ /* Global function definition    */
+ /* ============================= */
+ 
++#ifdef FXO
+ /**
+    Set direction of GPIO pin to out which is used for set/clear reset.
+ 
+@@ -944,7 +947,7 @@
+          return IFX_SUCCESS;
+       }
+       break;
+-      
++
+       case GPIO_DUSLIC_EASY50510:
+       {
+          TRACE(TAPIDEMO, DBG_LEVEL_LOW,
+@@ -982,8 +985,9 @@
+ 
+    return IFX_SUCCESS;
+ };
++#endif
+ 
+-
++#ifdef FXO
+ /*
+    Set/Clear reset of device by using GPIO port.
+ 
+@@ -1086,7 +1090,9 @@
+    /* usleep(100000); karol - workaround, */
+    return ret;
+ }
++#endif
+ 
++#ifdef EASY50510
+ /**
+    Set PCM master mode.
+ 
+@@ -1178,15 +1184,16 @@
+ 
+    return ret;
+ }
++#endif
+ 
+ /**
+    Register board.
+ 
+    \param pBoard - pointer to board
+- 
++
+    \return IFX_SUCCESS if successful, otherwise IFX_ERROR.
+ 
+-   \remarks 
++   \remarks
+ */
+ IFX_return_t BOARD_Easy50712_Register(BOARD_t* pBoard)
+ {
+@@ -1204,7 +1211,3 @@
+    pBoard->RemoveBoard = BOARD_Easy50712_RemoveBoard;
+    return IFX_SUCCESS;
+ }
+-
+-
+-
+-

package/ifx-tapidemo/patches/110-no_echo_cancelation.patch

@@ -0,0 +1,12 @@
+Index: tapidemo-5.0.1.27/src/device_vmmc.c
+===================================================================
+--- tapidemo-5.0.1.27.orig/src/device_vmmc.c	2009-11-09 15:40:31.000000000 +0100
++++ tapidemo-5.0.1.27/src/device_vmmc.c	2010-03-30 21:32:51.000000000 +0200
+@@ -240,7 +240,6 @@
+       TRACE(TAPIDEMO, DBG_LEVEL_HIGH,
+             ("Error, BBD file %s is not found.\n(File: %s, line: %d)\n",
+              pCpuDevice->pszBBD_CRAM_File, __FILE__, __LINE__));
+-      return IFX_ERROR;
+    }
+ 
+ #endif /* USE_FILESYSTEM */

package/ifx-vmmc/Config.in

@@ -0,0 +1,49 @@
+choice
+	prompt "device selection"
+	default VOICE_CPE_VMMC_WITH_DEVICE_DANUBE_extract
+	help
+		Select the target device.
+
+	config VOICE_CPE_VMMC_WITH_DEVICE_DANUBE_extract
+		bool "Danube, Twinpass, Vinax - extract binaries"
+
+	config VOICE_CPE_VMMC_WITH_DEVICE_DANUBE
+		bool "Danube, Twinpass, Vinax"
+
+	config VOICE_CPE_VMMC_WITH_DEVICE_AR9
+		bool "AR9 family"
+
+	config VOICE_CPE_VMMC_WITH_DEVICE_VR9
+		bool "VR9 family"
+
+endchoice
+
+config VOICE_CPE_VMMC_PMC
+	depends on (VOICE_CPE_VMMC_WITH_DEVICE_AR9 || VOICE_CPE_VMMC_WITH_DEVICE_VR9)
+	bool "Power Management Control support"
+	default n
+	help
+		Option to enable Power Management Control on AR9, VR9. Not supported for Danube.
+
+config VOICE_CPE_VMMC_DISABLE_DECT_NIBBLE_SWAP
+	bool "Disable DECT nibble swap"
+	default n
+	help
+		Option to disable DECT nibble swap for COSIC modem (for backward compatibility only).
+
+config VOICE_CPE_VMMC_EVENT_LOGGER
+	depends on BROKEN
+	bool "Event logger support"
+	default n
+	help
+		Option to enable details traces between drv_vmmc and the voice FW
+		- for debugging only
+		- requires package ifx-evtlog
+
+config VOICE_CPE_VMMC_MPS_HISTORY_SIZE
+	int "MPS history buffer in words (0<=size<=512)"
+	default "128"
+	help
+		MPS history buffer (default=128 words, maximum=512 words, 0=disable)
+		To opimize the memory footprint in RAM, you might want to set the
+		buffer size to 0.

package/ifx-vmmc/Makefile

@@ -0,0 +1,158 @@
+#
+# Copyright (C) 2008 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=drv_vmmc
+PKG_VERSION:=1.7.0
+PKG_RELEASE:=1
+
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
+PKG_MD5SUM:=3f1b44e79408a3320aa9f8b21a260fd0
+PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
+
+include $(INCLUDE_DIR)/package.mk
+
+define KernelPackage/ifx-vmmc
+  SUBMENU:=Voice over IP
+  TITLE:=TAPI LL driver for Voice Macro
+  URL:=http://www.lantiq.com/
+  MAINTAINER:=Lantiq
+  DEPENDS:=+kmod-ifx-tapi @BROKEN
+  FILES:=$(PKG_BUILD_DIR)/src/drv_vmmc.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,25,drv_vmmc)
+endef
+
+define KernelPackage/ifx-vmmc/description
+	Voice Subsystem Low Level Driver for Danube, AR9, VR9 device families
+endef
+
+define KernelPackage/ifx-vmmc/config
+	if PACKAGE_kmod-ifx-vmmc
+		source "$(SOURCE)/Config.in"
+	endif
+endef
+
+CONFIGURE_ARGS += \
+	ARCH=$(LINUX_KARCH) \
+	--enable-linux-26 \
+	--enable-kernelbuild="$(LINUX_DIR)" \
+	--enable-kernelincl="$(LINUX_DIR)/include" \
+	--enable-tapiincl="$(STAGING_DIR)/usr/include/drv_tapi" \
+	--with-ifxos-incl=$(STAGING_DIR)/usr/include/ifxos \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_VMMC_EVENT_LOGGER,el-debug) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_VMMC_PMC,pmc) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_VMMC_DISABLE_DECT_NIBBLE_SWAP,dect-nibble-swap) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_FAX,fax t38) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_CID,cid) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_DECT,dect) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_KPI,kpi) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_LT_GR909,lt calibration) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_HDLC,hdlc) \
+	$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_TRACES,trace)
+
+ifneq ($(CONFIG_VOICE_CPE_VMMC_MPS_HISTORY_SIZE),128)
+  CONFIGURE_ARGS += --enable-history-buf=$(CONFIG_VOICE_CPE_VMMC_MPS_HISTORY_SIZE)
+endif
+
+#defaults 
+FW_URL:=http://localhost/
+FW_TARGET:=ifx_firmware.bin
+FW_FILE:=fw_voip_ifx.tar.gz
+COEF_TARGET:=ifx_bbd_fxs.bin
+COEF_FILE:=coef_voip_ifx.tar.gz
+
+FW_DIR:=lib/firmware
+ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_DANUBE_extract),y)
+  CONFIGURE_ARGS += --with-device=DANUBE
+  FW_TARGET:=danube_firmware.bin
+  FW_URL:=http://www.arcor.de/hilfe/files/pdf/
+  FW_FILE=arcor_A800_452CPW_FW_1.02.206(20081201).bin
+  FW_MD5SUM:=19d9af4e369287a0f0abaed415cdac10
+  COEF_TARGET:=danube_bbd_fxs.bin
+  COEF_FILE:=arcor_A800_452CPW_FW_1.02.206(20081201).bin
+  COEF_MD5SUM:=19d9af4e369287a0f0abaed415cdac10
+endif
+
+ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_DANUBE),y)
+  CONFIGURE_ARGS += --with-device=DANUBE
+  FW_TARGET:=danube_firmware.bin
+  FW_FILE=fw_voip_danube-12.1.0.1.0.tar.gz
+  FW_MD5SUM:=51868b88dee9dbc65d3dbba355ded91c
+  COEF_TARGET:=danube_bbd_fxs.bin
+  COEF_FILE:=coef_voip_danube-0.9.0.tar.gz
+  COEF_MD5SUM:=c8ac6592b304b03829a8123560e15710
+endif
+
+ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_AR9),y)
+  CONFIGURE_ARGS += --with-device=AR9
+  # TODO: add fw/coef
+endif
+
+ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_VR9),y)
+  CONFIGURE_ARGS += --with-device=VR9
+  # TODO: add fw/coef
+endif
+
+ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_DANUBE_extract),y)
+define Download/decode
+  FILE:=ifxmips_fw_decode.tar.bz2
+  URL:=http://downloads.openwrt.org/sources/
+  MD5SUM:=1197ff6cace6a7c86492a468f5fbfe07
+endef
+$(eval $(call Download,decode))
+endif
+
+define Download/firmware
+  FILE:=$(FW_FILE)
+  URL:=$(FW_URL)
+  MD5SUM:=$(FW_MD5SUM)
+endef
+$(eval $(call Download,firmware))
+
+define Download/coef
+  FILE:=$(COEF_FILE)
+  URL:=$(FW_URL)
+  MD5SUM:=$(COEF_MD5SUM)
+endef
+$(eval $(call Download,coef))
+
+define Build/Configure
+	rm -rf \
+		$(PKG_BUILD_DIR)/coef \
+		$(PKG_BUILD_DIR)/firmware
+	mkdir -p \
+		$(PKG_BUILD_DIR)/coef \
+		$(PKG_BUILD_DIR)/firmware
+ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_DANUBE_extract),y)
+	$(PLATFORM_DIR)/extract.sh $(DL_DIR) '$(FW_FILE)' 
+	$(CP) $(DL_DIR)/voip.bin $(PKG_BUILD_DIR)/firmware/$(FW_TARGET)
+	$(CP) $(DL_DIR)/voip_coef.bin $(PKG_BUILD_DIR)/coef/$(COEF_TARGET)
+else
+	$(TAR) -C $(PKG_BUILD_DIR)/firmware -xvzf $(DL_DIR)/$(FW_FILE)
+	$(TAR) -C $(PKG_BUILD_DIR)/coef -xvzf $(DL_DIR)/$(COEF_FILE)
+endif
+	(cd $(PKG_BUILD_DIR); aclocal && autoconf && automake)
+	$(call Build/Configure/Default)
+endef
+
+define Build/InstallDev
+	$(INSTALL_DIR) $(1)/usr/include
+	mkdir -p $(1)/usr/include/drv_vmmc
+	$(CP) -v --dereference $(PKG_BUILD_DIR)/include/* $(1)/usr/include/drv_vmmc
+	(cd $(1)/usr/include/drv_vmmc && ln -snf . include)
+endef
+
+define KernelPackage/ifx-vmmc/install
+	$(INSTALL_DIR) $(1)/etc/init.d $(1)/$(FW_DIR)
+	$(INSTALL_BIN) ./files/vmmc.init $(1)/etc/init.d/vmmc
+	$(CP) $(PKG_BUILD_DIR)/firmware/$(FW_TARGET) $(1)/$(FW_DIR)/$(FW_TARGET)
+	$(CP) $(PKG_BUILD_DIR)/coef/$(COEF_TARGET) $(1)/$(FW_DIR)/$(COEF_TARGET)
+endef
+
+$(eval $(call KernelPackage,ifx-vmmc))

package/ifx-vmmc/files/vmmc.init

@@ -0,0 +1,25 @@
+#!/bin/sh /etc/rc.common
+#
+# Activate Voice CPE TAPI subsystem LL driver for VMMC
+
+START=31
+
+start() {
+	# TODO: clean up this mess
+	[ `cat /proc/cpuinfo | grep system | cut -f 3 -d ' '` =  "Twinpass-VE" ] && {
+		[ ! -e /dev/danube-port ] && mknod /dev/danube-port c 254 0
+		return;
+	}
+	[ `cat /proc/cpuinfo | grep system | cut -f 3 -d ' '` !=  "Danube" ] && {
+		[ ! -e /dev/amazon_s-port ] && mknod /dev/amazon_s-port c 240 1
+		echo "INFO configuring HW scheduling 33/66"
+		echo "t0 0x0" > /proc/mips/mtsched
+		echo "t1 0x1" > /proc/mips/mtsched
+		echo "v0 0x0" > /proc/mips/mtsched
+	}
+	[ `cat /proc/cpuinfo | grep system | cut -f 3 -d ' '` =  "Danube" ] && {
+		[ ! -e /dev/danube-port ] && mknod /dev/danube-port c 240 1
+		# switch life-line relais
+		echo 1 > /sys/class/leds/fxs_relay/brightness
+	}
+}

package/ifx-vmmc/patches/001-portability.patch

@@ -0,0 +1,26 @@
+--- a/src/Makefile.am
++++ b/src/Makefile.am
+@@ -227,7 +227,7 @@ drv_vmmc_CFLAGS += -fno-common
+ drv_vmmc_OBJS = "$(subst .c,.o, $(drv_vmmc_SOURCES) $(nodist_drv_vmmc_SOURCES))"
+ 
+ drv_vmmc.ko: $(drv_vmmc_SOURCES) $(EXTRA_DIST)
+-	@echo -e "Making Linux 2.6.x kernel object"
++	@echo "Making Linux 2.6.x kernel object"
+ 	@for f in $(drv_vmmc_SOURCES) $(nodist_drv_vmmc_SOURCES) ; do \
+ 		if test ! -e $(PWD)/$$f; then \
+ 			echo "  LN      $$f" ; \
+@@ -235,10 +235,10 @@ drv_vmmc.ko: $(drv_vmmc_SOURCES) $(EXTRA
+ 			ln -s @abs_srcdir@/$$f $(PWD)/$$f; \
+ 		fi; \
+ 	done;
+-	@echo -e "# drv_vmmc: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
+-	@echo -e "obj-m := $(subst .ko,.o,$@)"			>> $(PWD)/Kbuild
+-	@echo -e "$(subst .ko,,$@)-y := $(drv_vmmc_OBJS)"	>> $(PWD)/Kbuild
+-	@echo -e "EXTRA_CFLAGS := -DHAVE_CONFIG_H  $(CFLAGS) $(drv_vmmc_CFLAGS) $(INCLUDES)"	>> $(PWD)/Kbuild
++	@echo "# drv_vmmc: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
++	@echo "obj-m := $(subst .ko,.o,$@)"			>> $(PWD)/Kbuild
++	@echo "$(subst .ko,,$@)-y := $(drv_vmmc_OBJS)"	>> $(PWD)/Kbuild
++	@echo "EXTRA_CFLAGS := -DHAVE_CONFIG_H  $(CFLAGS) $(drv_vmmc_CFLAGS) $(INCLUDES)"	>> $(PWD)/Kbuild
+ 	$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules
+ 
+ clean-generic:

package/ifx-vmmc/patches/100-ifxmips.patch

@@ -0,0 +1,491 @@
+--- a/src/drv_vmmc_access.h
++++ b/src/drv_vmmc_access.h
+@@ -24,6 +24,10 @@
+ #include "drv_mps_vmmc.h"
+ #endif
+ 
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  define IFX_MPS IFXMIPS_MPS_BASE_ADDR
++#endif
++
+ /* ============================= */
+ /* Global Defines                */
+ /* ============================= */
+--- a/src/drv_vmmc_bbd.c
++++ b/src/drv_vmmc_bbd.c
+@@ -939,7 +939,11 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
+    IFX_uint8_t  padBytes = 0;
+ #endif
+    IFX_uint16_t cram_offset, cram_crc,
+-                pCmd [MAX_CMD_WORD]  = {0};
++                pCmd [MAX_CMD_WORD]
++#if defined (__GNUC__) || defined (__GNUG__)
++                   __attribute__ ((aligned(4)))
++#endif
++                   = {0};
+ 
+    /* read offset */
+    cpb2w (&cram_offset, &bbd_cram->pData[0], sizeof (IFX_uint16_t));
+--- a/src/drv_vmmc_danube.h
++++ b/src/drv_vmmc_danube.h
+@@ -15,12 +15,59 @@
+ */
+ 
+ #if defined SYSTEM_DANUBE
+-#include <asm/ifx/ifx_gpio.h>
++#  if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#     include <asm/mach-ifxmips/ifxmips_gpio.h>
++
++#     define IFX_GPIO_PIN_NUMBER_PER_PORT    16
++#     define IFX_GPIO_PIN_ID(port, pin)      ((port) \
++                                             * IFX_GPIO_PIN_NUMBER_PER_PORT \
++                                             + (pin))
++#     define IFX_GPIO_PIN_ID_TO_PORT(pin_id) (pin_id >> 4)
++#     define IFX_GPIO_PIN_ID_TO_PIN(pin_id)  (pin_id & 0x0F)
++
++#     define IFX_GPIO_MODULE_TAPI_VMMC       0 /* not used */
++
++#     define ifx_gpio_pin_reserve(a,b)       0 /* obsolete */
++
++#     define ifx_gpio_open_drain_set(a,b)    ifxmips_port_set_open_drain( \
++                                                IFX_GPIO_PIN_ID_TO_PORT(a), \
++                                                IFX_GPIO_PIN_ID_TO_PIN(a))
++
++#     define ifx_gpio_altsel0_set(a,b)       ifxmips_port_set_altsel0( \
++                                                IFX_GPIO_PIN_ID_TO_PORT(a), \
++                                                IFX_GPIO_PIN_ID_TO_PIN(a))
++
++#     define ifx_gpio_altsel1_set(a,b)       ifxmips_port_set_altsel1( \
++                                                IFX_GPIO_PIN_ID_TO_PORT(a), \
++                                                IFX_GPIO_PIN_ID_TO_PIN(a))
++
++#     define ifx_gpio_altsel0_clear(a,b)     ifxmips_port_clear_altsel0( \
++                                                IFX_GPIO_PIN_ID_TO_PORT(a), \
++                                                IFX_GPIO_PIN_ID_TO_PIN(a))
++
++#     define ifx_gpio_altsel1_clear(a,b)     ifxmips_port_clear_altsel1( \
++                                                IFX_GPIO_PIN_ID_TO_PORT(a), \
++                                                IFX_GPIO_PIN_ID_TO_PIN(a))
++
++#     define ifx_gpio_dir_in_set(a,b)        ifxmips_port_set_dir_in( \
++                                                IFX_GPIO_PIN_ID_TO_PORT(a), \
++                                                IFX_GPIO_PIN_ID_TO_PIN(a))
++
++#     define ifx_gpio_dir_out_set(a,b)       ifxmips_port_set_dir_out( \
++                                                IFX_GPIO_PIN_ID_TO_PORT(a), \
++                                                IFX_GPIO_PIN_ID_TO_PIN(a))
++
++#     define ifx_gpio_pin_free(a,b)          ifxmips_port_free_pin( \
++                                                IFX_GPIO_PIN_ID_TO_PORT(a), \
++                                                IFX_GPIO_PIN_ID_TO_PIN(a))
++#  else
++#     include <asm/ifx/ifx_gpio.h>
++#  endif
+ #else
+ #error no system selected
+ #endif
+ 
+-#define VMMC_TAPI_GPIO_MODULE_ID                        IFX_GPIO_MODULE_TAPI_VMMC
++#define VMMC_TAPI_GPIO_MODULE_ID             IFX_GPIO_MODULE_TAPI_VMMC
+ /**
+ 
+ */
+--- a/src/drv_vmmc_init.c
++++ b/src/drv_vmmc_init.c
+@@ -48,6 +48,14 @@
+ #include "drv_vmmc_pmc.h"
+ #endif /* PMC_SUPPORTED */
+ 
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
++#  define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
++#  define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
++#  define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
++#  define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
++#  define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
++#endif
+ 
+ /* ============================= */
+ /* Local Macros & Definitions    */
+--- a/src/drv_vmmc_init_cap.c
++++ b/src/drv_vmmc_init_cap.c
+@@ -22,6 +22,11 @@
+ #include "drv_mps_vmmc.h"
+ #include "drv_mps_vmmc_device.h"
+ 
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  define IFX_MPS_CHIPID_VERSION_GET   IFXMIPS_MPS_CHIPID_VERSION_GET
++#  define IFX_MPS_CHIPID               IFXMIPS_MPS_CHIPID
++#endif
++
+ /* ============================= */
+ /* Configuration defintions      */
+ /* ============================= */
+--- a/src/mps/drv_mps_vmmc_common.c
++++ b/src/mps/drv_mps_vmmc_common.c
+@@ -35,8 +35,35 @@
+ #include "ifxos_interrupt.h"
+ #include "ifxos_time.h"
+ 
+-#include <asm/ifx/ifx_regs.h>
+-#include <asm/ifx/ifx_gptu.h>
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  include <asm/mach-ifxmips/ifxmips.h>
++#  include <asm/mach-ifxmips/ifxmips_irq.h>
++#  include <asm/mach-ifxmips/ifxmips_gptu.h>
++
++#  define ifx_gptu_timer_request    ifxmips_request_timer
++#  define ifx_gptu_timer_start      ifxmips_start_timer
++#  define ifx_gptu_countvalue_get   ifxmips_get_count_value
++#  define ifx_gptu_timer_free       ifxmips_free_timer
++
++#  define IFX_MPS_SRAM              IFXMIPS_MPS_SRAM
++#  define IFX_MPS_AD0ENR            IFXMIPS_MPS_AD0ENR
++#  define IFX_MPS_AD1ENR            IFXMIPS_MPS_AD1ENR
++#  define IFX_MPS_VC0ENR            IFXMIPS_MPS_VC0ENR
++#  define IFX_MPS_SAD0SR            IFXMIPS_MPS_SAD0SR
++#  define IFX_MPS_RAD0SR            IFXMIPS_MPS_RAD0SR
++#  define IFX_MPS_RAD1SR            IFXMIPS_MPS_RAD1SR
++#  define IFX_MPS_CAD0SR            IFXMIPS_MPS_CAD0SR
++#  define IFX_MPS_CAD1SR            IFXMIPS_MPS_CAD1SR
++#  define IFX_MPS_RVC0SR            IFXMIPS_MPS_RVC0SR
++#  define IFX_MPS_CVC0SR            IFXMIPS_MPS_CVC0SR
++
++#  define INT_NUM_IM4_IRL14         (INT_NUM_IM4_IRL0 + 14)
++
++#  define bsp_mask_and_ack_irq      ifxmips_mask_and_ack_irq
++#else
++#  include <asm/ifx/ifx_regs.h>
++#  include <asm/ifx/ifx_gptu.h>
++#endif
+ 
+ #include "drv_mps_vmmc.h"
+ #include "drv_mps_vmmc_dbg.h"
+@@ -193,7 +220,8 @@ IFX_boolean_t ifx_mps_ext_bufman ()
+  */
+ IFX_void_t *ifx_mps_fastbuf_malloc (IFX_size_t size, IFX_int32_t priority)
+ {
+-   IFX_uint32_t ptr, flags;
++   unsigned long flags;
++   IFX_uint32_t ptr;
+    IFX_int32_t index = fastbuf_index;
+ 
+    if (fastbuf_initialized == 0)
+@@ -219,11 +247,11 @@ IFX_void_t *ifx_mps_fastbuf_malloc (IFX_
+       if ((volatile IFX_uint32_t) fastbuf_pool[index] & FASTBUF_USED)
+          continue;
+       ptr = fastbuf_pool[index];
+-      (volatile IFX_uint32_t) fastbuf_pool[index] |= FASTBUF_USED;
++      fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] | FASTBUF_USED;
+       if ((priority == FASTBUF_FW_OWNED) || (priority == FASTBUF_CMD_OWNED) ||
+           (priority == FASTBUF_EVENT_OWNED) ||
+           (priority == FASTBUF_WRITE_OWNED))
+-         (volatile IFX_uint32_t) fastbuf_pool[index] |= priority;
++         fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] | priority;
+       fastbuf_index = index;
+       IFXOS_UNLOCKINT (flags);
+       return (IFX_void_t *) ptr;
+@@ -247,7 +275,7 @@ IFX_void_t *ifx_mps_fastbuf_malloc (IFX_
+  */
+ IFX_void_t ifx_mps_fastbuf_free (const IFX_void_t * ptr)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+    IFX_int32_t index = fastbuf_index;
+ 
+    IFXOS_LOCKINT (flags);
+@@ -261,8 +289,9 @@ IFX_void_t ifx_mps_fastbuf_free (const I
+                                      FASTBUF_EVENT_OWNED | FASTBUF_WRITE_OWNED))
+           == ((IFX_uint32_t) ptr | FASTBUF_USED))
+       {
+-         (volatile IFX_uint32_t) fastbuf_pool[index] &= ~FASTBUF_USED;
+-         (volatile IFX_uint32_t) fastbuf_pool[index] &=
++         fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] & ~FASTBUF_USED;
++
++         fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] &
+             ~(FASTBUF_FW_OWNED | FASTBUF_CMD_OWNED | FASTBUF_EVENT_OWNED |
+               FASTBUF_WRITE_OWNED);
+          IFXOS_UNLOCKINT (flags);
+@@ -444,7 +473,7 @@ static mps_buffer_state_e ifx_mps_bufman
+  */
+ static IFX_int32_t ifx_mps_bufman_inc_level (IFX_uint32_t value)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    if (mps_buffer.buf_level + value > MPS_BUFFER_MAX_LEVEL)
+    {
+@@ -471,7 +500,7 @@ static IFX_int32_t ifx_mps_bufman_inc_le
+  */
+ static IFX_int32_t ifx_mps_bufman_dec_level (IFX_uint32_t value)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    if (mps_buffer.buf_level < value)
+    {
+@@ -932,7 +961,7 @@ IFX_int32_t ifx_mps_common_open (mps_com
+                                  mps_mbx_dev * pMBDev, IFX_int32_t bcommand,
+                                  IFX_boolean_t from_kernel)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    IFXOS_LOCKINT (flags);
+ 
+@@ -1048,7 +1077,7 @@ IFX_int32_t ifx_mps_common_close (mps_mb
+ IFX_void_t ifx_mps_release_structures (mps_comm_dev * pDev)
+ {
+    IFX_int32_t count;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    IFXOS_LOCKINT (flags);
+    IFXOS_BlockFree (pFW_img_data);
+@@ -1544,7 +1573,7 @@ IFX_int32_t ifx_mps_mbx_read_message (mp
+                                       IFX_uint32_t * bytes)
+ {
+    IFX_int32_t i, ret;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    IFXOS_LOCKINT (flags);
+ 
+@@ -1751,7 +1780,7 @@ IFX_int32_t ifx_mps_mbx_write_message (m
+ {
+    mps_fifo *mbx;
+    IFX_uint32_t i;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+    IFX_int32_t retval = -EAGAIN;
+    IFX_int32_t retries = 0;
+    IFX_uint32_t word = 0;
+@@ -2138,6 +2167,7 @@ IFX_int32_t ifx_mps_mbx_write_cmd (mps_m
+       TRACE (MPS, DBG_LEVEL_HIGH,
+              ("%s(): Invalid device ID %d !\n", __FUNCTION__, pMBDev->devID));
+    }
++
+    return retval;
+ }
+ 
+@@ -2161,7 +2191,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
+    mps_mbx_dev *mbx_dev;
+    MbxMsg_s msg;
+    IFX_uint32_t bytes_read = 0;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+    IFX_int32_t ret;
+ 
+    /* set pointer to data upstream mailbox, no matter if 0,1,2 or 3 because
+@@ -2252,7 +2282,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
+          {
+             ifx_mps_bufman_dec_level (1);
+             if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
+-                (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
++                ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
+             {
+                IFXOS_LockRelease (pMPSDev->provide_buffer);
+             }
+@@ -2295,7 +2325,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
+ #endif /* CONFIG_PROC_FS */
+             ifx_mps_bufman_dec_level (1);
+             if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
+-                (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
++                ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
+             {
+                IFXOS_LockRelease (pMPSDev->provide_buffer);
+             }
+@@ -2325,7 +2355,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
+ IFX_void_t ifx_mps_mbx_cmd_upstream (IFX_ulong_t dummy)
+ {
+    mps_fifo *mbx;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    /* set pointer to upstream command mailbox */
+    mbx = &(pMPSDev->cmd_upstrm_fifo);
+@@ -2373,7 +2403,7 @@ IFX_void_t ifx_mps_mbx_event_upstream (I
+    mps_event_msg msg;
+    IFX_int32_t length = 0;
+    IFX_int32_t read_length = 0;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    /* set pointer to upstream event mailbox */
+    mbx = &(pMPSDev->event_upstrm_fifo);
+@@ -2616,7 +2646,7 @@ IFX_void_t ifx_mps_disable_mailbox_int (
+ */
+ IFX_void_t ifx_mps_dd_mbx_int_enable (IFX_void_t)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+    MPS_Ad0Reg_u Ad0Reg;
+ 
+    IFXOS_LOCKINT (flags);
+@@ -2642,7 +2672,7 @@ IFX_void_t ifx_mps_dd_mbx_int_enable (IF
+ */
+ IFX_void_t ifx_mps_dd_mbx_int_disable (IFX_void_t)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+    MPS_Ad0Reg_u Ad0Reg;
+ 
+    IFXOS_LOCKINT (flags);
+@@ -2769,6 +2799,7 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t
+       }
+    }
+ 
++
+    if (MPS_Ad0StatusReg.fld.du_mbx)
+    {
+ #ifdef CONFIG_PROC_FS
+@@ -3062,7 +3093,8 @@ IFX_int32_t ifx_mps_get_fw_version (IFX_
+  */
+ IFX_return_t ifx_mps_init_gpt ()
+ {
+-   IFX_uint32_t flags, timer_flags, timer, loops = 0;
++   unsigned long flags;
++   IFX_uint32_t timer_flags, timer, loops = 0;
+    IFX_ulong_t count;
+ #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
+    timer = TIMER1A;
+--- a/src/mps/drv_mps_vmmc_danube.c
++++ b/src/mps/drv_mps_vmmc_danube.c
+@@ -32,9 +32,22 @@
+ #include "ifxos_select.h"
+ #include "ifxos_interrupt.h"
+ 
+-#include <asm/ifx/ifx_regs.h>
+-#include <asm/ifx/ifx_gpio.h>
+-#include <asm/ifx/common_routines.h>
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  include <asm/mach-ifxmips/ifxmips.h>
++#  include <asm/mach-ifxmips/ifxmips_irq.h>
++#  include <asm/mach-ifxmips/ifxmips_gptu.h>
++#  include <asm/mach-ifxmips/ifxmips_prom.h>
++
++#  define IFX_RCU_RST_REQ        IFXMIPS_RCU_RST
++#  define IFX_RCU_RST_REQ_CPU1   IFXMIPS_RCU_RST_CPU1
++
++#  define ifx_get_cp1_base       prom_get_cp1_base
++#  define ifx_get_cp1_size       prom_get_cp1_size
++#else
++#  include <asm/ifx/ifx_regs.h>
++#  include <asm/ifx_vpe.h>
++#  include <asm/ifx/ifx_gpio.h>
++#endif
+ 
+ #include "drv_mps_vmmc.h"
+ #include "drv_mps_vmmc_dbg.h"
+@@ -119,6 +132,15 @@ IFX_int32_t ifx_mps_download_firmware (m
+    }
+ 
+    /* check if FW image fits in available memory space */
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++   if (mem > ifx_get_cp1_size()<<20)
++   {
++      TRACE (MPS, DBG_LEVEL_HIGH,
++      ("[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\n",
++                 __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()<<20));
++      return IFX_ERROR;
++   }
++#else
+    if (mem > ifx_get_cp1_size())
+    {
+       TRACE (MPS, DBG_LEVEL_HIGH,
+@@ -126,6 +148,7 @@ IFX_int32_t ifx_mps_download_firmware (m
+                  __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()));
+       return IFX_ERROR;
+    }
++#endif
+ 
+    /* reset the driver */
+    ifx_mps_reset ();
+@@ -337,7 +360,7 @@ IFX_void_t ifx_mps_release (IFX_void_t)
+  */
+ IFX_void_t ifx_mps_wdog_expiry()
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    IFXOS_LOCKINT (flags);
+    /* recalculate and compare the firmware checksum */
+--- a/src/mps/drv_mps_vmmc_device.h
++++ b/src/mps/drv_mps_vmmc_device.h
+@@ -16,8 +16,15 @@
+                  declarations.
+ *******************************************************************************/
+ 
+-#include <asm/ifx/ifx_regs.h>
+-#include <asm/ifx_vpe.h>
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  include <asm/mach-ifxmips/ifxmips.h>
++#  include <asm/mach-ifxmips/ifxmips_irq.h>
++#  include <asm/mach-ifxmips/ifxmips_gpio.h>
++#  include <gpio.h>
++#else
++#  include <asm/ifx/ifx_regs.h>
++#  include <asm/ifx_vpe.h>
++#endif
+ 
+ /* ============================= */
+ /* MPS Common defines            */
+--- a/src/mps/drv_mps_vmmc_linux.c
++++ b/src/mps/drv_mps_vmmc_linux.c
+@@ -40,10 +40,26 @@
+ #include <linux/moduleparam.h>
+ #endif /* */
+ 
+-
+-#include <asm/ifx/irq.h>
+-#include <asm/ifx/ifx_regs.h>
+-#include <asm/ifx_vpe.h>
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  include <asm/mach-ifxmips/ifxmips.h>
++#  include <asm/mach-ifxmips/ifxmips_irq.h>
++
++#  define IFX_MPS_AD0ENR      IFXMIPS_MPS_AD0ENR
++#  define IFX_MPS_AD1ENR      IFXMIPS_MPS_AD1ENR
++#  define IFX_MPS_RAD0SR      IFXMIPS_MPS_RAD0SR
++#  define IFX_MPS_RAD1SR      IFXMIPS_MPS_RAD1SR
++#  define IFX_MPS_VC0ENR      IFXMIPS_MPS_VC0ENR
++#  define IFX_MPS_RVC0SR      IFXMIPS_MPS_RVC0SR
++
++#  define INT_NUM_IM4_IRL14   (INT_NUM_IM4_IRL0 + 14)
++#  define INT_NUM_IM4_IRL18   (INT_NUM_IM4_IRL0 + 18)
++#  define INT_NUM_IM4_IRL19   (INT_NUM_IM4_IRL0 + 19)
++#  define IFX_ICU_IM4_IER     IFXMIPS_ICU_IM4_IER
++#else
++#  include <asm/ifx/irq.h>
++#  include <asm/ifx/ifx_regs.h>
++#  include <asm/ifx_vpe.h>
++#endif
+ 
+ /* lib_ifxos headers */
+ #include "ifx_types.h"
+@@ -914,7 +930,7 @@ IFX_int32_t ifx_mps_ioctl (struct inode 
+ #endif /* MPS_FIFO_BLOCKING_WRITE */
+       case FIO_MPS_GET_STATUS:
+          {
+-            IFX_uint32_t flags;
++            unsigned long flags;
+ 
+             IFXOS_LOCKINT (flags);
+ 
+@@ -949,7 +965,7 @@ IFX_int32_t ifx_mps_ioctl (struct inode 
+ #if CONFIG_MPS_HISTORY_SIZE > 0
+       case FIO_MPS_GET_CMD_HISTORY:
+          {
+-            IFX_uint32_t flags;
++            unsigned long flags;
+ 
+             if (from_kernel)
+             {
+@@ -1637,6 +1653,7 @@ IFX_int32_t ifx_mps_get_status_proc (IFX
+          sprintf (buf + len, "   minLv: \t  %8d\n",
+                   ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space);
+    }
++
+    return len;
+ }
+ 

package/ifxmips-dsl-api/Config.in

@@ -17,6 +17,13 @@ config IFXMIPS_ANNEX_B
 
 endchoice
 
+config IFXMIPS_DSL_FIRMWARE
+	bool "ifxmips-dsl firmware extractor"
+	default y
+	depends on PACKAGE_kmod-ifxmips-dsl-api
+	help
+	  Say Y, if you need ifxmips-dsl to auto extract the firmware for you from the a800 firmware image
+
 config IFXMIPS_DSL_DEBUG
 	bool "ifxmips-dsl debugging"
 	depends on PACKAGE_kmod-ifxmips-dsl-api

package/ifxmips-dsl-api/Makefile

@@ -34,7 +34,7 @@ define KernelPackage/ifxmips-dsl-api
   TITLE:=DSL CPE API driver
   URL:=http://www.infineon.com/
   MAINTAINER:=Infineon Technologies AG / Lantiq / blogic@openwrt.org
-  DEPENDS:=@TARGET_ifxmips
+  DEPENDS:=@TARGET_ifxmips @BROKEN
   FILES:=$(PKG_BUILD_DIR)/src/mei/ifxmips_mei.$(LINUX_KMOD_SUFFIX) \
 	$(PKG_BUILD_DIR)/src/drv_dsl_cpe_api.$(LINUX_KMOD_SUFFIX) \
 	$(PKG_BUILD_DIR)/src/mei/ifxmips_atm.$(LINUX_KMOD_SUFFIX)
@@ -57,6 +57,17 @@ define KernelPackage/ifxmips-dsl-api/config
 	source "$(SOURCE)/Config.in"
 endef
 
+ifeq ($(CONFIG_IFXMIPS_DSL_FIRMWARE),y)
+FW_FILE:=arcor_A800_452CPW_FW_1.02.206(20081201).bin
+define Download/firmware
+  URL:=http://www.arcor.de/hilfe/files/pdf/
+  FILE=$(FW_FILE)
+  MD5SUM:=19d9af4e369287a0f0abaed415cdac10
+endef
+$(eval $(call Download,firmware))
+
+else
+
 define Download/annex-a
 	FILE:=$(FW_BASE_NAME)_a-$(FW_A_VER).tar.gz
 	URL:=http://mirror2.openwrt.org/sources/
@@ -70,6 +81,7 @@ define Download/annex-b
 	MD5SUM:=$(FW_B_MD5)
 endef
 $(eval $(call Download,annex-b))
+endif
 
 IFX_DSL_MAX_DEVICE=1
 IFX_DSL_LINES_PER_DEVICE=1
@@ -145,7 +157,12 @@ endef
 
 define KernelPackage/ifxmips-dsl-api/install
 	$(INSTALL_DIR) $(1)/lib/firmware/
+ifeq ($(CONFIG_IFXMIPS_DSL_FIRMWARE),y)
+	$(PLATFORM_DIR)/extract.sh $(DL_DIR) '$(FW_FILE)' 
+	$(CP) $(DL_DIR)/dsl_$(if $(CONFIG_IFXMIPS_ANNEX_A),a,b).bin $(1)/lib/firmware/ModemHWE.bin
+else
 	$(CP) $(PKG_BUILD_DIR)/$(FW_BASE_NAME)_$(if $(CONFIG_IFXMIPS_ANNEX_A),a_$(FW_A_FILE_VER),b_$(FW_B_FILE_VER)).bin $(1)/lib/firmware/ModemHWE.bin
+endif
 endef
 
 $(eval $(call KernelPackage,ifxmips-dsl-api))

package/ifxmips-dsl-control/Makefile

@@ -24,7 +24,7 @@ define Package/ifxmips-dsl-control
   TITLE:=DSL CPE control application
   URL:=http://www.infineon.com/
   MAINTAINER:=Infineon Technologies AG / Lantiq / blogic@openwrt.org
-  DEPENDS:=+kmod-ifxmips-dsl-api +libpthread
+  DEPENDS:=+kmod-ifxmips-dsl-api +libpthread @BROKEN
 endef
 
 define Package/ifxmips-dsl-control/description

package/ifxos/Makefile

@@ -10,20 +10,20 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=lib_ifxos
-PKG_VERSION:=1.5.10
+PKG_VERSION:=1.5.12
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_RELEASE:=1
 PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
-PKG_MD5SUM:=3602797b0f531f37546c6beb748d50cf
+PKG_MD5SUM:=ba775356bdd5e1b73b3e11a152710ed6
 
 include $(INCLUDE_DIR)/package.mk
 
 define KernelPackage/ifxos
-  SUBMENU:=Lantiq
+  SUBMENU:=Other modules
   TITLE:=Lantiq OS abstraction library
   URL:=http://www.lantiq.com/
   MAINTAINER:=Lantiq
-  DEPENDS:=@TARGET_ifxmips
+  DEPENDS:=@TARGET_ifxmips @BROKEN
   FILES:=$(PKG_BUILD_DIR)/src/drv_ifxos.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,10,drv_ifxos)
 endef

package/ifxos/patches/100-portability.patch

@@ -1,23 +1,8 @@
---- a/configure.in
-+++ b/configure.in
-@@ -149,12 +149,12 @@ AC_ARG_ENABLE(targetincl,
-        echo Set the target image include path $enableval
-        AC_SUBST([TARGET_INCL_PATH],[$enableval])
-     else
--       echo -e Set the default target image include path $DEFAULT_TARGET_INCL_PATH
-+       echo Set the default target image include path $DEFAULT_TARGET_INCL_PATH
-        AC_SUBST([TARGET_INCL_PATH],[$DEFAULT_TARGET_INCL_PATH])
-     fi
-    ],
-    [
--      echo -e Set the default target image include path $DEFAULT_TARGET_INCL_PATH
-+      echo Set the default target image include path $DEFAULT_TARGET_INCL_PATH
-       AC_SUBST([TARGET_INCL_PATH],[$DEFAULT_TARGET_INCL_PATH])
-    ]
- )
---- a/src/Makefile.am
-+++ b/src/Makefile.am
-@@ -610,7 +610,7 @@ if KERNEL_2_6
+Index: lib_ifxos-1.5.12/src/Makefile.am
+===================================================================
+--- lib_ifxos-1.5.12.orig/src/Makefile.am	2010-01-08 18:12:15.000000000 +0100
++++ lib_ifxos-1.5.12/src/Makefile.am	2010-03-31 18:56:12.000000000 +0200
+@@ -639,7 +639,7 @@
  drv_ifxos_OBJS = "$(subst .c,.o,$(filter %.c,$(drv_ifxos_SOURCES)))"
  
  drv_ifxos.ko: $(drv_ifxos_SOURCES)
@@ -26,7 +11,7 @@
  	if test ! -e common/ifxos_debug.c ; then \
  		echo "copy source files (as links only!)"; \
  		for f in $(filter %.c,$(drv_ifxos_SOURCES)); do \
-@@ -618,10 +618,10 @@ drv_ifxos.ko: $(drv_ifxos_SOURCES)
+@@ -647,10 +647,10 @@
  			cp -s $(addprefix @abs_srcdir@/,$$f) $(PWD)/`dirname $$f`/ ; \
  		done \
  	fi

package/kernel/modules/other.mk

@@ -261,7 +261,7 @@ $(eval $(call KernelPackage,ssb))
 define KernelPackage/bluetooth
   SUBMENU:=$(OTHER_MENU)
   TITLE:=Bluetooth support
-  DEPENDS:=@USB_SUPPORT +kmod-usb-core +kmod-hid
+  DEPENDS:=@USB_SUPPORT +kmod-usb-core +!TARGET_x86:kmod-hid
   KCONFIG:= \
 	CONFIG_BLUEZ \
 	CONFIG_BLUEZ_L2CAP \
@@ -651,7 +651,7 @@ $(eval $(call KernelPackage,sc520-wdt))
 define KernelPackage/input-core
   SUBMENU:=$(OTHER_MENU)
   TITLE:=Input device core
-  DEPENDS:=@LINUX_2_6
+  DEPENDS:=@LINUX_2_6 @!TARGET_x86
   KCONFIG:=CONFIG_INPUT
   FILES:=$(LINUX_DIR)/drivers/input/input-core.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,19,input-core)
@@ -667,7 +667,7 @@ $(eval $(call KernelPackage,input-core))
 define KernelPackage/input-evdev
   SUBMENU:=$(OTHER_MENU)
   TITLE:=Input event device
-  DEPENDS:=+kmod-input-core
+  DEPENDS:=+!TARGET_x86:kmod-input-core
   KCONFIG:=CONFIG_INPUT_EVDEV
   FILES:=$(LINUX_DIR)/drivers/input/evdev.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,60,evdev)
@@ -683,7 +683,7 @@ $(eval $(call KernelPackage,input-evdev))
 define KernelPackage/hid
   SUBMENU:=$(OTHER_MENU)
   TITLE:=HID Devices
-  DEPENDS:=+kmod-input-core +kmod-input-evdev
+  DEPENDS:=+kmod-input-core +kmod-input-evdev @!TARGET_x86
   KCONFIG:=CONFIG_HID
   FILES:=$(LINUX_DIR)/drivers/hid/hid.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,61,hid)
@@ -699,7 +699,7 @@ $(eval $(call KernelPackage,hid))
 define KernelPackage/input-polldev
   SUBMENU:=$(OTHER_MENU)
   TITLE:=Polled Input device support
-  DEPENDS:=+kmod-input-core @LINUX_2_6
+  DEPENDS:=+!TARGET_x86:kmod-input-core @LINUX_2_6
   KCONFIG:=CONFIG_INPUT_POLLDEV
   FILES:=$(LINUX_DIR)/drivers/input/input-polldev.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,20,input-polldev)
@@ -715,7 +715,7 @@ $(eval $(call KernelPackage,input-polldev))
 define KernelPackage/input-gpio-keys
   SUBMENU:=$(OTHER_MENU)
   TITLE:=GPIO key support
-  DEPENDS:= @GPIO_SUPPORT +kmod-input-core
+  DEPENDS:= @GPIO_SUPPORT +!TARGET_x86:kmod-input-core
   KCONFIG:=CONFIG_KEYBOARD_GPIO
   FILES:=$(LINUX_DIR)/drivers/input/keyboard/gpio_keys.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,60,gpio_keys)
@@ -749,7 +749,7 @@ $(eval $(call KernelPackage,input-gpio-buttons))
 define KernelPackage/input-joydev
   SUBMENU:=$(OTHER_MENU)
   TITLE:=Joystick device support
-  DEPENDS:=+kmod-input-core
+  DEPENDS:=+!TARGET_x86:kmod-input-core
   KCONFIG:=CONFIG_INPUT_JOYDEV
   FILES:=$(LINUX_DIR)/drivers/input/joydev.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,62,joydev)

package/kernel/modules/usb.mk

@@ -777,7 +777,7 @@ $(eval $(call KernelPackage,usb-net-rndis))
 
 
 define KernelPackage/usb-hid
-$(call KernelPackage/usb/Depends,@LINUX_2_6 +kmod-input-core +kmod-input-evdev +kmod-hid)
+$(call KernelPackage/usb/Depends,@LINUX_2_6 +!TARGET_x86:kmod-input-core +kmod-input-evdev +!TARGET_x86:kmod-hid)
   TITLE:=Support for USB Human Input Devices
   KCONFIG:=CONFIG_HID_SUPPORT=y CONFIG_USB_HID
   FILES:=$(LINUX_DIR)/drivers/$(USBHID_DIR)/usbhid.ko
@@ -793,7 +793,7 @@ $(eval $(call KernelPackage,usb-hid))
 
 
 define KernelPackage/usb-yealink
-$(call KernelPackage/usb/Depends,@LINUX_2_6 +kmod-input-core +kmod-input-evdev)
+$(call KernelPackage/usb/Depends,@LINUX_2_6 +!TARGET_x86:kmod-input-core +kmod-input-evdev)
   TITLE:=USB Yealink VOIP phone
   KCONFIG:=CONFIG_USB_YEALINK CONFIG_INPUT_YEALINK CONFIG_INPUT=m CONFIG_INPUT_MISC=y
   FILES:=$(LINUX_DIR)/drivers/$(USBINPUT_DIR)/yealink.ko
@@ -808,7 +808,7 @@ $(eval $(call KernelPackage,usb-yealink))
 
 
 define KernelPackage/usb-cm109
-$(call KernelPackage/usb/Depends,@LINUX_2_6 +kmod-input-core +kmod-input-evdev)
+$(call KernelPackage/usb/Depends,@LINUX_2_6 +!TARGET_x86:kmod-input-core +kmod-input-evdev)
   TITLE:=Support for CM109 device
   KCONFIG:=CONFIG_USB_CM109 CONFIG_INPUT_CM109 CONFIG_INPUT=m CONFIG_INPUT_MISC=y
   FILES:=$(LINUX_DIR)/drivers/$(USBINPUT_DIR)/cm109.ko

package/lua/Makefile

@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=lua
 PKG_VERSION:=5.1.4
-PKG_RELEASE:=5
+PKG_RELEASE:=6
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=http://www.lua.org/ftp/ \

package/mac80211/Config.in.rt2x00

@@ -0,0 +1,15 @@
+# rt2x00 configuration
+
+config PACKAGE_RT2X00_LIB_DEBUGFS
+	bool "Enable rt2x00 debugfs support"
+	depends PACKAGE_kmod-rt2x00-lib && PACKAGE_MAC80211_DEBUGFS
+	---help---
+	  Enable creation of debugfs files for the rt2x00 drivers.
+	  These debugfs files support both reading and writing of the
+	  most important register types of the rt2x00 hardware.
+
+config PACKAGE_RT2X00_DEBUG
+	bool "Enable rt2x00 debug output"
+	depends PACKAGE_kmod-rt2x00-lib
+	---help---
+	  Enable debugging output for all rt2x00 modules

package/mac80211/Makefile

@@ -11,7 +11,7 @@ include $(INCLUDE_DIR)/kernel.mk
 PKG_NAME:=mac80211
 
 PKG_VERSION:=2010-03-24
-PKG_RELEASE:=3
+PKG_RELEASE:=5
 PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
 #	http://www.orbit-lab.org/kernel/compat-wireless-2.6/2010/11 \
 #	http://wireless.kernel.org/download/compat-wireless-2.6
@@ -42,12 +42,12 @@ define KernelPackage/cfg80211
   $(call KernelPackage/mac80211/Default)
   TITLE:=cfg80211 - wireless configuration API
   DEPENDS+= +wireless-tools +iw @!LINUX_2_6_25
-ifeq ($(strip $(call CompareKernelPatchVer,$(KERNEL_PATCHVER),ge,2.6.33)),1) 
+ifeq ($(strip $(call CompareKernelPatchVer,$(KERNEL_PATCHVER),ge,2.6.33)),1)
   FILES:= \
 	$(PKG_BUILD_DIR)/compat/compat.$(LINUX_KMOD_SUFFIX) \
 	$(PKG_BUILD_DIR)/net/wireless/cfg80211.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,20,compat cfg80211)
-else 
+else
   FILES:= \
 	$(PKG_BUILD_DIR)/compat/compat.$(LINUX_KMOD_SUFFIX) \
 	$(PKG_BUILD_DIR)/compat/compat_firmware_class.$(LINUX_KMOD_SUFFIX) \
@@ -170,6 +170,11 @@ define Download/ar9170
 endef
 $(eval $(call Download,ar9170))
 
+NEED_RT2X00_LIB_CRYPTO:=y
+NEED_RT2X00_LIB_FIRMWARE:=y
+NEED_RT2X00_LIB_HT:=y
+NEED_RT2X00_LIB_LEDS:=y
+
 define KernelPackage/rt2x00/Default
   $(call KernelPackage/mac80211/Default)
   TITLE:=Ralink Drivers for RT2x00 cards
@@ -177,15 +182,19 @@ endef
 
 define KernelPackage/rt2x00-lib
 $(call KernelPackage/rt2x00/Default)
-  DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT) +kmod-mac80211 +kmod-crc-itu-t
+  DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT||TARGET_ramips) +kmod-mac80211 +kmod-crc-itu-t
   TITLE+= (LIB)
   FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2x00lib.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,25,rt2x00lib)
 endef
 
+define KernelPackage/rt2x00-lib/config
+	source "$(SOURCE)/Config.in.rt2x00"
+endef
+
 define KernelPackage/rt2x00-pci
 $(call KernelPackage/rt2x00/Default)
-  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-lib +kmod-eeprom-93cx6
+  DEPENDS+= @(PCI_SUPPORT||TARGET_ramips) +kmod-rt2x00-lib +kmod-eeprom-93cx6
   TITLE+= (PCI)
   FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2x00pci.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,26,rt2x00pci)
@@ -199,9 +208,17 @@ $(call KernelPackage/rt2x00/Default)
   AUTOLOAD:=$(call AutoLoad,26,rt2x00usb)
 endef
 
+define KernelPackage/rt2x00-soc
+$(call KernelPackage/rt2x00/Default)
+  DEPENDS+= @TARGET_ramips +kmod-rt2x00-lib
+  TITLE+= (SoC)
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2x00soc.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,26,rt2x00soc)
+endef
+
 define KernelPackage/rt2800-lib
 $(call KernelPackage/rt2x00/Default)
-  DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT) +kmod-rt2x00-lib +USB_SUPPORT:kmod-rt2x00-usb
+  DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT||TARGET_ramips) +kmod-rt2x00-lib +USB_SUPPORT:kmod-rt2x00-usb +TARGET_ramips:kmod-rt2x00-soc
   TITLE+= (rt2800 LIB)
   FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2800lib.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,27,rt2800lib)
@@ -249,7 +266,7 @@ endef
 
 define KernelPackage/rt2800-pci
 $(call KernelPackage/rt2x00/Default)
-  DEPENDS+= +kmod-rt2x00-pci +kmod-rt2800-lib +kmod-crc-ccitt
+  DEPENDS+= +kmod-rt2x00-pci +kmod-rt2800-lib +kmod-crc-ccitt +TARGET_ramips:kmod-rt2x00-soc
   TITLE+= (RT2860 PCI)
   FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2800pci.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,28,rt2800pci)
@@ -599,7 +616,18 @@ BUILDFLAGS:= \
 	$(if $(CONFIG_PACKAGE_ATH_DEBUG),-DCONFIG_ATH_DEBUG) \
 	-D__CONFIG_MAC80211_RC_DEFAULT=minstrel \
 	$(if $(CONFIG_ATH_USER_REGD),-DATH_USER_REGD=1) \
-	$(if $(CONFIG_PACKAGE_ATH9K_USE_MINSTREL),-DATH9K_USE_MINSTREL)
+	$(if $(CONFIG_PACKAGE_ATH9K_USE_MINSTREL),-DATH9K_USE_MINSTREL) \
+	$(if $(CONFIG_PACKAGE_RT2X00_LIB_DEBUGFS),-DCONFIG_RT2X00_LIB_DEBUGFS) \
+	$(if $(CONFIG_PACKAGE_RT2X00_DEBUG),-DCONFIG_RT2X00_DEBUG) \
+	$(if $(NEED_RT2X00_LIB_HT),-DCONFIG_RT2X00_LIB_HT) \
+	$(if $(NEED_RT2X00_LIB_CRYPTO),-DCONFIG_RT2X00_LIB_CRYPTO) \
+	$(if $(NEED_RT2X00_LIB_FIRMWARE),-DCONFIG_RT2X00_LIB_FIRMWARE) \
+	$(if $(NEED_RT2X00_LIB_LEDS),-DCONFIG_RT2X00_LIB_LEDS) \
+	$(if $(CONFIG_PACKAGE_kmod-rt2x00-pci),-DCONFIG_RT2X00_LIB_PCI) \
+	$(if $(CONFIG_PACKAGE_kmod-rt2x00-usb),-DCONFIG_RT2X00_LIB_USB) \
+	$(if $(CONFIG_PACKAGE_kmod-rt2x00-soc),-DCONFIG_RT2X00_LIB_SOC) \
+	$(if $(CONFIG_PCI_SUPPORT),-DCONFIG_RT2800PCI_PCI) \
+	$(if $(CONFIG_TARGET_ramips),-DCONFIG_RT2800PCI_SOC) \
 
 MAKE_OPTS:= \
 	CROSS_COMPILE="$(KERNEL_CROSS)" \
@@ -638,6 +666,12 @@ MAKE_OPTS:= \
 	CONFIG_RT2X00_LIB=$(if $(CONFIG_PACKAGE_kmod-rt2x00-lib),m) \
 	CONFIG_RT2X00_LIB_PCI=$(if $(CONFIG_PACKAGE_kmod-rt2x00-pci),m) \
 	CONFIG_RT2X00_LIB_USB=$(if $(CONFIG_PACKAGE_kmod-rt2x00-usb),m) \
+	CONFIG_RT2X00_LIB_SOC=$(if $(CONFIG_PACKAGE_kmod-rt2x00-soc),m) \
+	CONFIG_RT2X00_LIB_DEBUGFS=$(CONFIG_PACKAGE_RT2X00_LIB_DEBUGFS) \
+	CONFIG_RT2X00_LIB_CRYPTO=$(NEED_RT2X00_LIB_CRYPTO) \
+	CONFIG_RT2X00_LIB_FIRMWARE=$(NEED_RT2X00_LIB_FIRMWARE) \
+	CONFIG_RT2X00_LIB_HT=$(NEED_RT2X00_LIB_HT) \
+	CONFIG_RT2X00_LIB_LEDS=$(NEED_RT2X00_LIB_LEDS) \
 	CONFIG_RT2400PCI=$(if $(CONFIG_PACKAGE_kmod-rt2400-pci),m) \
 	CONFIG_RT2500PCI=$(if $(CONFIG_PACKAGE_kmod-rt2500-pci),m) \
 	CONFIG_RT2500USB=$(if $(CONFIG_PACKAGE_kmod-rt2500-usb),m) \
@@ -645,6 +679,8 @@ MAKE_OPTS:= \
 	CONFIG_RT73USB=$(if $(CONFIG_PACKAGE_kmod-rt73-usb),m) \
 	CONFIG_RT2800_LIB=$(if $(CONFIG_PACKAGE_kmod-rt2800-lib),m) \
 	CONFIG_RT2800PCI=$(if $(CONFIG_PACKAGE_kmod-rt2800-pci),m) \
+	CONFIG_RT2800PCI_PCI=$(if $(CONFIG_PCI_SUPPORT),y) \
+	CONFIG_RT2800PCI_SOC=$(if $(CONFIG_TARGET_ramips),y) \
 	CONFIG_RT2800USB=$(if $(CONFIG_PACKAGE_kmod-rt2800-usb),m) \
 	CONFIG_RTL8180=$(if $(CONFIG_PACKAGE_kmod-rtl8180),m) \
 	CONFIG_RTL8187=$(if $(CONFIG_PACKAGE_kmod-rtl8187),m) \
@@ -843,6 +879,7 @@ $(eval $(call KernelPackage,p54-usb))
 $(eval $(call KernelPackage,rt2x00-lib))
 $(eval $(call KernelPackage,rt2x00-pci))
 $(eval $(call KernelPackage,rt2x00-usb))
+$(eval $(call KernelPackage,rt2x00-soc))
 $(eval $(call KernelPackage,rt2800-lib))
 $(eval $(call KernelPackage,rt2400-pci))
 $(eval $(call KernelPackage,rt2500-pci))

package/mac80211/patches/015-remove-rt2x00-options.patch

@@ -0,0 +1,26 @@
+--- a/config.mk
++++ b/config.mk
+@@ -276,12 +276,12 @@ CONFIG_RTL8180=m
+ 
+ CONFIG_ADM8211=m
+ 
+-CONFIG_RT2X00_LIB_PCI=m
++# CONFIG_RT2X00_LIB_PCI=m
+ CONFIG_RT2400PCI=m
+ CONFIG_RT2500PCI=m
+ ifneq ($(CONFIG_CRC_CCITT),)
+ CONFIG_RT2800PCI=m
+-CONFIG_RT2800PCI_PCI=y
++# CONFIG_RT2800PCI_PCI=y
+ # CONFIG_RT2800PCI_RT30XX=y
+ # CONFIG_RT2800PCI_RT35XX=y
+ # CONFIG_RT2800PCI_SOC=y
+@@ -381,7 +381,7 @@ CONFIG_RT2800USB=m
+ # CONFIG_RT2800USB_RT35XX=y
+ # CONFIG_RT2800USB_UNKNOWN=y
+ endif
+-CONFIG_RT2X00_LIB_USB=m
++# CONFIG_RT2X00_LIB_USB=m
+ NEED_RT2X00=y
+ # RT73USB requires firmware
+ ifneq ($(CONFIG_CRC_ITU_T),)

package/mac80211/patches/300-fix-mesh.patch

@@ -0,0 +1,45 @@
+From 181ce6f71d907f42ab73376ce154015a835a6d8a Mon Sep 17 00:00:00 2001
+From: Javier Cardona <javier@cozybit.com>
+Date: Mon, 29 Mar 2010 11:00:20 -0700
+Subject: [PATCH] mac80211: Handle mesh action frames in ieee80211_rx_h_action
+
+This fixes the problem introduced in commit
+8404080568613d93ad7cf0a16dfb68 which broke mesh peer link establishment.
+
+changes:
+v2 	Added missing break (Johannes)
+v3 	Broke original patch into two (Johannes)
+
+Signed-off-by: Javier Cardona <javier@cozybit.com>
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ net/mac80211/mesh.c |    3 ---
+ net/mac80211/rx.c   |    5 +++++
+ 2 files changed, 5 insertions(+), 3 deletions(-)
+
+--- a/net/mac80211/mesh.c
++++ b/net/mac80211/mesh.c
+@@ -749,9 +749,6 @@ ieee80211_mesh_rx_mgmt(struct ieee80211_
+ 
+ 	switch (fc & IEEE80211_FCTL_STYPE) {
+ 	case IEEE80211_STYPE_ACTION:
+-		if (skb->len < IEEE80211_MIN_ACTION_SIZE)
+-			return RX_DROP_MONITOR;
+-		/* fall through */
+ 	case IEEE80211_STYPE_PROBE_RESP:
+ 	case IEEE80211_STYPE_BEACON:
+ 		skb_queue_tail(&ifmsh->skb_queue, skb);
+--- a/net/mac80211/rx.c
++++ b/net/mac80211/rx.c
+@@ -1964,6 +1964,11 @@ ieee80211_rx_h_action(struct ieee80211_r
+ 			goto handled;
+ 		}
+ 		break;
++	case MESH_PLINK_CATEGORY:
++	case MESH_PATH_SEL_CATEGORY:
++		if (ieee80211_vif_is_mesh(&sdata->vif))
++			return ieee80211_mesh_rx_mgmt(sdata, rx->skb);
++		break;
+ 	}
+ 
+ 	/*

package/mac80211/patches/600-rt2x00-disable-pci-code-if-CONFIG_PCI-not-defined.patch

@@ -0,0 +1,18 @@
+--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
++++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
+@@ -223,6 +223,7 @@ void rt2x00pci_uninitialize(struct rt2x0
+ }
+ EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
+ 
++#ifdef CONFIG_PCI
+ /*
+  * PCI driver handlers.
+  */
+@@ -397,6 +398,7 @@ int rt2x00pci_resume(struct pci_dev *pci
+ }
+ EXPORT_SYMBOL_GPL(rt2x00pci_resume);
+ #endif /* CONFIG_PM */
++#endif /* CONFIG_PCI */
+ 
+ /*
+  * rt2x00pci module information.

package/mac80211/patches/601-rt2x00-lib-use-rt2x00dev-irq.patch

@@ -0,0 +1,11 @@
+--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
++++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
+@@ -213,7 +213,7 @@ void rt2x00pci_uninitialize(struct rt2x0
+ 	/*
+ 	 * Free irq line.
+ 	 */
+-	free_irq(to_pci_dev(rt2x00dev->dev)->irq, rt2x00dev);
++	free_irq(rt2x00dev->irq, rt2x00dev);
+ 
+ 	/*
+ 	 * Free DMA

package/mac80211/patches/602-rt2x00-remove-mcu-requests-for-soc.patch

@@ -0,0 +1,59 @@
+The ralink SoC platforms do not have an MCU.
+
+Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
+---
+
+--- a/drivers/net/wireless/rt2x00/rt2800lib.c
++++ b/drivers/net/wireless/rt2x00/rt2800lib.c
+@@ -221,9 +221,9 @@ void rt2800_mcu_request(struct rt2x00_de
+ 	u32 reg;
+ 
+ 	/*
+-	 * SOC devices don't support MCU requests.
++	 * some devices don't support MCU requests.
+ 	 */
+-	if (rt2x00_is_soc(rt2x00dev))
++	if (!test_bit(DRIVER_REQUIRE_MCU, &rt2x00dev->flags))
+ 		return;
+ 
+ 	mutex_lock(&rt2x00dev->csr_mutex);
+--- a/drivers/net/wireless/rt2x00/rt2800pci.c
++++ b/drivers/net/wireless/rt2x00/rt2800pci.c
+@@ -60,6 +60,12 @@ static void rt2800pci_mcu_status(struct 
+ 	unsigned int i;
+ 	u32 reg;
+ 
++	/*
++	 * some devices don't support MCU requests.
++	 */
++	if (!test_bit(DRIVER_REQUIRE_MCU, &rt2x00dev->flags))
++		return;
++
+ 	for (i = 0; i < 200; i++) {
+ 		rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
+ 
+@@ -1098,10 +1104,12 @@ static int rt2800pci_probe_hw(struct rt2
+ 	__set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
+ 
+ 	/*
+-	 * This device requires firmware.
++	 * This device requires firmware and MCU access.
+ 	 */
+-	if (!rt2x00_is_soc(rt2x00dev))
++	if (!rt2x00_is_soc(rt2x00dev)){
+ 		__set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
++		__set_bit(DRIVER_REQUIRE_MCU, &rt2x00dev->flags);
++	}
+ 	__set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
+ 	__set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
+ 	if (!modparam_nohwcrypt)
+--- a/drivers/net/wireless/rt2x00/rt2x00.h
++++ b/drivers/net/wireless/rt2x00/rt2x00.h
+@@ -631,6 +631,7 @@ enum rt2x00_flags {
+ 	 * Driver requirements
+ 	 */
+ 	DRIVER_REQUIRE_FIRMWARE,
++	DRIVER_REQUIRE_MCU,
+ 	DRIVER_REQUIRE_BEACON_GUARD,
+ 	DRIVER_REQUIRE_ATIM_QUEUE,
+ 	DRIVER_REQUIRE_DMA,

package/openssl/Makefile

@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=openssl
 PKG_VERSION:=0.9.8m
-PKG_RELEASE:=2
+PKG_RELEASE:=3
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=http://www.openssl.org/source/ \

package/openssl/patches/400-cve-2010-0740.patch

@@ -0,0 +1,15 @@
+--- a/ssl/s3_pkt.c
++++ b/ssl/s3_pkt.c
+@@ -291,9 +291,9 @@ again:
+ 			if (version != s->version)
+ 				{
+ 				SSLerr(SSL_F_SSL3_GET_RECORD,SSL_R_WRONG_VERSION_NUMBER);
+-				/* Send back error using their
+-				 * version number :-) */
+-				s->version=version;
++                                if ((s->version & 0xFF00) == (version & 0xFF00))
++                                	/* Send back error using their minor version number :-) */
++					s->version = (unsigned short)version;
+ 				al=SSL_AD_PROTOCOL_VERSION;
+ 				goto f_err;
+ 				}

package/uboot-ifxmips/Makefile

@@ -23,7 +23,7 @@ include $(INCLUDE_DIR)/package.mk
 define Package/uboot-ifxmips
   SECTION:=boot
   CATEGORY:=Boot Loaders
-  DEPENDS:=@TARGET_ifxmips
+  DEPENDS:=@TARGET_ifxmips @BROKEN
   TITLE:=U-Boot for Infineon MIPS boards
   URL:=http://www.denx.de/wiki/U-Boot
 endef

package/uboot-lantiq/Config.in

@@ -0,0 +1,35 @@
+config UBOOT_TARGET
+	string "target"
+	default "easy50712_DDR166M"
+	depends on PACKAGE_uboot-lantiq
+	help
+	  The configuration reflects the settings for a dedicated board hardware.
+	  Select for Danube evaluation board easy50712_DDR166M .
+	  Select for AR9 evaluation board easy50812_DDR166M .
+
+config UBOOT_RAMBOOT
+	bool "Enable RAM boot image"
+	depends on PACKAGE_uboot-lantiq
+	help
+	  Using the UART boot mode of the ROM code this image could be loaded to the RAM.
+	  While executing the image in the RAM the functionality of the uboot image can be 
+	  tested first without touching the original flash.
+	  Note: Be carefull, by saving the environment the flash will be modified.
+	  The OWRT flash layout differs from the layout provided by Lantiq / Infineon.
+
+config UBOOT_RAMBOOT_DDR_CONFIG
+	string "DDR configuration file"
+	default "easy50712_DDR166M.conf"
+	depends on UBOOT_RAMBOOT
+	help
+	  The DDR configuration file should reflect the DDR memory device configuration .
+	  It will be used to create a RAM boot image
+	  Select for Danube evalution board easy50712_DDR166M.conf .
+	  Select for AR9 evalution board easy50812.conf .
+
+
+config UBOOT_A800
+	bool "add ARV452 Switch bringup hack"
+	depends on PACKAGE_uboot-lantiq
+	help
+	  Say Y, if you have a arv452 board (wav-281, A800, ..)

package/uboot-lantiq/Makefile

@@ -20,6 +20,10 @@ PKG_TARGETS:=bin
 
 include $(INCLUDE_DIR)/package.mk
 
+ifeq ($(DUMP),)
+  STAMP_CONFIGURED:=$(strip $(STAMP_CONFIGURED))_$(shell grep '^CONFIG_UBOOT_' $(TOPDIR)/.config | md5s)
+endif
+
 define Package/uboot-lantiq
   SECTION:=boot
   CATEGORY:=Boot Loaders
@@ -35,12 +39,18 @@ define Build/Prepare
 	find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
 endef
 
-UBOOT_CONFIG:=easy50712_DDR166M
+UBOOT_TARGET:=$(call qstrip,$(CONFIG_UBOOT_TARGET))
+UBOOT_RAMBOOT_DDR_CONFIG:=$(call qstrip,$(CONFIG_UBOOT_RAMBOOT_DDR_CONFIG))
+
 UBOOT_MAKE_OPTS:= \
 	CROSS_COMPILE=$(TARGET_CROSS) \
 	ENDIANNESS= \
 	V=1
 
+define Package/uboot-lantiq/config
+	source "$(SOURCE)/Config.in"
+endef
+
 define Build/Configure/Target
 	$(MAKE) -s -C $(PKG_BUILD_DIR) \
 		$(UBOOT_MAKE_OPTS) \
@@ -49,8 +59,10 @@ define Build/Configure/Target
 endef
 
 define Build/Configure
-	$(call Build/Configure/Target,$(UBOOT_CONFIG))
-	$(call Build/Configure/Target,$(UBOOT_CONFIG)_ramboot)
+	$(call Build/Configure/Target,$(UBOOT_TARGET))
+ifeq ($(CONFIG_UBOOT_RAMBOOT),y)
+	$(call Build/Configure/Target,$(UBOOT_TARGET)_ramboot)
+endif
 endef
 
 define Build/Compile/Target
@@ -61,22 +73,26 @@ define Build/Compile/Target
 endef
 
 define Build/Compile
-	$(call Build/Compile/Target,$(UBOOT_CONFIG))
-	$(call Build/Compile/Target,$(UBOOT_CONFIG)_ramboot)
+	$(call Build/Compile/Target,$(UBOOT_TARGET))
+ifeq ($(CONFIG_UBOOT_RAMBOOT),y)
+	$(call Build/Compile/Target,$(UBOOT_TARGET)_ramboot)
+endif
 endef
 
 define Package/uboot-lantiq/install
-	mkdir -p $(1)/$(UBOOT_CONFIG)
+	mkdir -p $(1)/$(UBOOT_TARGET)
 	dd \
-		if=$(PKG_BUILD_DIR)/$(UBOOT_CONFIG)/u-boot.bin \
-		of=$(1)/$(UBOOT_CONFIG)/u-boot.bin \
+		if=$(PKG_BUILD_DIR)/$(UBOOT_TARGET)/u-boot.bin \
+		of=$(1)/$(UBOOT_TARGET)/u-boot.bin \
 		bs=64k conv=sync
-	if [ -e $(UBOOT_CONFIG).conf ]; then \
+ifeq ($(CONFIG_UBOOT_RAMBOOT),y)
+	if [ -e $(UBOOT_RAMBOOT_DDR_CONFIG) ]; then \
 		perl ./gct \
-			$(UBOOT_CONFIG).conf \
-			$(PKG_BUILD_DIR)/$(UBOOT_CONFIG)_ramboot/u-boot.srec \
-			$(1)/$(UBOOT_CONFIG)/u-boot.asc; \
+			$(UBOOT_RAMBOOT_DDR_CONFIG) \
+			$(PKG_BUILD_DIR)/$(UBOOT_TARGET)_ramboot/u-boot.srec \
+			$(1)/$(UBOOT_TARGET)/u-boot.asc; \
 	fi
+endif
 endef
 
 $(eval $(call BuildPackage,uboot-lantiq))

package/uboot-lantiq/easy50812.conf

@@ -0,0 +1,55 @@
+0xbf800060 0x0000000f
+0xbf800010 0x00000000
+0xbf800020 0x00000000
+0xbf800200 0x00000002
+0xbf800210 0x00000000
+0xbf801000 0x00001b1b
+0xbf801010 0x00000000
+0xbf801020 0x00000000
+0xbf801030 0x00000000
+0xbf801040 0x00000000
+0xbf801050 0x00000200
+0xbf801060 0x00000306
+0xbf801070 0x00000303
+0xbf801080 0x00000102
+0xbf801090 0x0000070a
+0xbf8010a0 0x00000203
+0xbf8010b0 0x00000c02
+0xbf8010c0 0x000001c8
+0xbf8010d0 0x00000001
+0xbf8010e0 0x00000000
+0xbf8010f0 0x00000139
+0xbf801100 0x00002200
+0xbf801110 0x0000000d
+0xbf801120 0x00000301
+0xbf801130 0x00000200
+0xbf801140 0x00000a04
+0xbf801150 0x00001800
+0xbf801160 0x00001818
+0xbf801170 0x00000000
+0xbf801180 0x00000059
+0xbf801190 0x00000000
+0xbf8011a0 0x00000000
+0xbf8011b0 0x00000000
+0xbf8011c0 0x00000514
+0xbf8011d0 0x00002d93
+0xbf8011e0 0x00008235
+0xbf8011f0 0x00000000
+0xbf801200 0x00000000
+0xbf801210 0x00000000
+0xbf801220 0x00000000
+0xbf801230 0x00000000
+0xbf801240 0x00000000
+0xbf801250 0x00000000
+0xbf801260 0x00000000
+0xbf801270 0x00000000
+0xbf801280 0x00000000
+0xbf801290 0x00000000
+0xbf8012a0 0x00000000
+0xbf8012b0 0x00000000
+0xbf8012c0 0x00000000
+0xbf8012d0 0x00000600
+0xbf8012e0 0x00000000
+0xbf800060 0x0000000d
+0xbf801030 0x00000100
+

package/uboot-lantiq/files/board/infineon/easy50712/danube.c

@@ -32,6 +32,9 @@
 #include <asm/danube.h>
 #include <asm/reboot.h>
 #include <asm/io.h>
+#if defined(CONFIG_CMD_HTTPD)
+#include <httpd.h>
+#endif
 
 extern ulong ifx_get_ddr_hz(void);
 extern ulong ifx_get_cpuclk(void);
@@ -336,3 +339,56 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+#if defined(CONFIG_CMD_HTTPD)
+int do_http_upgrade(const unsigned char *data, const ulong size)
+{
+	char buf[128];
+
+	if(getenv ("ram_addr") == NULL)
+		return -1;
+	if(getenv ("kernel_addr") == NULL)
+		return -1;
+	/* check the image */
+	if(run_command("imi ${ram_addr}", 0) < 0) {
+		return -1;
+	}
+	/* write the image to the flash */
+	puts("http ugrade ...\n");
+	sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size);
+	return run_command(buf, 0);
+}
+
+int do_http_progress(const int state)
+{
+	/* toggle LED's here */
+	switch(state) {
+		case HTTP_PROGRESS_START:
+		puts("http start\n");
+		break;
+		case HTTP_PROGRESS_TIMEOUT:
+		puts(".");
+		break;
+		case HTTP_PROGRESS_UPLOAD_READY:
+		puts("http upload ready\n");
+		break;
+		case HTTP_PROGRESS_UGRADE_READY:
+		puts("http ugrade ready\n");
+		break;
+		case HTTP_PROGRESS_UGRADE_FAILED:
+		puts("http ugrade failed\n");
+		break;
+	}
+	return 0;
+}
+
+unsigned long do_http_tmp_address(void)
+{
+	char *s = getenv ("ram_addr");
+	if (s) {
+		ulong tmp = simple_strtoul (s, NULL, 16);
+		return tmp;
+	}
+	return 0 /*0x80a00000*/;
+}
+
+#endif

package/uboot-lantiq/files/board/infineon/easy50812/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+#COBJS	:= $(BOARD).o
+COBJS-y	+= ar9.o
+
+SOBJS	= lowlevel_init.o pmuenable.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

package/uboot-lantiq/files/board/infineon/easy50812/ar9.c

@@ -0,0 +1,619 @@
+/*
+* (C) Copyright 2003
+* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+*
+* (C) Copyright 2010
+* Thomas Langer, Ralph Hempel
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/addrspace.h>
+#include <asm/ar9.h>
+#include <asm/reboot.h>
+#include <asm/io.h>
+#if defined(CONFIG_CMD_HTTPD)
+#include <httpd.h>
+#endif
+
+extern ulong ifx_get_ddr_hz(void);
+extern ulong ifx_get_cpuclk(void);
+
+/* definitions for external PHYs / Switches */
+/* Split values into phy address and register address */
+#define PHYADDR(_reg)	((_reg >> 5) & 0xff), (_reg & 0x1f)
+
+/* IDs and registers of known external switches */
+#define ID_SAMURAI_0			0x1020
+#define ID_SAMURAI_1			0x0007
+#define SAMURAI_ID_REG0			0xA0
+#define SAMURAI_ID_REG1			0xA1
+#define ID_TANTOS			0x2599
+
+#define RGMII_MODE			0
+#define MII_MODE			1
+#define REV_MII_MODE			2
+#define RED_MII_MODE_IC			3		/*Input clock */
+#define RGMII_MODE_100MB		4
+#define TURBO_REV_MII_MODE		6		/*Turbo Rev Mii mode */
+#define RED_MII_MODE_OC			7		/*Output clock */
+#define RGMII_MODE_10MB			8
+
+#define mdelay(n)   udelay((n)*1000)
+
+static void ar9_sw_chip_init(u8 port, u8 mode);
+static void ar9_enable_sw_port(u8 port, u8 state);
+static void ar9_configure_sw_port(u8 port, u8 mode);
+static u16 ar9_smi_reg_read(u16 reg);
+static u16 ar9_smi_reg_write(u16 reg, u16 data);
+static char * const name = "lq_cpe_eth";
+static int external_switch_init(void);
+
+void _machine_restart(void)
+{
+	*AR9_RCU_RST_REQ |= AR9_RST_ALL;
+}
+
+#ifdef CONFIG_SYS_RAMBOOT
+phys_size_t initdram(int board_type)
+{
+	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
+}
+#elif defined(CONFIG_USE_DDR_RAM)
+phys_size_t initdram(int board_type)
+{
+	return (CONFIG_SYS_MAX_RAM);
+}
+#else
+
+static ulong max_sdram_size(void)     /* per Chip Select */
+{
+	/* The only supported SDRAM data width is 16bit.
+	*/
+#define CFG_DW	4
+
+	/* The only supported number of SDRAM banks is 4.
+	*/
+#define CFG_NB	4
+
+	ulong cfgpb0 = *AR9_SDRAM_MC_CFGPB0;
+	int   cols   = cfgpb0 & 0xF;
+	int   rows   = (cfgpb0 & 0xF0) >> 4;
+	ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
+
+	return size;
+}
+
+/*
+* Check memory range for valid RAM. A simple memory test determines
+* the actually available RAM size between addresses `base' and
+* `base + maxsize'.
+*/
+
+static long int dram_size(long int *base, long int maxsize)
+{
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];			/* to make test non-destructive */
+	unsigned char i = 0;
+
+	for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
+}
+
+phys_size_t initdram(int board_type)
+{
+	int   rows, cols, best_val = *AR9_SDRAM_MC_CFGPB0;
+	ulong size, max_size       = 0;
+	ulong our_address;
+
+	/* load t9 into our_address */
+	asm volatile ("move %0, $25" : "=r" (our_address) :);
+
+	/* Can't probe for RAM size unless we are running from Flash.
+	* find out whether running from DRAM or Flash.
+	*/
+	if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
+	{
+		return max_sdram_size();
+	}
+
+	for (cols = 0x8; cols <= 0xC; cols++)
+	{
+		for (rows = 0xB; rows <= 0xD; rows++)
+		{
+			*AR9_SDRAM_MC_CFGPB0 = (0x14 << 8) |
+											(rows << 4) | cols;
+			size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+											max_sdram_size());
+
+			if (size > max_size)
+			{
+				best_val = *AR9_SDRAM_MC_CFGPB0;
+				max_size = size;
+			}
+		}
+	}
+
+	*AR9_SDRAM_MC_CFGPB0 = best_val;
+	return max_size;
+}
+#endif
+
+int checkboard (void)
+{
+	unsigned long chipid = *AR9_MPS_CHIPID;
+	int part_num;
+
+	puts ("Board: ");
+
+	part_num = AR9_MPS_CHIPID_PARTNUM_GET(chipid);
+	switch (part_num)
+	{
+	case 0x16C:
+		puts("ARX188 ");
+		break;
+	case 0x16D:
+		puts("ARX168 ");
+		break;
+	case 0x16F:
+		puts("ARX182 ");
+		break;
+	case 0x170:
+		puts("GRX188 ");
+		break;
+	case 0x171:
+		puts("GRX168 ");
+		break;
+	default:
+		printf ("unknown, chip part number 0x%03X ", part_num);
+		break;
+	}
+	printf ("V1.%ld, ", AR9_MPS_CHIPID_VERSION_GET(chipid));
+
+	printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
+	printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
+
+	return 0;
+}
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+int board_early_init_f(void)
+{
+#ifdef CONFIG_EBU_ADDSEL0
+	(*AR9_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
+#endif
+#ifdef CONFIG_EBU_ADDSEL1
+	(*AR9_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
+#endif
+#ifdef CONFIG_EBU_ADDSEL2
+	(*AR9_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
+#endif
+#ifdef CONFIG_EBU_ADDSEL3
+	(*AR9_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
+#endif
+#ifdef CONFIG_EBU_BUSCON0
+	(*AR9_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
+#endif
+#ifdef CONFIG_EBU_BUSCON1
+	(*AR9_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
+#endif
+#ifdef CONFIG_EBU_BUSCON2
+	(*AR9_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
+#endif
+#ifdef CONFIG_EBU_BUSCON3
+	(*AR9_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
+#endif
+
+	return 0;
+}
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_IFX_ETOP)
+
+	*AR9_PMU_PWDCR &= 0xFFFFEFDF;
+	*AR9_PMU_PWDCR &= ~AR9_PMU_DMA; /* enable DMA from PMU */
+
+	if (lq_eth_initialize(bis) < 0)
+		return -1;
+
+	*AR9_RCU_RST_REQ |= 1;
+	udelay(200000);
+	*AR9_RCU_RST_REQ &= (unsigned long)~1;
+	udelay(1000);
+
+#ifdef CONFIG_EXTRA_SWITCH
+	if (external_switch_init()<0)
+		return -1;
+#endif /* CONFIG_EXTRA_SWITCH */
+#endif /* CONFIG_IFX_ETOP */
+
+	return 0;
+}
+
+static void ar9_configure_sw_port(u8 port, u8 mode)
+{
+	if(port)
+	{
+		if (mode  == 1) //MII mode
+		{
+			*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
+			*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
+			*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0xf000)) | 0x2000;
+			*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x2000;
+		}
+		else if(mode == 2 || mode == 6) //Rev Mii mode
+		{
+			*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
+			*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
+			*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0xf000)) & ~0x2000;
+			*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xd000;
+		}
+	}
+	else //Port 0
+	{
+		if (mode  == 1) //MII mode
+		{
+			*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
+			*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
+			*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0x0303)) | 0x0100;
+			*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0100;
+		}
+		else if(mode ==2 || mode ==6) //Rev Mii mode
+		{
+			*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
+			*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
+			*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0x0303)) & ~0x0100;
+			*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0203;
+		}
+	}
+}
+
+/*
+Call this function to place either MAC port 0 or 1 into working mode.
+Parameters:
+port - select ports 0 or 1.
+state of interface : state
+0: RGMII
+1: MII
+2: Rev MII
+3: Reduce MII (input clock)
+4: RGMII 100mb
+5: Reserve
+6: Turbo Rev MII
+7: Reduce MII (output clock)
+*/
+void ar9_enable_sw_port(u8 port, u8 state)
+{
+	REG32(AR9_SW_GCTL0) |= 0x80000000;
+	if (port == 0)
+	{
+		REG32(AR9_SW_RGMII_CTL) &= 0xffcffc0e ;
+	//#if AR9_REFBOARD_TANTOS
+		REG32(0xbf20302c) &= 0xffff81ff;
+		REG32(0xbf20302c) |= 4<<9 ;
+	//#endif
+		REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<8;
+		if((state &0x3) == 0)
+		{
+			REG32(AR9_SW_RGMII_CTL) &= 0xfffffff3;
+			if(state == 4)
+				REG32(AR9_SW_RGMII_CTL) |= 0x4;
+			else
+				REG32(AR9_SW_RGMII_CTL) |= 0x8;
+		}
+		if(state == 6)
+			REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<20));
+		if(state == 7)
+			REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<21));
+	}
+//  *AR9_PPE32_ETOP_CFG = *AR9_PPE32_ETOP_CFG & 0xfffffffe;
+	else
+	{
+		REG32(AR9_SW_RGMII_CTL) &= 0xff303fff ;
+		REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<18;
+		if((state &0x3) == 0)
+		{
+			REG32(AR9_SW_RGMII_CTL) &= 0xffffcfff;
+			if(state == 4)
+				REG32(AR9_SW_RGMII_CTL) |= 0x1000;
+			else
+				REG32(AR9_SW_RGMII_CTL) |= 0x2000;
+		}
+		if(state == 6)
+			REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<22));
+		if(state == 7)
+			REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<23));
+	}
+}
+
+void pci_reset(void)
+{
+	int i,j;
+#define AR9_V1_PCI_RST_FIX 1
+#if AR9_V1_PCI_RST_FIX // 5th June 2008 Add GPIO19 to control EJTAG_TRST
+	*AR9_GPIO_P1_ALTSEL0 = *AR9_GPIO_P1_ALTSEL0 & ~0x8;
+	*AR9_GPIO_P1_ALTSEL1 = *AR9_GPIO_P1_ALTSEL1 & ~0x8;
+	*AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR | 0x8;
+	*AR9_GPIO_P1_OD = *AR9_GPIO_P1_OD | 0x8;
+	*AR9_GPIO_P1_OUT = *AR9_GPIO_P1_OUT | 0x8;
+	*AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 & ~0x4000;
+	*AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~0x4000;
+	*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | 0x4000;
+	*AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | 0x4000;
+	for(j=0;j<5;j++) {
+		*AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT & ~0x4000;
+		for(i=0;i<0x10000;i++);
+		*AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT | 0x4000;
+		for(i=0;i<0x10000;i++);
+	}
+	*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR &  ~0x4000;
+	*AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR &  ~0x8;
+#endif
+}
+
+static u16 ar9_smi_reg_read(u16 reg)
+{
+	int i;
+	while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
+	REG32(AR9_SW_MDIO_CTL) = 0x8000| 0x2<<10 | ((u32) (reg&0x3ff)) ; /*0x10=MDIO_OP_READ*/
+	for(i=0;i<0x3fff;i++);
+	udelay(50);
+        while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
+	return((u16) (REG32(AR9_SW_MDIO_DATA)));
+}
+
+static u16 ar9_smi_reg_write(u16 reg, u16 data)
+{
+	int i;
+	while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
+	REG32(AR9_SW_MDIO_CTL) = 0x8000| (((u32) data)<<16) | 0x01<<10 | ((u32) (reg&0x3ff)) ; /*0x01=MDIO_OP_WRITE*/
+	for(i=0;i<0x3fff;i++);
+		udelay(50);
+	return 0;
+}
+
+static void ar9_sw_chip_init(u8 port, u8 mode)
+{
+	int i;
+	u16 chipid;
+
+	debug("\nsearching for switches ... ");
+
+	asm("sync");
+	pci_reset();
+
+	/* 25mhz clock out */
+	*AR9_CGU_IFCCR &= ~(3<<10);
+	*AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 | (1<<3);
+	*AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~(1<<3);
+	*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR  | (1<<3);
+	*AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | (1<<3);
+	*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 & ~(1<<0);
+	*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(1<<0);
+	*AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR  | (1<<0);
+	*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | (1<<0);
+
+	*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & 0xFFFBDFDF) ; 
+	*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & ~(AR9_PMU_DMA | AR9_PMU_SWITCH));
+	*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR | AR9_PMU_USB0 | AR9_PMU_USB0_P);
+
+	*AR9_GPIO_P2_OUT &= ~(1<<0);
+	asm("sync");
+
+	ar9_configure_sw_port(port, mode);
+	ar9_enable_sw_port(port, mode);
+	REG32(AR9_SW_P0_CTL) |= 0x400000; /* disable mdio polling for tantos */
+	asm("sync");
+
+	/*GPIO 55(P3.7) used as output, set high*/
+	*AR9_GPIO_P3_OD |=(1<<7);
+	*AR9_GPIO_P3_DIR |= (1<<7);
+	*AR9_GPIO_P3_ALTSEL0 &=~(1<<7);
+	*AR9_GPIO_P3_ALTSEL1 &=~(1<<7);
+	asm("sync");
+	udelay(10);
+
+	*AR9_GPIO_P3_OUT &= ~(1<<7);
+	for(i=0;i<1000;i++)
+		udelay(110);
+	*AR9_GPIO_P3_OUT |=(1<<7);
+	udelay(100);
+
+	if(port==0)
+		REG32(AR9_SW_P0_CTL) |= 0x40001;
+	else
+		REG32(AR9_SW_P1_CTL) |= 0x40001;
+
+	REG32(AR9_SW_P2_CTL) |= 0x40001;
+	REG32(AR9_SW_PMAC_HD_CTL) |= 0x40000; /* enable CRC */
+
+	*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xc00);
+	*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xc00);
+	*AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR  | 0xc00;
+	*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xc00;
+
+	asm("sync");
+	chipid = (unsigned short)(ar9_smi_reg_read(0x101));
+	printf("\nswitch chip id=%08x\n",chipid);
+	if (chipid != ID_TANTOS) {
+		debug("whatever detected\n");
+		ar9_smi_reg_write(0x1,0x840f);
+		ar9_smi_reg_write(0x3,0x840f);
+		ar9_smi_reg_write(0x5,0x840f);
+		ar9_smi_reg_write(0x7,0x840f);
+		ar9_smi_reg_write(0x8,0x840f);
+		ar9_smi_reg_write(0x12,0x3602);
+#ifdef CLK_OUT2_25MHZ
+		ar9_smi_reg_write(0x33,0x4000);
+#endif
+	} else { // Tantos switch ship
+		debug("Tantos switch detected\n");
+		ar9_smi_reg_write(0xa1,0x0004); /*port 5 force link up*/
+		ar9_smi_reg_write(0xc1,0x0004); /*port 6 force link up*/
+		ar9_smi_reg_write(0xf5,0x0BBB); /*port 4 duplex mode, flow control enable,1000Mbit/s*/
+										/*port 5 duplex mode, flow control enable, 1000Mbit/s*/
+										/*port 6 duplex mode, flow control enable, 1000Mbit/s*/
+	}
+	asm("sync");
+
+	/*reset GPHY*/
+	mdelay(200);
+	*AR9_RCU_RST_REQ |= (AR9_RCU_RST_REQ_DMA | AR9_RCU_RST_REQ_PPE) ;
+	udelay(50);
+	*AR9_GPIO_P2_OUT |= (1<<0);
+}
+
+static void ar9_dma_init(void)
+{
+	/* select port */
+	*AR9_DMA_PS = 0;
+
+	/* 
+	TXWGT 14:12 rw Port Weight for Transmit Direction (the default value “001”)
+
+	TXENDI 11:10 rw Endianness for Transmit Direction
+	Determine a byte swap between memory interface (left hand side) and
+	peripheral interface (right hand side).
+	00B B0_B1_B2_B3 No byte switching
+	01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
+	10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
+	
+	RXENDI 9:8 rw Endianness for Receive Direction
+	Determine a byte swap between peripheral (left hand side) and memory
+	interface (right hand side).
+	00B B0_B1_B2_B3 No byte switching
+	01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
+	10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
+	11B B3_B2_B1_B0 B0B1B2B3 => B3B2B1B0 
+
+	TXBL 5:4 rw Burst Length for Transmit Direction
+	Selects burst length for TX direction.
+	Others are reserved and will result in 2_WORDS burst length.
+	01B 2_WORDS 2 words
+	10B 4_WORDS 4 words
+	11B 8_WORDS 8 words
+
+	RXBL 3:2 rw Burst Length for Receive Direction
+	Selects burst length for RX direction.
+	Others are reserved and will result in 2_WORDS burst length.
+	01B 2_WORDS 2 words
+	10B 4_WORDS 4 words
+	11B 8_WORDS 8 words	
+	*/
+	*AR9_DMA_PCTRL = 0x1f28;
+}
+
+#ifdef CONFIG_EXTRA_SWITCH
+static int external_switch_init(void)
+{
+	ar9_sw_chip_init(0, RGMII_MODE);
+
+	ar9_dma_init();
+
+	return 0;
+}
+#endif /* CONFIG_EXTRA_SWITCH */
+
+#if defined(CONFIG_CMD_HTTPD)
+int do_http_upgrade(const unsigned char *data, const ulong size)
+{
+	char buf[128];
+
+	if(getenv ("ram_addr") == NULL)
+		return -1;
+	if(getenv ("kernel_addr") == NULL)
+		return -1;
+	/* check the image */
+	if(run_command("imi ${ram_addr}", 0) < 0) {
+		return -1;
+	}
+	/* write the image to the flash */
+	puts("http ugrade ...\n");
+	sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size);
+	return run_command(buf, 0);
+}
+
+int do_http_progress(const int state)
+{
+	/* toggle LED's here */
+	switch(state) {
+		case HTTP_PROGRESS_START:
+		puts("http start\n");
+		break;
+		case HTTP_PROGRESS_TIMEOUT:
+		puts(".");
+		break;
+		case HTTP_PROGRESS_UPLOAD_READY:
+		puts("http upload ready\n");
+		break;
+		case HTTP_PROGRESS_UGRADE_READY:
+		puts("http ugrade ready\n");
+		break;
+		case HTTP_PROGRESS_UGRADE_FAILED:
+		puts("http ugrade failed\n");
+		break;
+	}
+	return 0;
+}
+
+unsigned long do_http_tmp_address(void)
+{
+	char *s = getenv ("ram_addr");
+	if (s) {
+		ulong tmp = simple_strtoul (s, NULL, 16);
+		return tmp;
+	}
+	return 0 /*0x80a00000*/;
+}
+
+#endif

package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h

@@ -0,0 +1,51 @@
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
+
+#define MC_DC0_VALUE	0x1B1B
+#define MC_DC1_VALUE	0x0
+#define MC_DC2_VALUE	0x0
+#define MC_DC3_VALUE	0x0
+#define MC_DC4_VALUE	0x0
+#define MC_DC5_VALUE	0x200
+#define MC_DC6_VALUE	0x306
+#define MC_DC7_VALUE	0x303
+#define MC_DC8_VALUE	0x102
+#define MC_DC9_VALUE	0x70a
+#define MC_DC10_VALUE	0x203
+#define MC_DC11_VALUE	0xc02
+#define MC_DC12_VALUE	0x1C8
+#define MC_DC13_VALUE	0x1
+#define MC_DC14_VALUE	0x0
+#define MC_DC15_VALUE	0x139  /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE	0x2200
+#define MC_DC17_VALUE	0xd
+#define MC_DC18_VALUE	0x301
+#define MC_DC19_VALUE	0x200
+#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE	0x1800
+#define MC_DC22_VALUE	0x1818
+#define MC_DC23_VALUE	0x0
+#define MC_DC24_VALUE	0x59   /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE	0x0
+#define MC_DC26_VALUE	0x0
+#define MC_DC27_VALUE	0x0
+#define MC_DC28_VALUE	0x514
+#define MC_DC29_VALUE	0x2d93
+#define MC_DC30_VALUE	0x8235
+#define MC_DC31_VALUE	0x0
+#define MC_DC32_VALUE	0x0
+#define MC_DC33_VALUE	0x0
+#define MC_DC34_VALUE	0x0
+#define MC_DC35_VALUE	0x0
+#define MC_DC36_VALUE	0x0
+#define MC_DC37_VALUE	0x0
+#define MC_DC38_VALUE	0x0
+#define MC_DC39_VALUE	0x0
+#define MC_DC40_VALUE	0x0
+#define MC_DC41_VALUE	0x0
+#define MC_DC42_VALUE	0x0
+#define MC_DC43_VALUE	0x0
+#define MC_DC44_VALUE	0x0
+#define MC_DC45_VALUE	0x600
+//#define MC_DC45_VALUE	0x400
+#define MC_DC46_VALUE	0x0

package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr166_settings.h

@@ -0,0 +1,51 @@
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
+
+#define MC_DC0_VALUE	0x1B1B
+#define MC_DC1_VALUE	0x0
+#define MC_DC2_VALUE	0x0
+#define MC_DC3_VALUE	0x0
+#define MC_DC4_VALUE	0x0
+#define MC_DC5_VALUE	0x200
+#define MC_DC6_VALUE	0x306
+#define MC_DC7_VALUE	0x303
+#define MC_DC8_VALUE	0x102
+#define MC_DC9_VALUE	0x70a
+#define MC_DC10_VALUE	0x203
+#define MC_DC11_VALUE	0xc02
+#define MC_DC12_VALUE	0x1C8
+#define MC_DC13_VALUE	0x1
+#define MC_DC14_VALUE	0x0
+#define MC_DC15_VALUE	0x13f  /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE	0x2200
+#define MC_DC17_VALUE	0xd
+#define MC_DC18_VALUE	0x301
+#define MC_DC19_VALUE	0x200
+#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE	0x1600
+#define MC_DC22_VALUE	0x1616
+#define MC_DC23_VALUE	0x0
+#define MC_DC24_VALUE	0x5d   /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE	0x0
+#define MC_DC26_VALUE	0x0
+#define MC_DC27_VALUE	0x0
+#define MC_DC28_VALUE	0x514
+#define MC_DC29_VALUE	0x2d93
+#define MC_DC30_VALUE	0x8235
+#define MC_DC31_VALUE	0x0
+#define MC_DC32_VALUE	0x0
+#define MC_DC33_VALUE	0x0
+#define MC_DC34_VALUE	0x0
+#define MC_DC35_VALUE	0x0
+#define MC_DC36_VALUE	0x0
+#define MC_DC37_VALUE	0x0
+#define MC_DC38_VALUE	0x0
+#define MC_DC39_VALUE	0x0
+#define MC_DC40_VALUE	0x0
+#define MC_DC41_VALUE	0x0
+#define MC_DC42_VALUE	0x0
+#define MC_DC43_VALUE	0x0
+#define MC_DC44_VALUE	0x0
+#define MC_DC45_VALUE	0x600
+//#define MC_DC45_VALUE	0x400
+#define MC_DC46_VALUE	0x0

package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h

@@ -0,0 +1,51 @@
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
+
+#define MC_DC0_VALUE	0x1B1B
+#define MC_DC1_VALUE	0x0
+#define MC_DC2_VALUE	0x0
+#define MC_DC3_VALUE	0x0
+#define MC_DC4_VALUE	0x0
+#define MC_DC5_VALUE	0x200
+#define MC_DC6_VALUE	0x306
+#define MC_DC7_VALUE	0x303
+#define MC_DC8_VALUE	0x102
+#define MC_DC9_VALUE	0x80B
+#define MC_DC10_VALUE	0x203
+#define MC_DC11_VALUE	0xD02
+#define MC_DC12_VALUE	0x1C8
+#define MC_DC13_VALUE	0x1
+#define MC_DC14_VALUE	0x0
+#define MC_DC15_VALUE	0x144  /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE	0xC800
+#define MC_DC17_VALUE	0xF
+#define MC_DC18_VALUE	0x301
+#define MC_DC19_VALUE	0x200
+#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE	0x1200
+#define MC_DC22_VALUE	0x1212
+#define MC_DC23_VALUE	0x0
+#define MC_DC24_VALUE	0x66   /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE	0x0
+#define MC_DC26_VALUE	0x0
+#define MC_DC27_VALUE	0x0
+#define MC_DC28_VALUE	0x5FB
+#define MC_DC29_VALUE	0x35DF
+#define MC_DC30_VALUE	0x99E9
+#define MC_DC31_VALUE	0x0
+#define MC_DC32_VALUE	0x0
+#define MC_DC33_VALUE	0x0
+#define MC_DC34_VALUE	0x0
+#define MC_DC35_VALUE	0x0
+#define MC_DC36_VALUE	0x0
+#define MC_DC37_VALUE	0x0
+#define MC_DC38_VALUE	0x0
+#define MC_DC39_VALUE	0x0
+#define MC_DC40_VALUE	0x0
+#define MC_DC41_VALUE	0x0
+#define MC_DC42_VALUE	0x0
+#define MC_DC43_VALUE	0x0
+#define MC_DC44_VALUE	0x0
+#define MC_DC45_VALUE	0x600
+//#define MC_DC45_VALUE	0x400
+#define MC_DC46_VALUE	0x0

package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h

@@ -0,0 +1,51 @@
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */
+
+#define MC_DC0_VALUE	0x1B1B
+#define MC_DC1_VALUE	0x0
+#define MC_DC2_VALUE	0x0
+#define MC_DC3_VALUE	0x0
+#define MC_DC4_VALUE	0x0
+#define MC_DC5_VALUE	0x200
+#define MC_DC6_VALUE	0x306
+#define MC_DC7_VALUE	0x403
+#define MC_DC8_VALUE	0x102
+#define MC_DC9_VALUE	0x90c
+#define MC_DC10_VALUE	0x203
+#define MC_DC11_VALUE	0xf02
+#define MC_DC12_VALUE	0x2c8
+#define MC_DC13_VALUE	0x1
+#define MC_DC14_VALUE	0x0
+#define MC_DC15_VALUE	0x12f  /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE	0xc800
+#define MC_DC17_VALUE	0xf
+#define MC_DC18_VALUE	0x301
+#define MC_DC19_VALUE	0x200
+#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE	0x1500
+#define MC_DC22_VALUE	0x1515
+#define MC_DC23_VALUE	0x0
+#define MC_DC24_VALUE	0x57   /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE	0x0
+#define MC_DC26_VALUE	0x0
+#define MC_DC27_VALUE	0x0
+#define MC_DC28_VALUE	0x6b8
+#define MC_DC29_VALUE	0x3c84
+#define MC_DC30_VALUE	0xace5
+#define MC_DC31_VALUE	0x0
+#define MC_DC32_VALUE	0x0
+#define MC_DC33_VALUE	0x0
+#define MC_DC34_VALUE	0x0
+#define MC_DC35_VALUE	0x0
+#define MC_DC36_VALUE	0x0
+#define MC_DC37_VALUE	0x0
+#define MC_DC38_VALUE	0x0
+#define MC_DC39_VALUE	0x0
+#define MC_DC40_VALUE	0x0
+#define MC_DC41_VALUE	0x0
+#define MC_DC42_VALUE	0x0
+#define MC_DC43_VALUE	0x0
+#define MC_DC44_VALUE	0x0
+#define MC_DC45_VALUE	0x600
+//#define MC_DC45_VALUE	0x400
+#define MC_DC46_VALUE	0x0

package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h

@@ -0,0 +1,51 @@
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */
+
+#define MC_DC0_VALUE	0x1B1B
+#define MC_DC1_VALUE	0x0
+#define MC_DC2_VALUE	0x0
+#define MC_DC3_VALUE	0x0
+#define MC_DC4_VALUE	0x0
+#define MC_DC5_VALUE	0x200
+#define MC_DC6_VALUE	0x306
+#define MC_DC7_VALUE	0x403
+#define MC_DC8_VALUE	0x103
+#define MC_DC9_VALUE	0xb0e
+#define MC_DC10_VALUE	0x204
+#define MC_DC11_VALUE	0x1102
+#define MC_DC12_VALUE	0x2c8
+#define MC_DC13_VALUE	0x1
+#define MC_DC14_VALUE	0x0
+#define MC_DC15_VALUE	0x155  /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE	0xc800
+#define MC_DC17_VALUE	0x13
+#define MC_DC18_VALUE	0x401
+#define MC_DC19_VALUE	0x200
+#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE	0xc00
+#define MC_DC22_VALUE	0xc0c
+#define MC_DC23_VALUE	0x0
+#define MC_DC24_VALUE	0x74   /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE	0x0
+#define MC_DC26_VALUE	0x0
+#define MC_DC27_VALUE	0x0
+#define MC_DC28_VALUE	0x798
+#define MC_DC29_VALUE	0x445d
+#define MC_DC30_VALUE	0xc351
+#define MC_DC31_VALUE	0x0
+#define MC_DC32_VALUE	0x0
+#define MC_DC33_VALUE	0x0
+#define MC_DC34_VALUE	0x0
+#define MC_DC35_VALUE	0x0
+#define MC_DC36_VALUE	0x0
+#define MC_DC37_VALUE	0x0
+#define MC_DC38_VALUE	0x0
+#define MC_DC39_VALUE	0x0
+#define MC_DC40_VALUE	0x0
+#define MC_DC41_VALUE	0x0
+#define MC_DC42_VALUE	0x0
+#define MC_DC43_VALUE	0x0
+#define MC_DC44_VALUE	0x0
+#define MC_DC45_VALUE	0x600
+//#define MC_DC45_VALUE	0x400
+#define MC_DC46_VALUE	0x0

package/uboot-lantiq/files/board/infineon/easy50812/config.mk

@@ -0,0 +1,60 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Danube board with MIPS 24Kc CPU core
+#
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifdef CONFIG_LZMA_BOOTSTRAP
+
+ifdef BUILD_BOOTSTRAP
+
+$(info BUILD_BOOTSTRAP )
+#TEXT_BASE = 0xB0000000
+TEXT_BASE = 0x80010000
+
+else # BUILD_BOOTSTRAP
+
+ifndef TEXT_BASE
+$(info redefine TEXT_BASE = 0x80040000 )
+TEXT_BASE = 0x80040000
+endif
+
+endif # BUILD_BOOTSTRAP
+
+else
+
+ifdef BUILD_BOOTSTRAP
+$(error BUILD_BOOTSTRAP but not enabled in config)
+endif
+
+ifndef TEXT_BASE
+## Standard: boot from ebu
+$(info redefine TEXT_BASE = 0xB0000000 )
+TEXT_BASE = 0xB0000000
+## For testing: boot from RAM
+# TEXT_BASE = 0x80100000
+endif
+
+endif # CONFIG_LZMA_BOOTSTRAP

package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_init.S

@@ -0,0 +1,543 @@
+/*
+ *  Memory sub-system initialization code for AR9 board.
+ *
+ *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
+ *  Copyright (c) 2005	Andre Messerschmidt  Infineon
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* History:
+      peng liu May 25, 2006, for PLL setting after reset, 05252006
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+#if defined(CONFIG_USE_DDR_RAM)
+
+#if defined(CONFIG_CPU_111M_RAM_111M) || defined(CONFIG_CPU_333M_RAM_111M)
+#	include "ar9_ddr111_settings.h"  
+#elif defined(CONFIG_CPU_166M_RAM_166M) || defined(CONFIG_CPU_333M_RAM_166M) || defined(CONFIG_CPU_500M_RAM_166M) 
+#	include "ar9_ddr166_settings.h"
+#elif defined(CONFIG_CPU_442M_RAM_147M)
+#	include "ar9_ddr166_settings.h"
+#elif defined(CONFIG_CPU_393M_RAM_196M)
+#	ifdef CONFIG_ETRON_RAM
+#		include "etron_ddr196_settings.h"
+#	else
+#		include "ar9_ddr196_settings.h"
+#	endif
+#elif defined(CONFIG_CPU_442M_RAM_221M)
+#	include "ar9_ddr221_settings.h"
+#elif defined(CONFIG_CPU_500M_RAM_250M)
+#	include "ar9_ddr250_settings.h"
+#else
+#	warning "missing definition for ddr_settings.h, use default!"
+#	include "ar9_ddr_settings.h"
+#endif
+#endif /* CONFIG_USE_DDR_RAM */
+
+#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
+#error "missing include of ddr_settings.h"
+#endif
+
+#define EBU_MODUL_BASE		0xBE105300
+#define EBU_CLC(value)		0x0000(value)
+#define EBU_CON(value)		0x0010(value)
+#define EBU_ADDSEL0(value)	0x0020(value)
+#define EBU_ADDSEL1(value)	0x0024(value)
+#define EBU_ADDSEL2(value)	0x0028(value)
+#define EBU_ADDSEL3(value)	0x002C(value)
+#define EBU_BUSCON0(value)	0x0060(value)
+#define EBU_BUSCON1(value)	0x0064(value)
+#define EBU_BUSCON2(value)	0x0068(value)
+#define EBU_BUSCON3(value)	0x006C(value)
+
+#define MC_MODUL_BASE		0xBF800000
+#define MC_ERRCAUSE(value)	0x0010(value)
+#define MC_ERRADDR(value)	0x0020(value)
+#define MC_CON(value)		0x0060(value)
+
+#define MC_SRAM_ENABLE		0x00000004
+#define MC_SDRAM_ENABLE		0x00000002
+#define MC_DDRRAM_ENABLE	0x00000001
+
+#define MC_SDR_MODUL_BASE	0xBF800200
+#define MC_IOGP(value)		0x0000(value)
+#define MC_CTRLENA(value)	0x0010(value)
+#define MC_MRSCODE(value)	0x0020(value)
+#define MC_CFGDW(value)		0x0030(value)
+#define MC_CFGPB0(value)	0x0040(value)
+#define MC_LATENCY(value)	0x0080(value)
+#define MC_TREFRESH(value)	0x0090(value)
+#define MC_SELFRFSH(value)	0x00A0(value)
+
+#define MC_DDR_MODUL_BASE	0xBF801000
+#define MC_DC00(value)		0x0000(value)
+#define MC_DC01(value)		0x0010(value)
+#define MC_DC02(value)		0x0020(value)
+#define MC_DC03(value)		0x0030(value)
+#define MC_DC04(value)		0x0040(value)
+#define MC_DC05(value)		0x0050(value)
+#define MC_DC06(value)		0x0060(value)
+#define MC_DC07(value)		0x0070(value)
+#define MC_DC08(value)		0x0080(value)
+#define MC_DC09(value)		0x0090(value)
+#define MC_DC10(value)		0x00A0(value)
+#define MC_DC11(value)		0x00B0(value)
+#define MC_DC12(value)		0x00C0(value)
+#define MC_DC13(value)		0x00D0(value)
+#define MC_DC14(value)		0x00E0(value)
+#define MC_DC15(value)		0x00F0(value)
+#define MC_DC16(value)		0x0100(value)
+#define MC_DC17(value)		0x0110(value)
+#define MC_DC18(value)		0x0120(value)
+#define MC_DC19(value)		0x0130(value)
+#define MC_DC20(value)		0x0140(value)
+#define MC_DC21(value)		0x0150(value)
+#define MC_DC22(value)		0x0160(value)
+#define MC_DC23(value)		0x0170(value)
+#define MC_DC24(value)		0x0180(value)
+#define MC_DC25(value)		0x0190(value)
+#define MC_DC26(value)		0x01A0(value)
+#define MC_DC27(value)		0x01B0(value)
+#define MC_DC28(value)		0x01C0(value)
+#define MC_DC29(value)		0x01D0(value)
+#define MC_DC30(value)		0x01E0(value)
+#define MC_DC31(value)		0x01F0(value)
+#define MC_DC32(value)		0x0200(value)
+#define MC_DC33(value)		0x0210(value)
+#define MC_DC34(value)		0x0220(value)
+#define MC_DC35(value)		0x0230(value)
+#define MC_DC36(value)		0x0240(value)
+#define MC_DC37(value)		0x0250(value)
+#define MC_DC38(value)		0x0260(value)
+#define MC_DC39(value)		0x0270(value)
+#define MC_DC40(value)		0x0280(value)
+#define MC_DC41(value)		0x0290(value)
+#define MC_DC42(value)		0x02A0(value)
+#define MC_DC43(value)		0x02B0(value)
+#define MC_DC44(value)		0x02C0(value)
+#define MC_DC45(value)		0x02D0(value)
+#define MC_DC46(value)		0x02E0(value)
+
+#define RCU_OFFSET  0xBF203000
+#define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
+#define RCU_STS          (RCU_OFFSET + 0x0014)
+
+#define CGU_OFFSET  0xBF103000
+#define  PLL0_CFG     (CGU_OFFSET + 0x0004)
+#define  PLL1_CFG     (CGU_OFFSET + 0x0008)
+#define  PLL2_CFG     (CGU_OFFSET + 0x000C)
+#define  CGU_SYS      (CGU_OFFSET + 0x0010)
+#define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
+#define  IF_CLK       (CGU_OFFSET + 0x0018)
+#define  CGU_SMD      (CGU_OFFSET + 0x0020)
+#define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
+#define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
+#define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
+#define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
+#define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
+#define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
+#define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
+
+#define  pll1_36MHz_CONFIG 0x9800f25f
+
+	.set	noreorder
+
+
+/*
+ * void ebu_init(void)
+ */
+	.globl	ebu_init
+	.ent	ebu_init
+ebu_init:
+
+#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
+	defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
+	defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
+	defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
+
+	li	t1, EBU_MODUL_BASE
+#if defined(CONFIG_EBU_ADDSEL0)
+	li	t2, CONFIG_EBU_ADDSEL0
+	sw	t2, EBU_ADDSEL0(t1)
+#endif
+#if defined(CONFIG_EBU_ADDSEL1)
+	li	t2, CONFIG_EBU_ADDSEL1
+	sw	t2, EBU_ADDSEL1(t1)
+#endif
+#if defined(CONFIG_EBU_ADDSEL2)
+	li	t2, CONFIG_EBU_ADDSEL2
+	sw	t2, EBU_ADDSEL2(t1)
+#endif
+#if defined(CONFIG_EBU_ADDSEL3)
+	li	t2, CONFIG_EBU_ADDSEL3
+	sw	t2, EBU_ADDSEL3(t1)
+#endif
+
+#if defined(CONFIG_EBU_BUSCON0)
+	li	t2, CONFIG_EBU_BUSCON0
+	sw	t2, EBU_BUSCON0(t1)
+#endif
+#if defined(CONFIG_EBU_BUSCON1)
+	li	t2, CONFIG_EBU_BUSCON1
+	sw	t2, EBU_BUSCON1(t1)
+#endif
+#if defined(CONFIG_EBU_BUSCON2)
+	li	t2, CONFIG_EBU_BUSCON2
+	sw	t2, EBU_BUSCON2(t1)
+#endif
+#if defined(CONFIG_EBU_BUSCON3)
+	li	t2, CONFIG_EBU_BUSCON3
+	sw	t2, EBU_BUSCON3(t1)
+#endif
+
+#endif
+
+	j	ra
+	nop
+
+	.end	ebu_init
+
+
+/*
+ * void cgu_init(long)
+ *
+ * a0 has the clock value
+ */
+	.globl	cgu_init
+	.ent	cgu_init
+cgu_init:
+        li  t2, CGU_SYS
+        lw  t2,0(t2)
+        beq t2,a0,freq_up2date
+        nop
+        li  t1, CGU_SYS
+        sw	a0,0(t1)
+
+#if defined(CONFIG_CPU_333M_RAM_166M) && defined(CONFIG_USE_PLL1)
+        li  t1, PLL1_CFG
+        li  a1, pll1_36MHz_CONFIG
+        sw  a1, 0(t1)
+#endif
+
+#if defined(CONFIG_CLASS_II_DDR_PAD) 
+        li  t1, CGU_SMD
+        li  a1, 0x200000
+        sw  a1, 0(t1)      // Turn on DDR PAD Class II to INC drive.
+#endif
+
+        li  t1, RCU_RST_REQ
+        li  t2, 0x40000008
+        sw	t2,0(t1)
+        b   wait_reset
+        nop
+
+wait_reset:
+        b   wait_reset
+        nop
+
+freq_up2date:
+        j ra
+        nop
+	.end	cgu_init
+
+
+#ifndef CONFIG_USE_DDR_RAM
+/*
+ * void sdram_init(long)
+ *
+ * a0 has the clock value
+ */
+	.globl	sdram_init
+	.ent	sdram_init
+sdram_init:
+
+	/* SDRAM Initialization
+	 */
+	li	t1, MC_MODUL_BASE
+
+	/* Clear Error log registers */
+	sw	zero, MC_ERRCAUSE(t1)
+	sw	zero, MC_ERRADDR(t1)
+
+	/* Enable SDRAM module in memory controller */
+	li	t3, MC_SDRAM_ENABLE
+	lw	t2, MC_CON(t1)
+	or	t3, t2, t3
+	sw	t3, MC_CON(t1)
+
+	li	t1, MC_SDR_MODUL_BASE
+
+	/* disable the controller */
+	li	t2, 0
+	sw	t2, MC_CTRLENA(t1)
+
+	li	t2, 0x822
+	sw	t2, MC_IOGP(t1)
+
+	li	t2, 0x2
+	sw	t2, MC_CFGDW(t1)
+
+	/* Set CAS Latency */
+	li	t2, 0x00000020
+	sw	t2, MC_MRSCODE(t1)
+
+	/* Set CS0 to SDRAM parameters */
+	li	t2, 0x000014d8
+	sw	t2, MC_CFGPB0(t1)
+
+	/* Set SDRAM latency parameters */
+	li  	t2, 0x00036325;   /* BC PC100 */
+	sw	t2, MC_LATENCY(t1)
+
+	/* Set SDRAM refresh rate */
+	li	t2, 0x00000C30
+	sw	t2, MC_TREFRESH(t1)
+
+	/* Clear Power-down registers */
+	sw	zero, MC_SELFRFSH(t1)
+
+	/* Finally enable the controller */
+	li	t2, 1
+	sw	t2, MC_CTRLENA(t1)
+
+	j	ra
+	nop
+
+	.end	sdram_init
+
+#endif /* !CONFIG_USE_DDR_RAM */
+
+#ifdef CONFIG_USE_DDR_RAM
+/*
+ * void ddrram_init(long)
+ *
+ * a0 has the clock value
+ */
+	.globl	ddrram_init
+	.ent	ddrram_init
+ddrram_init:
+
+	/* DDR-DRAM Initialization
+	 */
+	li	t1, MC_MODUL_BASE
+
+	/* Clear Error log registers */
+	sw	zero, MC_ERRCAUSE(t1)
+	sw	zero, MC_ERRADDR(t1)
+
+	/* Enable DDR module in memory controller */
+	li	t3, MC_DDRRAM_ENABLE
+	lw	t2, MC_CON(t1)
+	or	t3, t2, t3
+	sw	t3, MC_CON(t1)
+
+	li	t1, MC_DDR_MODUL_BASE
+
+	/* Write configuration to DDR controller registers */
+	li	t2, MC_DC0_VALUE
+	sw	t2, MC_DC00(t1)
+
+	li	t2, MC_DC1_VALUE
+	sw	t2, MC_DC01(t1)
+
+	li	t2, MC_DC2_VALUE
+	sw	t2, MC_DC02(t1)
+
+	li	t2, MC_DC3_VALUE
+	sw	t2, MC_DC03(t1)
+
+	li	t2, MC_DC4_VALUE
+	sw	t2, MC_DC04(t1)
+
+	li	t2, MC_DC5_VALUE
+	sw	t2, MC_DC05(t1)
+
+	li	t2, MC_DC6_VALUE
+	sw	t2, MC_DC06(t1)
+
+	li	t2, MC_DC7_VALUE
+	sw	t2, MC_DC07(t1)
+
+	li	t2, MC_DC8_VALUE
+	sw	t2, MC_DC08(t1)
+
+	li	t2, MC_DC9_VALUE
+	sw	t2, MC_DC09(t1)
+
+	li	t2, MC_DC10_VALUE
+	sw	t2, MC_DC10(t1)
+
+	li	t2, MC_DC11_VALUE
+	sw	t2, MC_DC11(t1)
+
+	li	t2, MC_DC12_VALUE
+	sw	t2, MC_DC12(t1)
+
+	li	t2, MC_DC13_VALUE
+	sw	t2, MC_DC13(t1)
+
+	li	t2, MC_DC14_VALUE
+	sw	t2, MC_DC14(t1)
+
+	li	t2, MC_DC15_VALUE
+	sw	t2, MC_DC15(t1)
+
+	li	t2, MC_DC16_VALUE
+	sw	t2, MC_DC16(t1)
+
+	li	t2, MC_DC17_VALUE
+	sw	t2, MC_DC17(t1)
+
+	li	t2, MC_DC18_VALUE
+	sw	t2, MC_DC18(t1)
+
+	li	t2, MC_DC19_VALUE
+	sw	t2, MC_DC19(t1)
+
+	li	t2, MC_DC20_VALUE
+	sw	t2, MC_DC20(t1)
+
+	li	t2, MC_DC21_VALUE
+	sw	t2, MC_DC21(t1)
+
+	li	t2, MC_DC22_VALUE
+	sw	t2, MC_DC22(t1)
+
+	li	t2, MC_DC23_VALUE
+	sw	t2, MC_DC23(t1)
+
+	li	t2, MC_DC24_VALUE
+	sw	t2, MC_DC24(t1)
+
+	li	t2, MC_DC25_VALUE
+	sw	t2, MC_DC25(t1)
+
+	li	t2, MC_DC26_VALUE
+	sw	t2, MC_DC26(t1)
+
+	li	t2, MC_DC27_VALUE
+	sw	t2, MC_DC27(t1)
+
+	li	t2, MC_DC28_VALUE
+	sw	t2, MC_DC28(t1)
+
+	li	t2, MC_DC29_VALUE
+	sw	t2, MC_DC29(t1)
+
+	li	t2, MC_DC30_VALUE
+	sw	t2, MC_DC30(t1)
+
+	li	t2, MC_DC31_VALUE
+	sw	t2, MC_DC31(t1)
+
+	li	t2, MC_DC32_VALUE
+	sw	t2, MC_DC32(t1)
+
+	li	t2, MC_DC33_VALUE
+	sw	t2, MC_DC33(t1)
+
+	li	t2, MC_DC34_VALUE
+	sw	t2, MC_DC34(t1)
+
+	li	t2, MC_DC35_VALUE
+	sw	t2, MC_DC35(t1)
+
+	li	t2, MC_DC36_VALUE
+	sw	t2, MC_DC36(t1)
+
+	li	t2, MC_DC37_VALUE
+	sw	t2, MC_DC37(t1)
+
+	li	t2, MC_DC38_VALUE
+	sw	t2, MC_DC38(t1)
+
+	li	t2, MC_DC39_VALUE
+	sw	t2, MC_DC39(t1)
+
+	li	t2, MC_DC40_VALUE
+	sw	t2, MC_DC40(t1)
+
+	li	t2, MC_DC41_VALUE
+	sw	t2, MC_DC41(t1)
+
+	li	t2, MC_DC42_VALUE
+	sw	t2, MC_DC42(t1)
+
+	li	t2, MC_DC43_VALUE
+	sw	t2, MC_DC43(t1)
+
+	li	t2, MC_DC44_VALUE
+	sw	t2, MC_DC44(t1)
+
+	li	t2, MC_DC45_VALUE
+	sw	t2, MC_DC45(t1)
+
+	li	t2, MC_DC46_VALUE
+	sw	t2, MC_DC46(t1)
+
+	li	t2, 0x00000100
+	sw	t2, MC_DC03(t1)
+
+	j	ra
+	nop
+
+	.end	ddrram_init
+#endif /* CONFIG_USE_DDR_RAM */
+
+	.globl	lowlevel_init
+	.ent	lowlevel_init
+lowlevel_init:
+	/* EBU, CGU and SDRAM/DDR-RAM Initialization.
+	 */
+	move	t0, ra
+	/* We rely on the fact that non of the following ..._init() functions
+	 * modify t0
+	 */
+#if defined(CONFIG_SYS_EBU_BOOT)
+/*
+	using PPL1 value
+*/
+	li  a0,0x90
+	bal	cgu_init
+	nop
+#endif /* CONFIG_SYS_EBU_BOOT */
+
+	bal	ebu_init
+	nop
+
+#ifdef CONFIG_SYS_EBU_BOOT
+#ifndef CONFIG_SYS_RAMBOOT
+#ifdef CONFIG_USE_DDR_RAM
+	bal	ddrram_init
+	nop
+#else
+	bal	sdram_init
+	nop
+#endif
+#endif /* CONFIG_SYS_RAMBOOT */
+#endif /* CONFIG_SYS_EBU_BOOT */
+
+	move	ra, t0
+	j	ra
+	nop
+
+	.end	lowlevel_init

package/uboot-lantiq/files/board/infineon/easy50812/pmuenable.S

@@ -0,0 +1,48 @@
+/*
+ *  Power Management unit initialization code for AMAZON development board.
+ *
+ *  Copyright (c) 2003	Ou Ke, Infineon.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+#define PMU_PWDCR 		0xBF10201C
+#define PMU_SR			0xBF102020
+
+	.globl	pmuenable
+
+pmuenable:
+	li      t0, PMU_PWDCR
+	li      t1, 0x2		/* enable everything */
+	sw      t1, 0(t0)
+#if 0
+1:
+	li	t0, PMU_SR
+	lw      t2, 0(t0)
+	bne     t1, t2, 1b
+	nop
+#endif
+	j	ra
+	nop
+
+

package/uboot-lantiq/files/board/infineon/easy50812/u-boot.lds

@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = .;
+	_gp = ALIGN(16) + 0x7ff0;
+
+	.got : {
+	  __got_start = .;
+	  *(.got)
+	  __got_end = .;
+	}
+
+	.sdata  : { *(.sdata) }
+
+	.u_boot_cmd : {
+	  __u_boot_cmd_start = .;
+	  *(.u_boot_cmd)
+	  __u_boot_cmd_end = .;
+	}
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss (NOLOAD)  : { *(.sbss) }
+	.bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
+	uboot_end = .;
+}

package/uboot-lantiq/files/cpu/mips/ar9/Makefile

@@ -0,0 +1,46 @@
+#########################################################################
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	= clock.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

package/uboot-lantiq/files/cpu/mips/ar9/clock.c

@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ar9.h>
+
+ulong ifx_get_ddr_hz(void)
+{
+	switch((*AR9_CGU_SYS) & 0x05) {
+		case 0x01: 
+		case 0x05: 
+		return CLOCK_111M;
+	
+		case 0x00: 
+		case 0x04: 
+		return CLOCK_166M;
+	}
+
+	return 0;
+}
+
+ulong ifx_get_cpuclk(void)
+{
+	switch((*AR9_CGU_SYS) & 0x05) {
+		case 0x00: 
+		case 0x01: 
+		return CLOCK_333M;
+
+		case 0x04: 
+		return CLOCK_166M;
+
+		case 0x05: 
+		return CLOCK_111M;
+	}
+
+	return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+	unsigned int ddr_clock=ifx_get_ddr_hz();
+	if((*AR9_CGU_SYS) & 0x40){
+		return ddr_clock/2;
+	} else {
+		return ddr_clock;
+	}
+}

package/uboot-lantiq/files/cpu/mips/ar9/ifx_cache.S

@@ -0,0 +1,60 @@
+
+#define IFX_CACHE_EXTRA_INVALID_TAG						\
+	mtc0	zero, CP0_TAGLO, 1;						\
+	mtc0	zero, CP0_TAGLO, 2;						\
+	mtc0	zero, CP0_TAGLO, 3;						\
+	mtc0	zero, CP0_TAGLO, 4;
+
+#define IFX_CACHE_EXTRA_OPERATION						\
+	/* set WST bit */							\
+	mfc0	a0, CP0_ECC;							\
+	li	a1, ECCF_WST;							\
+	or	a0, a1;								\
+	mtc0	a0, CP0_ECC;							\
+										\
+	li	a0, K0BASE;							\
+	move	a2, t2;		/* icacheSize */				\
+	move	a3, t4;		/* icacheLineSize */				\
+	move	a1, a2;								\
+	icacheop(a0,a1,a2,a3,(Index_Store_Tag_I));				\
+										\
+	/* clear WST bit */							\
+	mfc0	a0, CP0_ECC;							\
+	li	a1, ~ECCF_WST;							\
+	and	a0, a1;								\
+	mtc0	a0, CP0_ECC;							\
+										\
+	/* 1: initialise dcache tags. */					\
+										\
+	/* cache line size */							\
+	li	a2, CFG_CACHELINE_SIZE;						\
+	/* kseg0 mem address */							\
+	li	a1, 0;								\
+	li	a3, CFG_CACHE_SETS * CFG_CACHE_WAYS;				\
+1:										\
+	/* store tag (invalid, not locked) */					\
+	cache 0x8, 0(a1);							\
+	cache 0x9, 0(a1);							\
+										\
+	add	a3, -1;								\
+	bne	a3, zero, 1b;							\
+	add	a1, a2;								\
+										\
+	/* set WST bit */							\
+	mfc0	a0, CP0_ECC;							\
+	li	a1, ECCF_WST;							\
+	or	a0, a1;								\
+	mtc0	a0, CP0_ECC;							\
+										\
+	li	a0, K0BASE;							\
+	move	a2, t3;		/* dcacheSize */				\
+	move	a3, t5;		/* dcacheLineSize */				\
+	move	a1, a2;								\
+	icacheop(a0,a1,a2,a3,(Index_Store_Tag_D));				\
+										\
+	/* clear WST bit */							\
+	mfc0	a0, CP0_ECC;							\
+	li	a1, ~ECCF_WST;							\
+	and	a0, a1;								\
+	mtc0	a0, CP0_ECC;
+

package/uboot-lantiq/files/drivers/net/ifx_etop.c

@@ -36,11 +36,17 @@
 #include <asm/types.h>
 #include <asm/io.h>
 #include <asm/addrspace.h>
+#include <config.h>
 
 #include "ifx_etop.h"
 
+#if defined(CONFIG_AR9)
+#define TX_CHAN_NO   1
+#define RX_CHAN_NO   0
+#else
 #define TX_CHAN_NO   7
 #define RX_CHAN_NO   6
+#endif
 
 #define NUM_RX_DESC	PKTBUFSRX
 #define NUM_TX_DESC	8
@@ -245,7 +251,19 @@ static void lq_eth_halt(struct eth_device *dev)
 	}
 }
 
-static int lq_eth_send(struct eth_device *dev, volatile void *packet,int length)
+#ifdef DEBUG
+static void lq_dump(const u8 *data, const u32 length)
+{
+	u32 i;
+	debug("\n");
+	for(i=0;i<length;i++) {
+		debug("%02x ", data[i]);
+	}
+	debug("\n");
+}
+#endif
+
+static int lq_eth_send(struct eth_device *dev, volatile void *packet, int length)
 {
 	int i;
 	int res = -1;
@@ -273,12 +291,17 @@ static int lq_eth_send(struct eth_device *dev, volatile void *packet,int length)
 		tx_desc->status.field.DataLen = (u32)length;
 
 	flush_cache((u32)packet, tx_desc->status.field.DataLen);
+	asm("SYNC");
 	tx_desc->status.field.OWN=1;
 
 	res=length;
 	tx_num++;
 	if (tx_num==NUM_TX_DESC) tx_num=0;
 
+#ifdef DEBUG
+	lq_dump(tx_desc->DataPtr, tx_desc->status.field.DataLen);
+#endif
+
 	dma_writel(dma_cs, TX_CHAN_NO);
 	if (!(dma_readl(dma_cctrl) & 1)) {
 		dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1);
@@ -298,6 +321,10 @@ static int lq_eth_recv(struct eth_device *dev)
 	if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1)) {
 		return 0;
 	}
+	debug("rx");
+#ifdef DEBUG
+	lq_dump(rx_desc->DataPtr, rx_desc->status.field.DataLen);
+#endif
 	length = rx_desc->status.field.DataLen;
 	if (length > 4) {
 		invalidate_dcache_range((u32)CKSEG0ADDR(rx_desc->DataPtr), (u32) CKSEG0ADDR(rx_desc->DataPtr) + length);

package/uboot-lantiq/files/include/asm-mips/ar9.h

@@ -0,0 +1,424 @@
+/*
+ * (C) Copyright 2010
+ * Ralph Hempel
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+ 
+/***********************************************************************/
+/*  Module      :  PMU register address and bits                       */
+/***********************************************************************/
+#define AR9_PMU									(0xBF102000)
+/* PMU Power down Control Register */
+#define AR9_PMU_PWDCR							((volatile u32*)(AR9_PMU + 0x001C))
+/* PMU Status Register */
+#define AR9_PMU_SR								((volatile u32*)(AR9_PMU + 0x0020))
+/** DMA block */
+#define AR9_PMU_DMA								(1<<5)
+#define AR9_PMU_SDIO							(1<<16)
+#define AR9_PMU_USB0							(1<<6)
+#define AR9_PMU_USB0_P							(1<<0)
+#define AR9_PMU_SWITCH							(1<<28)
+
+
+/***********************************************************************/
+/*  Module      :  RCU register address and bits                       */
+/***********************************************************************/
+#define AR9_RCU_BASE_ADDR						(0xBF203000)
+#define AR9_RCU_RST_REQ							((volatile u32*)(AR9_RCU_BASE_ADDR + 0x0010))
+#define AR9_RCU_RST_STAT						((volatile u32*)(AR9_RCU_BASE_ADDR + 0x0014))
+#define AR9_RST_ALL								(1 << 30)
+
+/*** Reset Request Register Bits ***/
+#define AR9_RCU_RST_REQ_SRST					(1 << 30)
+#define AR9_RCU_RST_REQ_ARC_JTAG				(1 << 20)
+#define AR9_RCU_RST_REQ_PCI						(1 << 13)
+#define AR9_RCU_RST_REQ_AFE						(1 << 11)
+#define AR9_RCU_RST_REQ_SDIO					(1 << 19)
+#define AR9_RCU_RST_REQ_DMA						(1 << 9)
+#define AR9_RCU_RST_REQ_PPE						(1 << 8)
+#define AR9_RCU_RST_REQ_DFE						(1 << 7)
+
+/***********************************************************************/
+/*  Module      :  GPIO register address and bits                       */
+/***********************************************************************/
+#define AR9_GPIO								(0xBE100B00)
+/***Port 0 Data Output Register (0010H)***/
+#define AR9_GPIO_P0_OUT							((volatile u32 *)(AR9_GPIO+ 0x0010))
+/***Port 1 Data Output Register (0040H)***/
+#define AR9_GPIO_P1_OUT							((volatile u32 *)(AR9_GPIO+ 0x0040))
+/***Port 2 Data Output Register (0070H)***/
+#define AR9_GPIO_P2_OUT							((volatile u32 *)(AR9_GPIO+ 0x0070))
+/***Port 3 Data Output Register (00A0H)***/
+#define AR9_GPIO_P3_OUT							((volatile u32 *)(AR9_GPIO+ 0x00A0))
+/***Port 0 Data Input Register (0014H)***/
+#define AR9_GPIO_P0_IN							((volatile u32 *)(AR9_GPIO+ 0x0014))
+/***Port 1 Data Input Register (0044H)***/
+#define AR9_GPIO_P1_IN							((volatile u32 *)(AR9_GPIO+ 0x0044))
+/***Port 2 Data Input Register (0074H)***/
+#define AR9_GPIO_P2_IN							((volatile u32 *)(AR9_GPIO+ 0x0074))
+/***Port 3 Data Input Register (00A4H)***/
+#define AR9_GPIO_P3_IN							((volatile u32 *)(AR9_GPIO+ 0x00A4))
+/***Port 0 Direction Register (0018H)***/
+#define AR9_GPIO_P0_DIR							((volatile u32 *)(AR9_GPIO+ 0x0018))
+/***Port 1 Direction Register (0048H)***/
+#define AR9_GPIO_P1_DIR							((volatile u32 *)(AR9_GPIO+ 0x0048))
+/***Port 2 Direction Register (0078H)***/
+#define AR9_GPIO_P2_DIR							((volatile u32 *)(AR9_GPIO+ 0x0078))
+/***Port 3 Direction Register (0048H)***/
+#define AR9_GPIO_P3_DIR							((volatile u32 *)(AR9_GPIO+ 0x00A8))
+/***Port 0 Alternate Function Select Register 0 (001C H) ***/
+#define AR9_GPIO_P0_ALTSEL0						((volatile u32 *)(AR9_GPIO+ 0x001C))
+/***Port 1 Alternate Function Select Register 0 (004C H) ***/
+#define AR9_GPIO_P1_ALTSEL0						((volatile u32 *)(AR9_GPIO+ 0x004C))
+/***Port 2 Alternate Function Select Register 0 (007C H) ***/
+#define AR9_GPIO_P2_ALTSEL0						((volatile u32 *)(AR9_GPIO+ 0x007C))
+/***Port 3 Alternate Function Select Register 0 (00AC H) ***/
+#define AR9_GPIO_P3_ALTSEL0						((volatile u32 *)(AR9_GPIO+ 0x00AC))
+/***Port 0 Alternate Function Select Register 1 (0020 H) ***/
+#define AR9_GPIO_P0_ALTSEL1						((volatile u32 *)(AR9_GPIO+ 0x0020))
+/***Port 1 Alternate Function Select Register 0 (0050 H) ***/
+#define AR9_GPIO_P1_ALTSEL1					((volatile u32 *)(AR9_GPIO+ 0x0050))
+/***Port 2 Alternate Function Select Register 0 (0080 H) ***/
+#define AR9_GPIO_P2_ALTSEL1						((volatile u32 *)(AR9_GPIO+ 0x0080))
+/***Port 3 Alternate Function Select Register 0 (0064 H) ***/
+#define AR9_GPIO_P3_ALTSEL1						((volatile u32 *)(AR9_GPIO+ 0x0064))
+/***Port 0 Open Drain Control Register (0024H)***/
+#define AR9_GPIO_P0_OD							((volatile u32 *)(AR9_GPIO+ 0x0024))
+/***Port 1 Open Drain Control Register (0054H)***/
+#define AR9_GPIO_P1_OD							((volatile u32 *)(AR9_GPIO+ 0x0054))
+/***Port 2 Open Drain Control Register (0084H)***/
+#define AR9_GPIO_P2_OD							((volatile u32 *)(AR9_GPIO+ 0x0084))
+/***Port 3 Open Drain Control Register (0034H)***/
+#define AR9_GPIO_P3_OD							((volatile u32 *)(AR9_GPIO+ 0x0034))
+/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/
+#define AR9_GPIO_P0_STOFF						((volatile u32 *)(AR9_GPIO+ 0x0028))
+/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/
+#define AR9_GPIO_P1_STOFF						((volatile u32 *)(AR9_GPIO+ 0x0058))
+/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/
+#define AR9_GPIO_P2_STOFF						((volatile u32 *)(AR9_GPIO+ 0x0088))
+/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/
+//#define AR9_GPIO_P3_STOFF						((volatile u32 *)(AR9_GPIO+ 0x0094))
+/***Port 0 Pull Up/Pull Down Select Register (002C H)***/
+#define AR9_GPIO_P0_PUDSEL						((volatile u32 *)(AR9_GPIO+ 0x002C))
+/***Port 1 Pull Up/Pull Down Select Register (005C H)***/
+#define AR9_GPIO_P1_PUDSEL						((volatile u32 *)(AR9_GPIO+ 0x005C))
+/***Port 2 Pull Up/Pull Down Select Register (008C H)***/
+#define AR9_GPIO_P2_PUDSEL						((volatile u32 *)(AR9_GPIO+ 0x008C))
+/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/
+#define AR9_GPIO_P3_PUDSEL						((volatile u32 *)(AR9_GPIO+ 0x0038))
+/***Port 0 Pull Up Device Enable Register (0030 H)***/
+#define AR9_GPIO_P0_PUDEN						((volatile u32 *)(AR9_GPIO+ 0x0030))
+/***Port 1 Pull Up Device Enable Register (0060 H)***/
+#define AR9_GPIO_P1_PUDEN						((volatile u32 *)(AR9_GPIO+ 0x0060))
+/***Port 2 Pull Up Device Enable Register (0090 H)***/
+#define AR9_GPIO_P2_PUDEN						((volatile u32 *)(AR9_GPIO+ 0x0090))
+/***Port 3 Pull Up Device Enable Register (003c H)***/
+#define AR9_GPIO_P3_PUDEN						((volatile u32 *)(AR9_GPIO+ 0x003C))
+
+/***********************************************************************/
+/*  Module      :  CGU register address and bits                       */
+/***********************************************************************/
+#define AR9_CGU									(0xBF103000)
+/***CGU Clock PLL0 ***/
+#define AR9_CGU_PLL0_CFG						((volatile u32*)(AR9_CGU+ 0x0004))
+/***CGU Clock PLL1 ***/
+#define AR9_CGU_PLL1_CFG						((volatile u32*)(AR9_CGU+ 0x0008))
+/***CGU Clock SYS Mux Register***/
+#define AR9_CGU_SYS								((volatile u32*)(AR9_CGU+ 0x0010))
+/***CGU Interface Clock Control Register***/
+#define AR9_CGU_IFCCR							((volatile u32*)(AR9_CGU+ 0x0018))
+/***CGU PCI Clock Control Register**/
+#define AR9_CGU_PCICR							((volatile u32*)(AR9_CGU+ 0x0034))
+#define CLOCK_60M								60000000
+#define CLOCK_83M								83333333
+#define CLOCK_111M								111111111
+#define CLOCK_133M								133333333
+#define CLOCK_166M								166666667
+#define CLOCK_196M								196666667
+#define CLOCK_333M								333333333
+#define CLOCK_366M								366666667
+#define CLOCK_500M								500000000
+
+/***********************************************************************/
+/*  Module      :  MPS register address and bits                       */
+/***********************************************************************/
+#define AR9_MPS									(KSEG1+0x1F107000)
+#define AR9_MPS_CHIPID							((volatile u32*)(AR9_MPS + 0x0344))
+#define AR9_MPS_CHIPID_VERSION_GET(value)		(((value) >> 28) & ((1 << 4) - 1))
+#define AR9_MPS_CHIPID_PARTNUM_GET(value)		(((value) >> 12) & ((1 << 16) - 1))
+#define AR9_MPS_CHIPID_MANID_GET(value)			(((value) >> 1) & ((1 << 10) - 1))
+
+/***********************************************************************/
+/*  Module      :  EBU register address and bits                       */
+/***********************************************************************/
+#define AR9_EBU									(0xBE105300)
+
+#define AR9_EBU_CLC								((volatile u32*)(AR9_EBU+ 0x0000))
+#define AR9_EBU_CLC_DISS						(1 << 1)
+#define AR9_EBU_CLC_DISR						(1 << 0)
+
+#define AR9_EBU_ID								((volatile u32*)(AR9_EBU+ 0x0008))
+
+/***EBU Global Control Register***/
+#define AR9_EBU_CON								((volatile u32*)(AR9_EBU+ 0x0010))
+#define AR9_EBU_CON_DTACS (value)				(((( 1 << 3) - 1) & (value)) << 20)
+#define AR9_EBU_CON_DTARW (value)				(((( 1 << 3) - 1) & (value)) << 16)
+#define AR9_EBU_CON_TOUTC (value)				(((( 1 << 8) - 1) & (value)) << 8)
+#define AR9_EBU_CON_ARBMODE (value)				(((( 1 << 2) - 1) & (value)) << 6)
+#define AR9_EBU_CON_ARBSYNC						(1 << 5)
+//#define AR9_EBU_CON_1							(1 << 3)
+
+/***EBU Address Select Register 0***/
+#define AR9_EBU_ADDSEL0							((volatile u32*)(AR9_EBU + 0x0020))
+/***EBU Address Select Register 1***/
+#define AR9_EBU_ADDSEL1							((volatile u32*)(AR9_EBU + 0x0024))
+/***EBU Address Select Register 2***/
+#define AR9_EBU_ADDSEL2							((volatile u32*)(AR9_EBU + 0x0028))
+/***EBU Address Select Register 3***/
+#define AR9_EBU_ADDSEL3							((volatile u32*)(AR9_EBU + 0x002C))
+#define AR9_EBU_ADDSEL_BASE (value)				(((( 1 << 20) - 1) & (value)) << 12)
+#define AR9_EBU_ADDSEL_MASK (value)				(((( 1 << 4) - 1) & (value)) << 4)
+#define AR9_EBU_ADDSEL_MIRRORE					(1 << 1)
+#define AR9_EBU_ADDSEL_REGEN					(1 << 0)
+
+/***EBU Bus Configuration Register 0***/
+#define AR9_EBU_BUSCON0							((volatile u32*)(AR9_EBU+ 0x0060))
+#define AR9_EBU_BUSCON0_WRDIS					(1 << 31)
+#define AR9_EBU_BUSCON0_ADSWP (value)			(1 << 30)
+#define AR9_EBU_BUSCON0_PG_EN (value)			(1 << 29)
+#define AR9_EBU_BUSCON0_AGEN (value)			(((( 1 << 3) - 1) & (value)) << 24)
+#define AR9_EBU_BUSCON0_SETUP					(1 << 22)
+#define AR9_EBU_BUSCON0_WAIT (value)			(((( 1 << 2) - 1) & (value)) << 20)
+#define AR9_EBU_BUSCON0_WAITINV					(1 << 19)
+#define AR9_EBU_BUSCON0_VN_EN					(1 << 18)
+#define AR9_EBU_BUSCON0_PORTW (value)			(((( 1 << 2) - 1) & (value)) << 16)
+#define AR9_EBU_BUSCON0_ALEC (value)			(((( 1 << 2) - 1) & (value)) << 14)
+#define AR9_EBU_BUSCON0_BCGEN (value)			(((( 1 << 2) - 1) & (value)) << 12)
+#define AR9_EBU_BUSCON0_WAITWDC (value)			(((( 1 << 4) - 1) & (value)) << 8)
+#define AR9_EBU_BUSCON0_WAITRRC (value)			(((( 1 << 2) - 1) & (value)) << 6)
+#define AR9_EBU_BUSCON0_HOLDC (value)			(((( 1 << 2) - 1) & (value)) << 4)
+#define AR9_EBU_BUSCON0_RECOVC (value)			(((( 1 << 2) - 1) & (value)) << 2)
+#define AR9_EBU_BUSCON0_CMULT (value)			(((( 1 << 2) - 1) & (value)) << 0)
+
+/***EBU Bus Configuration Register 1***/
+#define AR9_EBU_BUSCON1							((volatile u32*)(AR9_EBU+ 0x0064))
+#define AR9_EBU_BUSCON1_WRDIS					(1 << 31)
+#define AR9_EBU_BUSCON1_ALEC (value)			(((( 1 << 2) - 1) & (value)) << 29)
+#define AR9_EBU_BUSCON1_BCGEN (value)			(((( 1 << 2) - 1) & (value)) << 27)
+#define AR9_EBU_BUSCON1_AGEN (value)			(((( 1 << 2) - 1) & (value)) << 24)
+#define AR9_EBU_BUSCON1_CMULTR (value)			(((( 1 << 2) - 1) & (value)) << 22)
+#define AR9_EBU_BUSCON1_WAIT (value)			(((( 1 << 2) - 1) & (value)) << 20)
+#define AR9_EBU_BUSCON1_WAITINV					(1 << 19)
+#define AR9_EBU_BUSCON1_SETUP					(1 << 18)
+#define AR9_EBU_BUSCON1_PORTW (value)			(((( 1 << 2) - 1) & (value)) << 16)
+#define AR9_EBU_BUSCON1_WAITRDC (value)			(((( 1 << 7) - 1) & (value)) << 9)
+#define AR9_EBU_BUSCON1_WAITWRC (value)			(((( 1 << 3) - 1) & (value)) << 6)
+#define AR9_EBU_BUSCON1_HOLDC (value)			(((( 1 << 2) - 1) & (value)) << 4)
+#define AR9_EBU_BUSCON1_RECOVC (value)			(((( 1 << 2) - 1) & (value)) << 2)
+#define AR9_EBU_BUSCON1_CMULT (value)			(((( 1 << 2) - 1) & (value)) << 0)
+
+/***EBU Bus Configuration Register 2***/
+#define AR9_EBU_BUSCON2							((volatile u32*)(AR9_EBU+ 0x0068))
+#define AR9_EBU_BUSCON2_WRDIS					(1 << 31)
+#define AR9_EBU_BUSCON2_ALEC (value)			(((( 1 << 2) - 1) & (value)) << 29)
+#define AR9_EBU_BUSCON2_BCGEN (value)			(((( 1 << 2) - 1) & (value)) << 27)
+#define AR9_EBU_BUSCON2_AGEN (value)			(((( 1 << 2) - 1) & (value)) << 24)
+#define AR9_EBU_BUSCON2_CMULTR (value)			(((( 1 << 2) - 1) & (value)) << 22)
+#define AR9_EBU_BUSCON2_WAIT (value)			(((( 1 << 2) - 1) & (value)) << 20)
+#define AR9_EBU_BUSCON2_WAITINV					(1 << 19)
+#define AR9_EBU_BUSCON2_SETUP					(1 << 18)
+#define AR9_EBU_BUSCON2_PORTW (value)			(((( 1 << 2) - 1) & (value)) << 16)
+#define AR9_EBU_BUSCON2_WAITRDC (value)			(((( 1 << 7) - 1) & (value)) << 9)
+#define AR9_EBU_BUSCON2_WAITWRC (value)			(((( 1 << 3) - 1) & (value)) << 6)
+#define AR9_EBU_BUSCON2_HOLDC (value)			(((( 1 << 2) - 1) & (value)) << 4)
+#define AR9_EBU_BUSCON2_RECOVC (value)			(((( 1 << 2) - 1) & (value)) << 2)
+#define AR9_EBU_BUSCON2_CMULT (value)			(((( 1 << 2) - 1) & (value)) << 0)
+
+/***EBU Bus Configuration Register 2***/
+#define AR9_EBU_BUSCON3							((volatile u32*)(AR9_EBU+ 0x006C))
+#define AR9_EBU_BUSCON3_WRDIS					(1 << 31)
+#define AR9_EBU_BUSCON3_ADSWP (value)			(1 << 30)
+#define AR9_EBU_BUSCON3_PG_EN (value)			(1 << 29)
+#define AR9_EBU_BUSCON3_AGEN (value)			(((( 1 << 3) - 1) & (value)) << 24)
+#define AR9_EBU_BUSCON3_SETUP					(1 << 22)
+#define AR9_EBU_BUSCON3_WAIT (value) 			(((( 1 << 2) - 1) & (value)) << 20)
+#define AR9_EBU_BUSCON3_WAITINV					(1 << 19)
+#define AR9_EBU_BUSCON3_VN_EN					(1 << 18)
+#define AR9_EBU_BUSCON3_PORTW (value)			(((( 1 << 2) - 1) & (value)) << 16)
+#define AR9_EBU_BUSCON3_ALEC (value)			(((( 1 << 2) - 1) & (value)) << 14)
+#define AR9_EBU_BUSCON3_BCGEN (value)			(((( 1 << 2) - 1) & (value)) << 12)
+#define AR9_EBU_BUSCON3_WAITWDC (value)			(((( 1 << 4) - 1) & (value)) << 8)
+#define AR9_EBU_BUSCON3_WAITRRC (value)			(((( 1 << 2) - 1) & (value)) << 6)
+#define AR9_EBU_BUSCON3_HOLDC (value)			(((( 1 << 2) - 1) & (value)) << 4)
+#define AR9_EBU_BUSCON3_RECOVC (value)			(((( 1 << 2) - 1) & (value)) << 2)
+#define AR9_EBU_BUSCON3_CMULT (value)			(((( 1 << 2) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  SDRAM register address and bits                     */
+/***********************************************************************/
+#define AR9_SDRAM								(0xBF800000)
+
+/***********************************************************************/
+/*  Module      :  ASC0 register address and bits                      */
+/***********************************************************************/
+#define AR9_ASC0								(KSEG1 | 0x1E100400)
+#define AR9_ASC0_TBUF							((volatile u32*)(AR9_ASC0 + 0x0020))
+#define AR9_ASC0_RBUF							((volatile u32*)(AR9_ASC0 + 0x0024))
+#define AR9_ASC0_FSTAT							((volatile u32*)(AR9_ASC0 + 0x0048))
+
+/***********************************************************************/
+/*  Module      :  ASC1 register address and bits                      */
+/***********************************************************************/
+#define AR9_ASC1								(KSEG1 | 0x1E100C00)
+#define AR9_ASC1_TBUF							((volatile u32*)(AR9_ASC1 + 0x0020))
+#define AR9_ASC1_RBUF							((volatile u32*)(AR9_ASC1 + 0x0024))
+#define AR9_ASC1_FSTAT							((volatile u32*)(AR9_ASC1 + 0x0048))
+
+/***********************************************************************/
+/*  Module      :  DMA register address and bits                       */
+/***********************************************************************/
+#define AR9_DMA_OFFSET 							(0xBE104100)
+/***********************************************************************/
+#define AR9_DMA_CLC								((volatile u32*)(AR9_DMA_OFFSET + 0x0000))
+#define AR9_DMA_ID								((volatile u32*)(AR9_DMA_OFFSET + 0x0008))
+#define AR9_DMA_CTRL							(volatile u32*)(AR9_DMA_BASE + 0x10)
+
+/** DMA Port Select Register */
+#define AR9_DMA_PS								((volatile u32*)(AR9_DMA_OFFSET + 0x0040))
+/** DMA Port Control Register */
+#define AR9_DMA_PCTRL							((volatile u32*)(AR9_DMA_OFFSET + 0x0044))
+#define AR9_DMA_IRNEN							((volatile u32*)(AR9_DMA_OFFSET + 0x00F4))
+#define AR9_DMA_IRNCR							((volatile u32*)(AR9_DMA_OFFSET + 0x00F8))
+#define AR9_DMA_IRNICR							((volatile u32*)(AR9_DMA_OFFSET + 0x00FC))
+
+#define AR9_DMA_CS								((volatile u32*)(AR9_DMA_OFFSET + 0x0018))
+#define AR9_DMA_CCTRL							((volatile u32*)(AR9_DMA_OFFSET + 0x001C))
+#define AR9_DMA_CDBA							((volatile u32*)(AR9_DMA_OFFSET + 0x0020))
+#define AR9_DMA_CIE								((volatile u32*)(AR9_DMA_OFFSET + 0x002C))
+#define AR9_DMA_CIS								((volatile u32*)(AR9_DMA_OFFSET + 0x0028))
+#define AR9_DMA_CDLEN							((volatile u32*)(AR9_DMA_OFFSET + 0x0024))
+#define AR9_DMA_CPOLL							((volatile u32*)(AR9_DMA_OFFSET + 0x0014))
+
+/***********************************************************************/
+/*  Module      :  GPORT switch register                               */
+/***********************************************************************/
+#define AR9_SW									(0xBE108000)
+#define AR9_SW_PS								(AR9_SW + 0x000)
+#define AR9_SW_P0_CTL							(AR9_SW + 0x004)
+#define AR9_SW_P1_CTL							(AR9_SW + 0x008)
+#define AR9_SW_P2_CTL							(AR9_SW + 0x00C)
+#define AR9_SW_P0_VLAN							(AR9_SW + 0x010)
+#define AR9_SW_P1_VLAN							(AR9_SW + 0x014)
+#define AR9_SW_P2_VLAN							(AR9_SW + 0x018)
+#define AR9_SW_P0_INCTL							(AR9_SW + 0x020)
+#define AR9_SW_P1_INCTL							(AR9_SW + 0x024)
+#define AR9_SW_P2_INCTL							(AR9_SW + 0x028)
+#define AR9_SW_DF_PORTMAP						(AR9_SW + 0x02C)
+#define AR9_SW_P0_ECS_Q32						(AR9_SW + 0x030)
+#define AR9_SW_P0_ECS_Q10						(AR9_SW + 0x034)
+#define AR9_SW_P0_ECW_Q32						(AR9_SW + 0x038)
+#define AR9_SW_P0_ECW_Q10						(AR9_SW + 0x03C)
+#define AR9_SW_P1_ECS_Q32						(AR9_SW + 0x040)
+#define AR9_SW_P1_ECS_Q10						(AR9_SW + 0x044)
+#define AR9_SW_P1_ECW_Q32						(AR9_SW + 0x048)
+#define AR9_SW_P1_ECW_Q10						(AR9_SW + 0x04C)
+#define AR9_SW_P2_ECS_Q32						(AR9_SW + 0x050)
+#define AR9_SW_P2_ECS_Q10						(AR9_SW + 0x054)
+#define AR9_SW_P2_ECW_Q32						(AR9_SW + 0x058)
+#define AR9_SW_P2_ECW_Q10						(AR9_SW + 0x05C)
+#define AR9_SW_INT_ENA							(AR9_SW + 0x060)
+#define AR9_SW_INT_ST							(AR9_SW + 0x064)
+#define AR9_SW_GCTL0							(AR9_SW + 0x068)
+#define AR9_SW_GCTL1							(AR9_SW + 0x06C)
+#define AR9_SW_ARP								(AR9_SW + 0x070)
+#define AR9_SW_STRM_CTL							(AR9_SW + 0x074)
+#define AR9_SW_RGMII_CTL						(AR9_SW + 0x078)
+#define AR9_SW_1P_PRT							(AR9_SW + 0x07C)
+#define AR9_SW_GBKT_SZBS						(AR9_SW + 0x080)
+#define AR9_SW_GBKT_SZEBS						(AR9_SW + 0x084)
+#define AR9_SW_BF_TH							(AR9_SW + 0x088)
+#define AR9_SW_PMAC_HD_CTL						(AR9_SW + 0x08C)
+#define AR9_SW_PMAC_SA1							(AR9_SW + 0x090)
+#define AR9_SW_PMAC_SA2							(AR9_SW + 0x094)
+#define AR9_SW_PMAC_DA1							(AR9_SW + 0x098)
+#define AR9_SW_PMAC_DA2							(AR9_SW + 0x09C)
+#define AR9_SW_PMAC_VLAN						(AR9_SW + 0x0A0)
+#define AR9_SW_PMAC_TX_IPG						(AR9_SW + 0x0A4)
+#define AR9_SW_PMAC_RX_IPG						(AR9_SW + 0x0A8)
+#define AR9_SW_ADR_TB_CTL0						(AR9_SW + 0x0AC)
+#define AR9_SW_ADR_TB_CTL1						(AR9_SW + 0x0B0)
+#define AR9_SW_ADR_TB_CTL2						(AR9_SW + 0x0B4)
+#define AR9_SW_ADR_TB_ST0						(AR9_SW + 0x0B8)
+#define AR9_SW_ADR_TB_ST1						(AR9_SW + 0x0BC)
+#define AR9_SW_ADR_TB_ST2						(AR9_SW + 0x0C0)
+#define AR9_SW_RMON_CTL							(AR9_SW + 0x0C4)
+#define AR9_SW_RMON_ST							(AR9_SW + 0x0C8)
+#define AR9_SW_MDIO_CTL							(AR9_SW + 0x0CC)
+#define AR9_SW_MDIO_DATA						(AR9_SW + 0x0D0)
+#define AR9_SW_TP_FLT_ACT						(AR9_SW + 0x0D4)
+#define AR9_SW_PRTCL_FLT_ACT					(AR9_SW + 0x0D8)
+#define AR9_SW_VLAN_FLT0						(AR9_SW + 0x100)
+#define AR9_SW_VLAN_FLT1						(AR9_SW + 0x104)
+#define AR9_SW_VLAN_FLT2						(AR9_SW + 0x108)
+#define AR9_SW_VLAN_FLT3						(AR9_SW + 0x10C)
+#define AR9_SW_VLAN_FLT4						(AR9_SW + 0x110)
+#define AR9_SW_VLAN_FLT5						(AR9_SW + 0x114)
+#define AR9_SW_VLAN_FLT6						(AR9_SW + 0x118)
+#define AR9_SW_VLAN_FLT7						(AR9_SW + 0x11C)
+#define AR9_SW_VLAN_FLT8						(AR9_SW + 0x120)
+#define AR9_SW_VLAN_FLT9						(AR9_SW + 0x124)
+#define AR9_SW_VLAN_FLT10						(AR9_SW + 0x128)
+#define AR9_SW_VLAN_FLT11						(AR9_SW + 0x12C)
+#define AR9_SW_VLAN_FLT12						(AR9_SW + 0x130)
+#define AR9_SW_VLAN_FLT13						(AR9_SW + 0x134)
+#define AR9_SW_VLAN_FLT14						(AR9_SW + 0x138)
+#define AR9_SW_VLAN_FLT15						(AR9_SW + 0x13C)
+#define AR9_SW_TP_FLT10							(AR9_SW + 0x140)
+#define AR9_SW_TP_FLT32							(AR9_SW + 0x144)
+#define AR9_SW_TP_FLT54							(AR9_SW + 0x148)
+#define AR9_SW_TP_FLT76							(AR9_SW + 0x14C)
+#define AR9_SW_DFSRV_MAP0						(AR9_SW + 0x150)
+#define AR9_SW_DFSRV_MAP1						(AR9_SW + 0x154)
+#define AR9_SW_DFSRV_MAP2						(AR9_SW + 0x158)
+#define AR9_SW_DFSRV_MAP3						(AR9_SW + 0x15C)
+#define AR9_SW_TCP_PF0							(AR9_SW + 0x160)
+#define AR9_SW_TCP_PF1							(AR9_SW + 0x164)
+#define AR9_SW_TCP_PF2							(AR9_SW + 0x168)
+#define AR9_SW_TCP_PF3							(AR9_SW + 0x16C)
+#define AR9_SW_TCP_PF4							(AR9_SW + 0x170)
+#define AR9_SW_TCP_PF5							(AR9_SW + 0x174)
+#define AR9_SW_TCP_PF6							(AR9_SW + 0x178)
+#define AR9_SW_TCP_PF7							(AR9_SW + 0x17C)
+#define AR9_SW_RA_03_00							(AR9_SW + 0x180)
+#define AR9_SW_RA_07_04							(AR9_SW + 0x184)
+#define AR9_SW_RA_0B_08							(AR9_SW + 0x188)
+#define AR9_SW_RA_0F_0C							(AR9_SW + 0x18C)
+#define AR9_SW_RA_13_10							(AR9_SW + 0x190)
+#define AR9_SW_RA_17_14							(AR9_SW + 0x194)
+#define AR9_SW_RA_1B_18							(AR9_SW + 0x198)
+#define AR9_SW_RA_1F_1C							(AR9_SW + 0x19C)
+#define AR9_SW_RA_23_20							(AR9_SW + 0x1A0)
+#define AR9_SW_RA_27_24							(AR9_SW + 0x1A4)
+#define AR9_SW_RA_2B_28							(AR9_SW + 0x1A8)
+#define AR9_SW_RA_2F_2C							(AR9_SW + 0x1AC)
+#define AR9_SW_F0								(AR9_SW + 0x1B0)
+#define AR9_SW_F1								(AR9_SW + 0x1B4)
+
+#define REG32(addr)								*((volatile u32 *)(addr))

package/uboot-lantiq/files/include/configs/easy50712.h

@@ -112,4 +112,6 @@
 #	define CONFIG_EBU_BUSCON0		0x0001D7FF
 #endif
 
+#define CONFIG_CMD_HTTPD		/* enable upgrade via HTTPD */
+
 #endif	/* __CONFIG_H */

package/uboot-lantiq/files/include/configs/easy50812.h

@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the Danube reference board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* #define DEBUG */
+
+#define CONFIG_MIPS32		1		/* MIPS32 CPU compatible */
+#define CONFIG_MIPS34KC		1		/* MIPS 34Kc CPU core */	
+#define CONFIG_AR9		1		/* an AR9 device */
+#define CONFIG_EASY50812	1		/* on the AR9 reference board */
+#define CONFIG_SYS_MAX_RAM	32*1024*1024 	/* 32 MB */
+#define CONFIG_FLASH_CFI_DRIVER	1		/* using CFI flash driver */
+
+#define CONFIG_SYS_INIT_RAM_LOCK_MIPS
+
+/* use PPL1 and fixed values for CPU / DDR and bus speed */
+#define CONFIG_USE_PLL1
+#define CONFIG_CPU_333M_RAM_166M
+#define CONFIG_CLASS_II_DDR_PAD
+
+#ifdef CONFIG_SYS_RAMBOOT
+	#define CONFIG_SKIP_LOWLEVEL_INIT	/* no cache */
+#else
+	#define CONFIG_SYS_EBU_BOOT
+	#define INFINEON_EBU_BOOTCFG	0x688C688C	/* CMULT = 8 for 150 MHz */
+#endif
+
+#ifndef	CPU_CLOCK_RATE
+#define CPU_CLOCK_RATE		(ifx_get_cpuclk())
+#endif
+
+#define	CONFIG_SYS_PROMPT	"AR9 => "	/* Monitor Command Prompt */
+#undef CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser		*/
+
+/*
+ * Include common defines/options for all Lantiq boards
+ */
+#include "ifx-common.h"
+
+/*
+ * Cache Configuration (cpu/chip specific, ar9)
+ */
+#define CONFIG_SYS_DCACHE_SIZE		(16384)
+#define CONFIG_SYS_ICACHE_SIZE		(16384)
+#define CONFIG_SYS_CACHELINE_SIZE	(32)
+#define CONFIG_SYS_MIPS_CACHE_OPER_MODE	CONF_CM_CACHABLE_NO_WA
+
+#define CONFIG_NET_MULTI
+#if 0
+#define CONFIG_M4530_ETH
+#define CONFIG_M4530_FPGA
+#endif
+
+#define CONFIG_IFX_ETOP			/* lantiq ethernet cpe interface */
+#define CLK_OUT2_25MHZ
+#define CONFIG_EXTRA_SWITCH		/* search for external switches like tantos */
+#define CONFIG_RMII			/*  use interface in RMII mode */
+#define CONFIG_MII
+#define CONFIG_CMD_MII			/* enable MII command */	
+
+#define CONFIG_IFX_ASC			/* use lantiq ASC driver */
+#ifdef CONFIG_USE_ASC0
+#define CONFIG_SYS_IFX_ASC_BASE		0x1E100400
+#else
+#define CONFIG_SYS_IFX_ASC_BASE		0x1E100C00
+#endif
+
+#ifdef CONFIG_SYS_RAMBOOT
+/* Configuration of EBU: */
+/* starting address from 0xb0000000 */
+/* make the flash available from RAM boot */
+#	define CONFIG_EBU_ADDSEL0		0x10000031
+#	define CONFIG_EBU_BUSCON0		0x0001D7FF
+#endif
+
+#define CONFIG_CMD_HTTPD		/* enable upgrade via HTTPD */
+
+#endif	/* __CONFIG_H */

package/uboot-lantiq/patches/100-ifx_targets.patch

@@ -23,7 +23,7 @@
  	${LIST_au1xx0}	\
 --- a/Makefile
 +++ b/Makefile
-@@ -474,7 +475,7 @@ $(obj)include/autoconf.mk: $(obj)include
+@@ -474,7 +474,7 @@ $(obj)include/autoconf.mk: $(obj)include
  	set -e ; \
  	: Extract the config macros ; \
  	$(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \
@@ -32,7 +32,7 @@
  	mv $@.tmp $@
  
  #########################################################################
-@@ -3354,7 +3355,7 @@ incaip_config: unconfig
+@@ -3354,7 +3354,7 @@ incaip_config: unconfig
  		{ echo "#define CPU_CLOCK_RATE 150000000" >>$(obj)include/config.h ; \
  		  $(XECHO) "... with 150MHz system clock" ; \
  		}
@@ -41,7 +41,7 @@
  
  tb0229_config: unconfig
  	@$(MKCONFIG) $(@:_config=) mips mips tb0229
-@@ -3395,6 +3396,30 @@ vct_platinumavc_onenand_small_config: un
+@@ -3395,6 +3395,50 @@ vct_platinumavc_onenand_small_config: un
  	@$(MKCONFIG) -a vct mips mips vct micronas
  
  #########################################################################
@@ -68,6 +68,26 @@
 +	fi
 +	@$(MKCONFIG) -a $(word 1,$(subst _, ,$@)) mips mips easy50712 infineon danube
 +
++easy50812%config	: unconfig
++	@mkdir -p $(obj)include
++	@mkdir -p $(obj)board/infineon/easy50812
++	@[ -z "$(findstring ramboot,$@)" ] || \
++		{ echo "TEXT_BASE = 0xA0400000" >$(obj)board/infineon/easy50812/config.tmp ; \
++			echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \
++			$(XECHO) "... with ramboot configuration" ; \
++		}
++	@if [ "$(findstring _DDR,$@)" ] ; then \
++		echo "#define CONFIG_USE_DDR_RAM"  >>$(obj)include/config.h ; \
++		DDR=$(subst DDR,,$(filter DDR%,$(subst _, ,$@))); \
++		case "$${DDR}" in \
++		111M|166M|e111M|e166M|promos400|samsung166|psc166) \
++			$(XECHO) "... with DDR RAM config $${DDR}" ; \
++			echo "#define CONFIG_USE_DDR_RAM_CFG_$${DDR}" >>$(obj)include/config.h ;; \
++		*)	$(XECHO) "... DDR RAM config \\\"$${DDR}\\\" unknown, use default"; \
++		esac; \
++	fi
++	@$(MKCONFIG) -a $(word 1,$(subst _, ,$@)) mips mips easy50812 infineon ar9
++
 +#########################################################################
  ## MIPS32 AU1X00
  #########################################################################

rules.mk

@@ -104,7 +104,7 @@ TARGET_PATH:=$(STAGING_DIR_HOST)/bin:$(PATH)
 TARGET_CFLAGS:=$(TARGET_OPTIMIZATION)$(if $(CONFIG_DEBUG), -g3)
 TARGET_CPPFLAGS:=-I$(STAGING_DIR)/usr/include -I$(STAGING_DIR)/include
 TARGET_LDFLAGS:=-L$(STAGING_DIR)/usr/lib -L$(STAGING_DIR)/lib
-LIBGCC_S=$(if $(wildcard $(TOOLCHAIN_DIR)/lib/libgcc_s.so),-L$(TOOLCHAIN_DIR)/lib -lgcc_s,$(wildcard $(TOOLCHAIN_DIR)/lib/gcc/*/*/libgcc.a))
+LIBGCC_S=$(if $(wildcard $(TOOLCHAIN_DIR)/lib/libgcc_s.so),-L$(TOOLCHAIN_DIR)/lib -lgcc_s,$(wildcard $(TOOLCHAIN_DIR)/usr/lib/gcc/*/*/libgcc.a))
 
 ifndef DUMP
   ifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),)

target/imagebuilder/Config.in

@@ -1,7 +1,6 @@
 config IB
 	bool "Build the OpenWrt Image Builder"
 	depends !TARGET_ROOTFS_INITRAMFS
-	depends !TARGET_uml
 	depends !PROFILE_KCONFIG
 	depends !EXTERNAL_TOOLCHAIN
 	help

target/imagebuilder/Makefile

@@ -31,17 +31,15 @@ $(BIN_DIR)/$(IB_NAME).tar.bz2: clean
 		$(TMP_DIR)/.packageinfo \
 		$(PKG_BUILD_DIR)/
 	$(CP) $(PACKAGE_DIR) $(PKG_BUILD_DIR)/packages
-	$(CP) $(TOOLCHAIN_DIR)/bin $(PKG_BUILD_DIR)/staging_dir/host/
-	$(CP) $(STAGING_DIR_HOST)/bin/* $(PKG_BUILD_DIR)/staging_dir/host/bin/
+	$(CP) $(STAGING_DIR_HOST)/bin $(PKG_BUILD_DIR)/staging_dir/host/
 	$(CP) $(TOPDIR)/target/linux $(PKG_BUILD_DIR)/target/
 	rm -rf \
-		$(PKG_BUILD_DIR)/target/linux/*/patches \
-		$(PKG_BUILD_DIR)/target/linux/*/*/patches
+		$(PKG_BUILD_DIR)/target/linux/*/files{,-*} \
+		$(PKG_BUILD_DIR)/target/linux/*/patches{,-*}
 	-cp $(KERNEL_BUILD_DIR)/* $(IB_KDIR)/ # don't copy subdirectories here
 	echo REVISION:="$(REVISION)" > $(PKG_BUILD_DIR)/include/version.mk
-	find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
-	find $(PKG_BUILD_DIR) -name CVS | $(XARGS) rm -rf
-	find $(PKG_BUILD_DIR) -name .git | $(XARGS) rm -rf
+	find $(PKG_BUILD_DIR) -name CVS -o -name .git -o -name .svn \
+	  | $(XARGS) rm -rf
 	$(TAR) c -C $(BUILD_DIR) $(IB_NAME) | bzip2 -c > $@
 
 download:

target/linux/brcm-2.4/files/arch/mips/bcm947xx/prom.c

@@ -21,25 +21,32 @@ void __init
 prom_init(int argc, const char **argv)
 {
 	unsigned long mem;
+	unsigned long max;
 
         mips_machgroup = MACH_GROUP_BRCM;
         mips_machtype = MACH_BCM947XX;
 
-	/* Figure out memory size by finding aliases */
+	/* Figure out memory size by finding aliases
+	 * 
+	 * BCM47XX uses 128MB for addressing the ram, if the system contains
+	 * less that that amount of ram it remaps the ram more often into the
+	 * available space.
+	 * Accessing memory after 128MB will cause an exception.
+	 * max contains the biggest possible address supported by the platform.
+	 * If the method wants to try something above we assume 128MB ram.
+ 	 */
+	max = ((unsigned long)(prom_init) | ((128 << 20) - 1));
 	for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
+		if (((unsigned long)(prom_init) + mem) > max) {
+			mem = (128 << 20);
+			printk("assume 128MB RAM\n");
+			break;
+		}
 		if (*(unsigned long *)((unsigned long)(prom_init) + mem) == 
 		    *(unsigned long *)(prom_init))
 			break;
 	}
 
-	/* Ignoring the last page when ddr size is 128M. Cached
-	 * accesses to last page is causing the processor to prefetch
-	 * using address above 128M stepping out of the ddr address
-	 * space.
-	 */
-	if (mem == 0x8000000)
-		mem -= 0x1000;
-
 	add_memory_region(0, mem, BOOT_MEM_RAM);
 }
 

target/linux/brcm63xx/files/arch/mips/include/asm/mach-bcm63xx/bcm_tag.h

@@ -1,178 +1,69 @@
 #ifndef __BCM63XX_TAG_H
 #define __BCM63XX_TAG_H
 
-#define IMAGE_LEN 10                   /* Length of Length Field */
-#define ADDRESS_LEN 12                 /* Length of Address field */
-#define TAGID_LEN  6                   /* Length of tag ID */
-#define TAGINFO_LEN 20                 /* Length of vendor information field in tag */
 #define TAGVER_LEN 4                   /* Length of Tag Version */
 #define TAGLAYOUT_LEN 4                /* Length of FlashLayoutVer */
+#define SIG1_LEN 20		       /* Company Signature 1 Length */
+#define SIG2_LEN 14                    /* Company Signature 2 Lenght */
+#define BOARDID_LEN 16		       /* Length of BoardId */
+#define ENDIANFLAG_LEN 2               /* Endian Flag Length */
+#define CHIPID_LEN 6		       /* Chip Id Length */
+#define IMAGE_LEN 10                   /* Length of Length Field */
+#define ADDRESS_LEN 12                 /* Length of Address field */
+#define DUALFLAG_LEN 2		       /* Dual Image flag Length */
+#define INACTIVEFLAG_LEN 2	       /* Inactie Flag Length */
+#define RSASIG_LEN 20   	       /* Length of RSA Signature in tag */
+#define TAGINFO1_LEN 30                /* Length of vendor information field1 in tag */
+#define FLASHLAYOUTVER_LEN 4	       /* Length of Flash Layout Version String tag */
+#define TAGINFO2_LEN 16                /* Length of vendor information field2 in tag */
+#define CRC_LEN 4                      /* Length of CRC in bytes */
+#define ALTTAGINFO_LEN 54              /* Alternate length for vendor information; Pirelli */
 
-#define NUM_TAGID 5
+#define NUM_PIRELLI 2
 #define IMAGETAG_CRC_START		0xFFFFFFFF
 
-struct tagiddesc_t {
-  char tagid[TAGID_LEN + 1];
-  char tagiddesc[80];
-};
-
- // bc221 is used by BT Voyager and should be right
- // bc310 should be right, and may apply to 3.08 code as well
-#define TAGID_DEFINITIONS { \
-  { "bccfe", "Broadcom CFE flash image" }, \
-  { "bc300", "Broadcom code version 3.00-3.06 and all ftp/tftp flash" }, \
-  { "ag306", "Alice Gate (Pirelli, based on Broadcom 3.06)" }, \
-  { "bc221", "Broadcom code version 2.21" }, \
-  { "bc310", "Broadcom code version 3.10-3.12" }, \
+#define PIRELLI_BOARDS { \
+  "AGPF_S0", \
+  "DWV_SO", \
 }
 
-struct bcm_tag_bccfe {
-	unsigned char tagVersion[TAGVER_LEN];           // 0-3: Version of the image tag
-	unsigned char sig_1[20];                        // 4-23: Company Line 1
-	unsigned char sig_2[14];                        // 24-37: Company Line 2
-	unsigned char chipid[6];                        // 38-43: Chip this image is for
-	unsigned char boardid[16];                      // 44-59: Board name
-	unsigned char big_endian[2];                    // 60-61: Map endianness -- 1 BE 0 LE
-	unsigned char totalLength[IMAGE_LEN];           // 62-71: Total length of image
-	unsigned char cfeAddress[ADDRESS_LEN];          // 72-83: Address in memory of CFE
-	unsigned char cfeLength[IMAGE_LEN];             // 84-93: Size of CFE
-	unsigned char rootAddress[ADDRESS_LEN];         // 94-105: Address in memory of rootfs
-	unsigned char rootLength[IMAGE_LEN];            // 106-115: Size of rootfs
-	unsigned char kernelAddress[ADDRESS_LEN];       // 116-127: Address in memory of kernel
-	unsigned char kernelLength[IMAGE_LEN];          // 128-137: Size of kernel
-	unsigned char dualImage[2];                     // 138-139: Unused at present
-	unsigned char inactiveFlag[2];                  // 140-141: Unused at present
-        unsigned char information1[TAGINFO_LEN];        // 142-161: Unused at present
-        unsigned char tagId[TAGID_LEN];                 // 162-167: Identifies which type of tag this is, currently two-letter company code, and then three digits for version of broadcom code in which this tag was first introduced
-        unsigned char tagIdCRC[4];                      // 168-171: CRC32 of tagId
-	unsigned char reserved1[44];                    // 172-215: Reserved area not in use
-	unsigned char imageCRC[4];                      // 216-219: CRC32 of images
-        unsigned char reserved2[16];                    // 220-235: Unused at present
-        unsigned char headerCRC[4];                     // 236-239: CRC32 of header excluding tagVersion
-        unsigned char reserved3[16];                    // 240-255: Unused at present
-};
+/*
+ * The broadcom firmware assumes the rootfs starts the image,
+ * therefore uses the rootfs start (flashImageAddress)
+ * to determine where to flash the image.  Since we have the kernel first
+ * we have to give it the kernel address, but the crc uses the length
+ * associated with this address (rootLength), which is added to the kernel
+ * length (kernelLength) to determine the length of image to flash and thus
+ * needs to be rootfs + deadcode (jffs2 EOF marker)
+*/
 
-struct bcm_tag_bc300 {
-	unsigned char tagVersion[TAGVER_LEN];           // 0-3: Version of the image tag
-	unsigned char sig_1[20];                        // 4-23: Company Line 1
-	unsigned char sig_2[14];                        // 24-37: Company Line 2
-	unsigned char chipid[6];                        // 38-43: Chip this image is for
-	unsigned char boardid[16];                      // 44-59: Board name
-	unsigned char big_endian[2];                    // 60-61: Map endianness -- 1 BE 0 LE
-	unsigned char totalLength[IMAGE_LEN];           // 62-71: Total length of image
-	unsigned char cfeAddress[ADDRESS_LEN];          // 72-83: Address in memory of CFE
-	unsigned char cfeLength[IMAGE_LEN];             // 84-93: Size of CFE
-	unsigned char flashImageStart[ADDRESS_LEN];     // 94-105: Address in memory of kernel (start of image)
-	unsigned char flashRootLength[IMAGE_LEN];       // 106-115: Size of rootfs + deadcode (web flash uses this + kernelLength to determine the size of the kernel+rootfs flash image)
- 	unsigned char kernelAddress[ADDRESS_LEN];       // 116-127: Address in memory of kernel
-	unsigned char kernelLength[IMAGE_LEN];          // 128-137: Size of kernel
-	unsigned char dualImage[2];                     // 138-139: Unused at present
-	unsigned char inactiveFlag[2];                  // 140-141: Unused at present
-        unsigned char information1[TAGINFO_LEN];        // 142-161: Unused at present
-        unsigned char tagId[TAGID_LEN];                 // 162-167: Identifies which type of tag this is, currently two-letter company code, and then three digits for version of broadcom code in which this tag was first introduced
-        unsigned char tagIdCRC[4];                      // 168-173: CRC32 to ensure validity of tagId
-        unsigned char rootAddress[ADDRESS_LEN];         // 174-183: Address in memory of rootfs partition
-        unsigned char rootLength[IMAGE_LEN];            // 184-193: Size of rootfs partition
-	unsigned char reserved1[22];                    // 194-215: Reserved area not in use
-	unsigned char imageCRC[4];                      // 216-219: CRC32 of images
-        unsigned char reserved2[16];                    // 220-235: Unused at present
-        unsigned char headerCRC[4];                     // 236-239: CRC32 of header excluding tagVersion
-        unsigned char reserved3[16];                    // 240-255: Unused at present
-};
-
-struct bcm_tag_ag306 {
-	unsigned char tagVersion[TAGVER_LEN];           // 0-3: Version of the image tag
-	unsigned char sig_1[20];                        // 4-23: Company Line 1
-	unsigned char sig_2[14];                        // 24-37: Company Line 2
-	unsigned char chipid[6];                        // 38-43: Chip this image is for
-	unsigned char boardid[16];                      // 44-59: Board name
-	unsigned char big_endian[2];                    // 60-61: Map endianness -- 1 BE 0 LE
-	unsigned char totalLength[IMAGE_LEN];           // 62-71: Total length of image
-	unsigned char cfeAddress[ADDRESS_LEN];          // 72-83: Address in memory of CFE
-	unsigned char cfeLength[IMAGE_LEN];             // 84-93: Size of CFE
-	unsigned char flashImageStart[ADDRESS_LEN];     // 94-105: Address in memory of kernel (start of image)
-	unsigned char flashRootLength[IMAGE_LEN];       // 106-115: Size of rootfs + deadcode (web flash uses this + kernelLength to determine the size of the kernel+rootfs flash image)
- 	unsigned char kernelAddress[ADDRESS_LEN];       // 116-127: Address in memory of kernel
-	unsigned char kernelLength[IMAGE_LEN];          // 128-137: Size of kernel
-	unsigned char dualImage[2];                     // 138-139: Unused at present
-	unsigned char inactiveFlag[2];                  // 140-141: Unused at present
-        unsigned char information1[TAGINFO_LEN];        // 142-161: Unused at present
-	unsigned char information2[54];                 // 162-215: Compilation and related information (not generated/used by OpenWRT)
-	unsigned char kernelCRC[4] ;                    // 216-219: CRC32 of images
-        unsigned char rootAddress[ADDRESS_LEN];         // 220-231: Address in memory of rootfs partition
-        unsigned char tagIdCRC[4];                      // 232-235: Checksum to ensure validity of tagId
-        unsigned char headerCRC[4];                     // 236-239: CRC32 of header excluding tagVersion
-	unsigned char rootLength[IMAGE_LEN];            // 240-249: Size of rootfs
-        unsigned char tagId[TAGID_LEN];                 // 250-255: Identifies which type of tag this is, currently two-letter company code, and then three digits for version of broadcom code in which this tag was first introduced
-};
-
-struct bcm_tag_bc221 {
-	unsigned char tagVersion[TAGVER_LEN];           // 0-3: Version of the image tag
-	unsigned char sig_1[20];                        // 4-23: Company Line 1
-	unsigned char sig_2[14];                        // 24-37: Company Line 2
-	unsigned char chipid[6];                        // 38-43: Chip this image is for
-	unsigned char boardid[16];                      // 44-59: Board name
-	unsigned char big_endian[2];                    // 60-61: Map endianness -- 1 BE 0 LE
-	unsigned char totalLength[IMAGE_LEN];           // 62-71: Total length of image
-	unsigned char cfeAddress[ADDRESS_LEN];          // 72-83: Address in memory of CFE
-	unsigned char cfeLength[IMAGE_LEN];             // 84-93: Size of CFE
-	unsigned char flashImageStart[ADDRESS_LEN];     // 94-105: Address in memory of kernel (start of image)
-	unsigned char flashRootLength[IMAGE_LEN];       // 106-115: Size of rootfs + deadcode (web flash uses this + kernelLength to determine the size of the kernel+rootfs flash image)
- 	unsigned char kernelAddress[ADDRESS_LEN];       // 116-127: Address in memory of kernel
-	unsigned char kernelLength[IMAGE_LEN];          // 128-137: Size of kernel
-	unsigned char dualImage[2];                     // 138-139: Unused at present
-	unsigned char inactiveFlag[2];                  // 140-141: Unused at present
-        unsigned char rsa_signature[TAGINFO_LEN];       // 142-161: RSA Signature (unused at present; some vendors may use this)
-        unsigned char reserved5[2];                     // 162-163: Unused at present
-        unsigned char tagId[TAGID_LEN];                 // 164-169: Identifies which type of tag this is, currently two-letter company code, and then three digits for version of broadcom code in which this tag was first introduced
-        unsigned char rootAddress[ADDRESS_LEN];         // 170-181: Address in memory of rootfs partition
-        unsigned char rootLength[IMAGE_LEN];            // 182-191: Size of rootfs partition
-        unsigned char flashLayoutVer[4];                // 192-195: Version flash layout
-        unsigned char fskernelCRC[4];                   // 196-199: Guessed to be kernel CRC
-        unsigned char reserved4[16];                    // 200-215: Reserved area; unused at present
-	unsigned char imageCRC[4];                      // 216-219: CRC32 of images
-        unsigned char reserved2[12];                    // 220-231: Unused at present
-        unsigned char tagIdCRC[4];                      // 232-235: CRC32 to ensure validity of tagId
-        unsigned char headerCRC[4];                     // 236-239: CRC32 of header excluding tagVersion
-        unsigned char reserved3[16];                    // 240-255: Unused at present
-};
-
-struct bcm_tag_bc310 {
-	unsigned char tagVersion[4];                    // 0-3: Version of the image tag
-	unsigned char sig_1[20];                        // 4-23: Company Line 1
-	unsigned char sig_2[14];                        // 24-37: Company Line 2
-	unsigned char chipid[6];                        // 38-43: Chip this image is for
-	unsigned char boardid[16];                      // 44-59: Board name
-	unsigned char big_endian[2];                    // 60-61: Map endianness -- 1 BE 0 LE
-	unsigned char totalLength[IMAGE_LEN];           // 62-71: Total length of image
-	unsigned char cfeAddress[ADDRESS_LEN];          // 72-83: Address in memory of CFE
-	unsigned char cfeLength[IMAGE_LEN];             // 84-93: Size of CFE
-	unsigned char flashImageStart[ADDRESS_LEN];     // 94-105: Address in memory of kernel (start of image)
-	unsigned char flashRootLength[IMAGE_LEN];       // 106-115: Size of rootfs + deadcode (web flash uses this + kernelLength to determine the size of the kernel+rootfs flash image)
- 	unsigned char kernelAddress[ADDRESS_LEN];       // 116-127: Address in memory of kernel
-	unsigned char kernelLength[IMAGE_LEN];          // 128-137: Size of kernel
-	unsigned char dualImage[2];                     // 138-139: Unused at present
-	unsigned char inactiveFlag[2];                  // 140-141: Unused at present
-        unsigned char information1[TAGINFO_LEN];        // 142-161: Unused at present; Some vendors use this for optional information
-        unsigned char tagId[6];                         // 162-167: Identifies which type of tag this is, currently two-letter company code, and then three digits for version of broadcom code in which this tag was first introduced
-        unsigned char tagIdCRC[4];                      // 168-171: CRC32 to ensure validity of tagId
-        unsigned char rootAddress[ADDRESS_LEN];         // 172-183: Address in memory of rootfs partition
-        unsigned char rootLength[IMAGE_LEN];            // 184-193: Size of rootfs partition
-	unsigned char reserved1[22];                    // 193-215: Reserved area not in use
-	unsigned char imageCRC[4];                      // 216-219: CRC32 of images
-        unsigned char rootfsCRC[4];                     // 220-227: CRC32 of rootfs partition
-        unsigned char kernelCRC[4];                     // 224-227: CRC32 of kernel partition
-        unsigned char reserved2[8];                     // 228-235: Unused at present
-        unsigned char headerCRC[4];                     // 235-239: CRC32 of header excluding tagVersion
-        unsigned char reserved3[16];                    // 240-255: Unused at present
-};
-
-union bcm_tag {
-  struct bcm_tag_bccfe bccfe;
-  struct bcm_tag_bc300 bc300;
-  struct bcm_tag_ag306 ag306;
-  struct bcm_tag_bc221 bc221;
-  struct bcm_tag_bc310 bc310;
+struct bcm_tag {
+	char tagVersion[TAGVER_LEN];           // 0-3: Version of the image tag
+	char sig_1[SIG1_LEN];                  // 4-23: Company Line 1
+	char sig_2[SIG2_LEN];                  // 24-37: Company Line 2
+	char chipid[CHIPID_LEN];               // 38-43: Chip this image is for
+	char boardid[BOARDID_LEN];             // 44-59: Board name
+	char big_endian[ENDIANFLAG_LEN];       // 60-61: Map endianness -- 1 BE 0 LE
+	char totalLength[IMAGE_LEN];           // 62-71: Total length of image
+	char cfeAddress[ADDRESS_LEN];          // 72-83: Address in memory of CFE
+	char cfeLength[IMAGE_LEN];             // 84-93: Size of CFE
+	char flashImageStart[ADDRESS_LEN];     // 94-105: Address in memory of image start (kernel for OpenWRT, rootfs for stock firmware)
+	char rootLength[IMAGE_LEN];            // 106-115: Size of rootfs
+	char kernelAddress[ADDRESS_LEN];       // 116-127: Address in memory of kernel
+	char kernelLength[IMAGE_LEN];          // 128-137: Size of kernel
+	char dualImage[DUALFLAG_LEN];          // 138-139: Unused at present
+	char inactiveFlag[INACTIVEFLAG_LEN];   // 140-141: Unused at present
+        char rsa_signature[RSASIG_LEN];        // 142-161: RSA Signature (unused at present; some vendors may use this)
+	char information1[TAGINFO1_LEN];       // 162-191: Compilation and related information (not generated/used by OpenWRT)
+        char flashLayoutVer[FLASHLAYOUTVER_LEN];// 192-195: Version flash layout
+        char fskernelCRC[CRC_LEN];             // 196-199: kernel+rootfs CRC32
+	char information2[TAGINFO2_LEN];       // 200-215: Unused at present except Alice Gate where is is information
+	char imageCRC[CRC_LEN];                // 216-219: CRC32 of image less imagetag (kernel for Alice Gate)
+        char rootfsCRC[CRC_LEN];               // 220-223: CRC32 of rootfs partition
+        char kernelCRC[CRC_LEN];               // 224-227: CRC32 of kernel partition
+        char reserved1[8];                     // 228-235: Unused at present
+        char headerCRC[CRC_LEN];               // 236-239: CRC32 of header excluding tagVersion
+        char reserved2[16];                    // 240-255: Unused at present
 };
 
 #endif /* __BCM63XX_TAG_H */

target/linux/brcm63xx/image/Makefile

@@ -30,9 +30,9 @@ endef
 define Image/Build/CFE
 	# Generate the tagged image
 	$(STAGING_DIR_HOST)/bin/imagetag -i $(KDIR)/vmlinux.lzma.cfe -f $(KDIR)/root.$(1) \
-		-o $(BIN_DIR)/openwrt-$(2)-$(1)-$(6)-cfe.bin \
+		-o $(BIN_DIR)/openwrt-$(4)-$(1)-cfe.bin \
 		-b $(2) -c $(3) -e $(LOADADDR) -l $(LOADADDR) \
-	        -t $(4) -d "$(5)" $(7)
+	        -r "$(5)" $(6)
 #		-b $(2) -c $(3) -e $(KERNEL_ENTRY) -l $(LOADADDR)
 
 endef
@@ -40,17 +40,17 @@ endef
 define Image/Build/CFEAGPF
 	# Generate the tagged image
 	$(STAGING_DIR_HOST)/bin/imagetag -i $(KDIR)/vmlinux.lzma.cfe -f $(KDIR)/root.$(1) \
-		-o $(BIN_DIR)/openwrt-$(2)-$(1)-$(7)-cfe.bin \
+		-o $(BIN_DIR)/openwrt-$(5)-$(1)-cfe.bin \
 		-b $(2) -c $(3) -e $(LOADADDR) -l $(LOADADDR) \
-		-v 8 -m IMAGE -k 0x20000 -n $(4) -t $(5)
+		-v 8 -m IMAGE -k 0x20000 -n $(4)
 endef
 
 define Image/Build/RG100A
 	# Generate the tagged image
 	$(STAGING_DIR_HOST)/bin/imagetag -i $(KDIR)/vmlinux.lzma.cfe -f $(KDIR)/root.$(1) \
-		-o $(BIN_DIR)/openwrt-$(6)-$(1)-$(7)-cfe.bin \
+		-o $(BIN_DIR)/openwrt-$(5)-$(1)-cfe.bin \
 		-b $(2) -c $(3) -e $(LOADADDR) -l $(LOADADDR) \
-		-k 0x20000 -n $(4) -t $(5)
+		-k 0x20000 -n $(4)
 endef
 
 
@@ -105,84 +105,70 @@ endef
 define Image/Build
 	dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-root.$(1) bs=128k conv=sync
 	# Various routers
-	$(call Image/Build/CFE,$(1),96345GW2,6345,bccfe,,bccfe,)
-	$(call Image/Build/CFE,$(1),96345GW2,6345,bc221,,bc221,-y 5)
-	$(call Image/Build/CFE,$(1),96345GW2,6345,bc300,,bc300,)
-	$(call Image/Build/CFE,$(1),96345GW2,6345,bc310,OpenWRT-$(REVISION),bc310,)
-	$(call Image/Build/CFE,$(1),96348GW,6348,bccfe,,bccfe,)
-	$(call Image/Build/CFE,$(1),96348GW,6348,bc221,,bc221,-y 5)
+	$(call Image/Build/CFE,$(1),96345GW2,6345,96345GW2-generic)
+	$(call Image/Build/CFE,$(1),96345GW2,6345,96348GW2-bc221,,-y 5)
+	$(call Image/Build/CFE,$(1),96345GW2,6345,92345GW2-revision,OpenWRT-$(REVISION))
+	$(call Image/Build/CFE,$(1),96348GW,6348,96348GW-generic,,)
+	$(call Image/Build/CFE,$(1),96348GW,6348,96348GW-bc221,,-y 5)
+	$(call Image/Build/CFE,$(1),6338GW,6338,6338GW-generic,,)
+	$(call Image/Build/CFE,$(1),6338W,6338,6338W-generic,,)
+
 	# BT Voyager V210_BTR
-	$(call Image/Build/CFE,$(1),V210_BB,6348,bc221,,btvgr,-y 5)
+	$(call Image/Build/CFE,$(1),V210_BB,6348,BTV210_BTR,,-y 5)
 	# BT Voyager V210_ROI, V210_WB
-	$(call Image/Build/CFE,$(1),V210,6348,bc221,,btvgr,-y 5)
+	$(call Image/Build/CFE,$(1),V210,6348,BTV210_ROI_WB,,-y 5)
 	# BT Voyager V2091_BTR
-	$(call Image/Build/CFE,$(1),V2091_BB,6348,bc221,,btvgr,-y 5)
+	$(call Image/Build/CFE,$(1),V2091_BB,6348,BTV2091_BTR,,y 5)
 	# BT Voyager V2091_ROI, V2091_WB
-	$(call Image/Build/CFE,$(1),V2091,6348,bc221,,btvgr,-y 5)
+	$(call Image/Build/CFE,$(1),V2091,6348,BTV2091_ROI_WB,,-y 5)
 	# BT Voyager V220V, V220V_MGCP_BTR
-	$(call Image/Build/CFE,$(1),RTA1052V,6348,bc221,,btvgr,-y 5)
+	$(call Image/Build/CFE,$(1),RTA1052V,6348,BTV220V_MGCP_BTR,,-y 5)
 	# BT Voyager V2110, V2110_AA, V2110_ROI
-	$(call Image/Build/CFE,$(1),V2110,6348,bc221,,btvgr,-y 5)
+	$(call Image/Build/CFE,$(1),V2110,6348,BTV2110,,-y 5)
 	# BT Voyager V2500V, V2500V_SIP_CLUB, V2500V_AA
-	$(call Image/Build/CFE,$(1),V2500V_BB,6348,bc221,,btvgr,-y 5)
+	$(call Image/Build/CFE,$(1),V2500V_BB,6348,BTV2500V,,-y 5)
 	# RTA1025W_16 (numerous routers)
-	$(call Image/Build/CFE,$(1),RTA1025W_16,6348,bc221,,btrta,-y 5)
+	$(call Image/Build/CFE,$(1),RTA1025W_16,6348,RTA1025W_16,,-y 5)
 	# Tecom GW6000
-	$(call Image/Build/CFE,$(1),96348GW,6348,bc300,,bc300,)
+	$(call Image/Build/CFE,$(1),96348GW,6348,GW6000)
 	# Tecom GW6200
-	$(call Image/Build/CFE,$(1),96348GW,6348,bc310,$(shell printf '\x99'),gw6200)
+	$(call Image/Build/CFE,$(1),96348GW,6348,GW6200,$(shell printf '\x99'))
 	# Neufbox4
-	$(call Image/Build/CFE,$(1),96358VW,6358,bccfe,,bccfe)
-	$(call Image/Build/CFE,$(1),96358VW,6358,bc310,OpenWRT-$(REVISION),nb4)
+	$(call Image/Build/CFE,$(1),96358VW,6358,NEUFBOX4,OpenWRT-$(REVISION))
 	# Comtrend 536, 5621
-	$(call Image/Build/CFE,$(1),96348GW-11,6348,bccfe,,bccfe)
-	$(call Image/Build/CFE,$(1),96348GW-11,6348,bc300,,bc300)
-	# TP-Link 8900GB
-	$(call Image/Build/CFE,$(1),96348GW-11,6348,bc310,$(shell printf 'PRID\x89\x10\x00\x02'),td8900GB)
+	$(call Image/Build/CFE,$(1),96348GW-11,6348,CT536_CT5621)
 	# Davolink DV201AMR
 	$(call Image/Build/CFEOLD,$(1),DV201AMR,6348)
 	# USR 9108
-	$(call Image/Build/CFE,$(1),96348GW-A,6348,bccfe,,bccfe)
-	$(call Image/Build/CFE,$(1),96348GW-A,6348,bc300,,bc300)
+	$(call Image/Build/CFE,$(1),96348GW-A,6348,USR9108)
 	# NetGear DG834GT, DG834PN
-	$(call Image/Build/CFE,$(1),96348GW-10,6348,bccfe,,bccfe)
-	$(call Image/Build/CFE,$(1),96348GW-10,6348,bc300,,bc300)
+	$(call Image/Build/CFE,$(1),96348GW-10,6348,DG834GT_DG834PN)
 	# Belkin f5d7633
-	$(call Image/Build/CFE,$(1),96348GW-10,6348,bc310,,bc310)
+	$(call Image/Build/CFE,$(1),96348GW-10,6348,F5D7633)
 	# D-Link DSL-2640B
-	$(call Image/Build/CFE,$(1),D-4P-W,6348,bc310,,bc310)
+	$(call Image/Build/CFE,$(1),D-4P-W,6348,DSL2640B)
+	# D-Link DSL-2740B
+	$(call Image/Build/CFE,$(1),96358GW,6358,DSL2740B)
 
 	# TP-Link TD-8810A, TD-8810B, TD-8811A, TD-8811B
-	$(call Image/Build/CFE,$(1),8L-2M-8M,6338,bccfe,,bccfe)
-	$(call Image/Build/CFE,$(1),8L-2M-8M,6338,bc300,,bc300)
-
-	# Generic 6338 images
-	$(call Image/Build/CFE,$(1),6338GW,6338,bccfe,,bccfe)
-	$(call Image/Build/CFE,$(1),6338GW,6338,bc221,,bc221)
-	$(call Image/Build/CFE,$(1),6338GW,6338,bc300,,bc300)
-	$(call Image/Build/CFE,$(1),6338GW,6338,bc310,,bc310)
-	$(call Image/Build/CFE,$(1),6338W,6338,bccfe,,bccfe)
-	$(call Image/Build/CFE,$(1),6338W,6338,bc221,,bc221)
-	$(call Image/Build/CFE,$(1),6338W,6338,bc300,,bc300)
-	$(call Image/Build/CFE,$(1),6338W,6338,bc310,,bc310)
+	$(call Image/Build/CFE,$(1),8L-2M-8M,6338,TP8810_8811)
+	# TP-Link 8900GB
+	$(call Image/Build/CFE,$(1),96348GW-11,6348,TD8900GB,$(shell printf 'PRID\x89\x10\x00\x02'))
 
 	# Sagem F@ST2404
-	$(call Image/Build/CFE,$(1),F@ST2404,6348,bccfe,,bccfe)
-	$(call Image/Build/CFE,$(1),F@ST2404,6348,bc300,,bc300)
-	$(call Image/Build/CFE,$(1),F@ST2404,6348,bc310,OpenWRT-$(REVISION),bc310)
+	$(call Image/Build/CFE,$(1),F@ST2404,6348,F@ST2404-cfe)
+	$(call Image/Build/CFE,$(1),F@ST2404,6348,F@ST2404,OpenWRT-$(REVISION))
 	# Inventel Livebox
 	$(call Image/Build/RedBoot,livebox)
-	# D-Link DSL-2740B
-	$(call Image/Build/CFE,$(1),96358GW,6358,bc310,,dsl2740b)
 	# Pirelli Alice Gate VoIP 2 Plus Wi-Fi AGPF-S0
-	$(call Image/Build/CFEAGPF,$(1),AGPF-S0,6358,0x20000,bccfe,,bccfe)
-	$(call Image/Build/CFEAGPF,$(1),AGPF-S0,6358,0x20000,ag306,,agv2+w)
+	$(call Image/Build/CFEAGPF,$(1),AGPF-S0,6358,0x20000,AGV2+W-cfe)
+	$(call Image/Build/CFEAGPF,$(1),AGPF-S0,6358,0x20000,AGV2+W)
 	# Pirelli A226G
-	$(call Image/Build/CFEAGPF,$(1),DWV-S0,6358,0x10000,bccfe,,bccfe)
-	$(call Image/Build/CFEAGPF,$(1),DWV-S0,6358,0x10000,ag306,DWV_96358,a226g)
+	$(call Image/Build/CFEAGPF,$(1),DWV-S0,6358,0x10000,A226G-cfe)
+	$(call Image/Build/CFEAGPF,$(1),DWV-S0,6358,0x10000,A226G)
 	
 	# RG100A,DB120 etc.
-	$(call Image/Build/RG100A,$(1),96358VW2,6358,0x20000,bc310,rg100a,bc310)
+	$(call Image/Build/RG100A,$(1),96358VW2,6358,0x20000,RG100A_DB120)
 
 endef
 

target/linux/brcm63xx/image/README.images-bcm63xx

@@ -16,6 +16,11 @@ Images flashable using cfe are labelled openwrt-<board>-<filesystem>-cfe.bin
 The imagetags for tftp/ftp flashing is based on Broadcom 3.00-3.04 imagetags
 and is known to be correct as the source code GPL and is available for reading.
 
+Broadcom code 2.21 is based on the BT Voyager firmware image I looked at.  It
+may in fact be BT Voyager-specific.  2.21 is actually more difficult to deal
+with the imagetag from 3.00 as it has three different CRC calculations in
+addtition to the header CRC.
+
 Broadcom 3.00-3.02 flashing has been tested on Comtrend CT-5261, CT-536 and 
 Tecom GW6000, and is the version of the flashing that was present before the
 imagetags were split by broadcom code version (early June 2009)
@@ -27,16 +32,11 @@ this author (Daniel Dickinson) has seen is the Alice Gate (Pirelli) firmware
 which is known to be different due to vendor (Pirelli) modifications to the
 Broadcom code.
 
-Broadcom 3.08 introduced changes to the imagetag to deal with TR69 (a remote
-router management system developed by the DSL Forum).  The version we are
-using as 3.08 is based on the BT Voyager firmware image I looked at.  It may
-in fact be BT Voyager-specific, and may in fact not be 3.08, but modified 3.06
-and not apply to all 3.08 versions.
-
 Broadcom 3.10 uses an imagetag that is believed to apply to all 3.10 and 3.12
-versions, and has been tested on the Tecom GW6200.  It is similar to 3.08.  
-There is a field for vendor-specific information, that at least in some cases
-is not optional.  It is based on the hexedit of a neufbox4 firmware image, the
+versions, and has been tested on the Tecom GW6200.  This version introdec changes to
+the imagetag to deal with TR69 (a remote rouer management system developed by the
+DSL forum).  There is a field for vendor-specific information, that at least in some
+cases is not optional.  It is based on the hexedit of a neufbox4 firmware image, the
 information in https://dev.openwrt.org/ticket/4987, and the hexedit of a Tecom
 GW6200 image.
 
@@ -44,43 +44,41 @@ Some boards share the same tag format, but require vendor-specific fields in
 the board.  In that case the tagid is shared, but the filename of the generated
 image reflects the router for which the image was created.
 
-router        |method| codever |tagid |filename
-+-------------+------+---------+------+----------------------------------------
-|any          |cfe   |   any   |bccfe |openwrt-<board>-<fs>-bccfe-cfe.bin
-|any          |t/ftp |   any   |bc300 |openwrt-<board>-<fs>-bc300-cfe.bin
-|             |web   |3.00-3.06|bc300 |openwrt-<board>-<fs>-bc300-cfe.bin
-|             |web   |3.10-3.12|bc310 |openwrt-<board>-<fs>-bc310-cfe.bin
-|AGVoIP2+WiFi |web   |alice3.06|ag306 |openwrt-AGPF-S0-<fs>-agv2+w-cfe.bin
-|CT536        |web   |3.02     |bc300 |openwrt-96348GW-11-<fs>-bc300-cfe.bin
-|CT5621       |web   |3.02     |bc300 |openwrt-96348GW-11-<fs>-bc300-cfe.bin
-|DG834GT      |web   |3.02     |bc300 |openwrt-96348GW-10-<fs>-bc300-cfe.bin
-|DG834PN      |web   |3.02     |bc300 |openwrt-96348GW-10-<fs>-bc300-cfe.bin
-|DSL-2640B    |web   |3.10     |bc310 |openwrt-D-4P-W-<fs>-bc310-cfe.bin
-|DSL-2740B    |web   |3.10     |bc310 |openwrt-96358GW-<fs>-dsl2740b-cfe.bin
-|F5D7633      |web   |3.10     |bc310 |openwrt-96348GW-10-<fs>-bc310-cfe.bin
-|F@ST2404     |web   |?        |bc300 |openwrt-F@ST2404-<fs>-bc300-cfe.bin
-|F@ST2404     |web   |?        |bc310 |openwrt-F@ST2404-<fs>-bc310-cfe.bin
-|GW6000       |web   |3.00     |bc300 |openwrt-96348GW-<fs>-bc300-cfe.bin
-|GW6200       |web   |3.10     |bc310 |openwrt-96348GW-<fs>-gw6200-cfe.bin
-|Neufbox4     |web   |3.12     |bc310 |openwrt-96358VW-<fs>-nb4-cfe.bin
-|TD8810A      |web   |3.06     |bc300 |openwrt-8L-2M-8M-<fs>-bc306-cfe.bin
-|TD8810B      |web   |3.06     |bc300 |openwrt-8L-2M-8M-<fs>-bc306-cfe.bin
-|TD8811A      |web   |3.06     |bc300 |openwrt-8L-2M-8M-<fs>-bc306-cfe.bin
-|TD8811B      |web   |3.06     |bc300 |openwrt-8L-2M-8M-<fs>-bc306-cfe.bin
-|TD8900GB     |web   |3.06     |bc300 |openwrt-96348GW-11-<fs>-td8900gb-cfe.bin
-|USR9108      |web   |?        |bc300 |openwrt-96348GW-A-<fs>-bc300-cfe.bin
-|V2091_BTR    |web   |2.21     |bc221 |openwrt-V2091_BB-<fs>-btvgr-cfe.bin
-|V2091_ROI    |web   |2.21     |bc221 |openwrt-V2091-<fs>-btvgr-cfe.bin
-|V2091_WB     |web   |2.21     |bc221 |openwrt-V2091-<fs>-btvgr-cfe.bin
-|V210_BTR     |web   |2.21     |bc221 |openwrt-V210_BB-<fs>-btvgr-cfe.bin
-|V210_ROI     |web   |2.21     |bc221 |openwrt-V210-<fs>-btvgr-cfe.bin
-|V210_WB      |web   |2.21     |bc221 |openwrt-V210-<fs>-btvgr-cfe.bin
-|V2110        |web   |2.21     |bc221 |openwrt-V2110-<fs>-btvgr-cfe.bin
-|V2110_AA     |web   |2.21     |bc221 |openwrt-V2110-<fs>-btvgr-cfe.bin
-|V2110_ROI    |web   |2.21     |bc221 |openwrt-V2110-<fs>-btvgr-cfe.bin
-|V2500V       |web   |2.21     |bc221 |openwrt-V2500V_BB-<fs>-btvgr-cfe.bin
-|V2500V_AA    |web   |2.21     |bc221 |openwrt-V2500V_BB-<fs>-btvgr-cfe.bin
-|V2500V_SIP_CLUB |web|2.21     |bc221 |openwrt-V2500V_BB-<fs>-btvgr-cfe.bin
+router        |method       | codever |filename
++-------------+-------------+---------+---------------------------------------
+|any          |cfe+most web |   any   |openwrt-<board>-<fs>-cfe.bin
+|AGVoIP2+WiFi |cfe          |alice3.06|openwrt-AGV2+W-cfe-<fs>-cfe.bin
+|AGVoIP2+WiFi |web          |alice3.06|openwrt-AGV2+W-cfe-<fs>-cfe.bin
+|CT536        |web          |3.02     |openwrt-CT536_CT5621-<fs>-cfe.bin
+|CT5621       |web          |3.02     |openwrt-CT536_CT5621-<fs>-cfe.bin
+|DG834GT      |web          |3.02     |openwrt-DG834GT_DG834PN-<fs>-cfe.bin
+|DG834PN      |web          |3.02     |openwrt-DG834GT_DG834PN-<fs>-cfe.bin
+|DSL-2640B    |web          |3.10     |openwrt-DSL2640B-<fs>-cfe.bin
+|DSL-2740B    |web          |3.10     |openwrt-DSL2670B-<fs>-cfe.bin
+|F5D7633      |web          |3.10     |openwrt-F5D7633-<fs>-cfe.bin
+|F@ST2404     |web          |3.0X?    |openwrt-F@ST2404-cfe-<fs>-cfe.bin
+|F@ST2404     |web          |3.1X?    |openwrt-F@ST2404-<fs>-cfe.bin
+|GW6000       |web          |3.00     |openwrt-GW6000-<fs>-cfe.bin
+|GW6200       |web          |3.10     |openwrt-GW6200-<fs>-cfe.bin
+|Neufbox4     |web          |3.12     |openwrt-NEUFBOX4-<fs>-cfe.bin
+|TD8810A      |web          |3.06     |openwrt-TD8810-<fs>-cfe.bin
+|TD8810B      |web          |3.06     |openwrt-TD8810-<fs>-cfe.bin
+|TD8811A      |web          |3.06     |openwrt-TD8811-<fs>-cfe.bin
+|TD8811B      |web          |3.06     |openwrt-TD881-<fs>-cfe.bin
+|TD8900GB     |web          |3.06     |openwrt-TD8900DB<fs>-cfe.bin
+|USR9108      |web          |3.0X?    |openwrt-USR9108-<fs>-cfe.bin
+|V2091_BTR    |web          |2.21     |openwrt-V2091_BTR-<fs>-cfe.bin
+|V2091_ROI    |web          |2.21     |openwrt-V2091-<fs>-cfe.bin
+|V2091_WB     |web          |2.21     |openwrt-V2091-<fs>-cfe.bin
+|V210_BTR     |web          |2.21     |openwrt-V210_BTR-<fs>-cfe.bin
+|V210_ROI     |web          |2.21     |openwrt-V210-ROI_WB<fs>-cfe.bin
+|V210_WB      |web          |2.21     |openwrt-V210-ROI_WB<fs>-cfe.bin
+|V2110        |web          |2.21     |openwrt-V2110-<fs>-cfe.bin
+|V2110_AA     |web          |2.21     |openwrt-V2110-<fs>-cfe.bin
+|V2110_ROI    |web          |2.21     |openwrt-V2110-<fs>-cfe.bin
+|V2500V       |web          |2.21     |openwrt-V2500V<fs>-cfe.bin
+|V2500V_AA    |web          |2.21     |openwrt-V2500V-<fs>-cfe.bin
+|V2500V_SIP_CLUB |web       |2.21     |openwrt-V2500V-<fs>-cfe.bin
 
 Old imagetag routers
 --------------------
@@ -126,3 +124,4 @@ TP-Link			   |TD-W8900GB				      |3.06
 Tecom                      |GW6000                                    |3.00
 Tecom                      |GW6200                                    |3.10
 USR			   |9108				      |?
+

target/linux/brcm63xx/patches-2.6.32/040-bcm963xx_flashmap.patch

@@ -11,9 +11,11 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
  drivers/mtd/redboot.c     |   13 ++++++++++---
  3 files changed, 18 insertions(+), 3 deletions(-)
 
---- a/drivers/mtd/maps/Kconfig
-+++ b/drivers/mtd/maps/Kconfig
-@@ -259,6 +259,13 @@ config MTD_ALCHEMY
+Index: linux-2.6.32.10/drivers/mtd/maps/Kconfig
+===================================================================
+--- linux-2.6.32.10.orig/drivers/mtd/maps/Kconfig	2010-03-29 06:35:59.987293878 -0400
++++ linux-2.6.32.10/drivers/mtd/maps/Kconfig	2010-03-29 06:37:14.968545954 -0400
+@@ -259,6 +259,13 @@
  	help
  	  Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards
  
@@ -27,9 +29,11 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
  config MTD_DILNETPC
  	tristate "CFI Flash device mapped on DIL/Net PC"
  	depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN
---- a/drivers/mtd/redboot.c
-+++ b/drivers/mtd/redboot.c
-@@ -39,7 +39,7 @@ static inline int redboot_checksum(struc
+Index: linux-2.6.32.10/drivers/mtd/redboot.c
+===================================================================
+--- linux-2.6.32.10.orig/drivers/mtd/redboot.c	2010-03-29 06:36:00.017292877 -0400
++++ linux-2.6.32.10/drivers/mtd/redboot.c	2010-03-29 06:37:14.968545954 -0400
+@@ -39,7 +39,7 @@
  	return 1;
  }
  
@@ -38,7 +42,7 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
                               struct mtd_partition **pparts,
                               unsigned long fis_origin)
  {
-@@ -162,6 +162,14 @@ static int parse_redboot_partitions(stru
+@@ -162,6 +162,14 @@
  		goto out;
  	}
  
@@ -53,7 +57,7 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
  	for (i = 0; i < numslots; i++) {
  		struct fis_list *new_fl, **prev;
  
-@@ -184,9 +192,8 @@ static int parse_redboot_partitions(stru
+@@ -184,9 +192,8 @@
  		new_fl->img = &buf[i];
                  if (fis_origin) {
                          buf[i].flash_base -= fis_origin;
@@ -64,16 +68,20 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
  
  		/* I'm sure the JFFS2 code has done me permanent damage.
  		 * I now think the following is _normal_
---- a/drivers/mtd/maps/Makefile
-+++ b/drivers/mtd/maps/Makefile
-@@ -61,3 +61,4 @@ obj-$(CONFIG_MTD_BFIN_ASYNC)	+= bfin-asy
+Index: linux-2.6.32.10/drivers/mtd/maps/Makefile
+===================================================================
+--- linux-2.6.32.10.orig/drivers/mtd/maps/Makefile	2010-03-29 06:35:59.947294290 -0400
++++ linux-2.6.32.10/drivers/mtd/maps/Makefile	2010-03-29 06:37:14.968545954 -0400
+@@ -61,3 +61,4 @@
  obj-$(CONFIG_MTD_RBTX4939)	+= rbtx4939-flash.o
  obj-$(CONFIG_MTD_VMU)		+= vmu-flash.o
  obj-$(CONFIG_MTD_GPIO_ADDR)	+= gpio-addr-flash.o
 +obj-$(CONFIG_MTD_BCM963XX)	+= bcm963xx-flash.o
---- /dev/null
-+++ b/drivers/mtd/maps/bcm963xx-flash.c
-@@ -0,0 +1,399 @@
+Index: linux-2.6.32.10/drivers/mtd/maps/bcm963xx-flash.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.32.10/drivers/mtd/maps/bcm963xx-flash.c	2010-03-29 13:33:58.797288897 -0400
+@@ -0,0 +1,266 @@
 +/*
 + * Copyright (C) 2006-2008  Florian Fainelli <florian@openwrt.org>
 + * 			    Mike Albon <malbon@openwrt.org>
@@ -119,179 +127,46 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
 +       .bankwidth	= BUSWIDTH,
 +};
 +
-+static struct tagiddesc_t tagidtab[NUM_TAGID] = TAGID_DEFINITIONS;
-+
-+static uint32_t tagcrc32tab[256] = {
-+	0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
-+	0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
-+	0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
-+	0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
-+	0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
-+	0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
-+	0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
-+	0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
-+	0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
-+	0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
-+	0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
-+	0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
-+	0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
-+	0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
-+	0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
-+	0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
-+	0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
-+	0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
-+	0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
-+	0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
-+	0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
-+	0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
-+	0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
-+	0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
-+	0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
-+	0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
-+	0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
-+	0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
-+	0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
-+	0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
-+	0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
-+	0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
-+};
-+
-+static uint32_t tagcrc32(uint32_t crc, uint8_t *data, size_t len)
-+{
-+	while (len--)
-+		crc = (crc >> 8) ^ tagcrc32tab[(crc ^ *data++) & 0xFF];
-+
-+	return crc;
-+}
 +
 +static int parse_cfe_partitions( struct mtd_info *master, struct mtd_partition **pparts)
 +{
 +	int nrparts = 3, curpart = 0; /* CFE,NVRAM and global LINUX are always present. */
-+	union bcm_tag *buf;
++	struct bcm_tag *buf;
 +	struct mtd_partition *parts;
 +	int ret;
 +	size_t retlen;
 +	unsigned int rootfsaddr, kerneladdr, spareaddr;
 +	unsigned int rootfslen, kernellen, sparelen, totallen;
-+	unsigned char *tagid;
 +	int namelen = 0;
 +	int i;
-+	uint32_t tagidcrc;
-+	uint32_t calctagidcrc;
-+        bool tagid_match = false;
 +	char *boardid;
 +        char *tagversion;
-+	char *matchtagid;
 +
 +	/* Allocate memory for buffer */
-+	buf = vmalloc(sizeof(union bcm_tag));
++	buf = vmalloc(sizeof(struct bcm_tag));
 +	if (!buf)
 +		return -ENOMEM;
 +
 +	/* Get the tag */
-+	ret = master->read(master,master->erasesize,sizeof(union bcm_tag), &retlen, (void *)buf);
-+	if (retlen != sizeof(union bcm_tag)){
++	ret = master->read(master,master->erasesize,sizeof(struct bcm_tag), &retlen, (void *)buf);
++	if (retlen != sizeof(struct bcm_tag)){
 +		vfree(buf);
 +		return -EIO;
 +	}
 +
-+	/* tagId isn't in the same location, so we check each tagid against the
-+         * tagid CRC.  If the CRC is valid we have found the right tag and so
-+         * use that tag
-+         */
++	sscanf(buf->kernelAddress, "%u", &kerneladdr);
++	sscanf(buf->kernelLength, "%u", &kernellen);
++	sscanf(buf->totalLength, "%u", &totallen);
++	tagversion = &(buf->tagVersion[0]);
++	boardid = &(buf->boardid[0]);
 +
-+	for (i = 0; i < NUM_TAGID; i++) {
-+	  switch(i) {
-+	  case 0:
-+	    matchtagid = "bccfe";
-+	    tagid = &(buf->bccfe.tagId[0]);
-+	    sscanf(buf->bccfe.rootAddress,"%u", &rootfsaddr);
-+	    sscanf(buf->bccfe.rootLength, "%u", &rootfslen);
-+	    sscanf(buf->bccfe.kernelAddress, "%u", &kerneladdr);
-+	    sscanf(buf->bccfe.kernelLength, "%u", &kernellen);
-+	    sscanf(buf->bccfe.totalLength, "%u", &totallen);
-+	    tagidcrc = *(uint32_t *)&(buf->bccfe.tagIdCRC[0]);
-+	    tagversion = &(buf->bccfe.tagVersion[0]);
-+	    boardid = &(buf->bccfe.boardid[0]);
-+	    break;
-+	  case 1:
-+	    matchtagid = "bc300";
-+	    tagid = &(buf->bc300.tagId[0]);
-+	    sscanf(buf->bc300.rootAddress,"%u", &rootfsaddr);
-+	    sscanf(buf->bc300.rootLength, "%u", &rootfslen);
-+	    sscanf(buf->bc300.kernelAddress, "%u", &kerneladdr);
-+	    sscanf(buf->bc300.kernelLength, "%u", &kernellen);
-+	    sscanf(buf->bc300.totalLength, "%u", &totallen);
-+	    tagidcrc = *(uint32_t *)&(buf->bc300.tagIdCRC[0]);
-+	    tagversion = &(buf->bc300.tagVersion[0]);
-+	    boardid = &(buf->bc300.boardid[0]);
-+	    break;
-+	  case 2:
-+	    matchtagid = "ag306";
-+	    tagid = &(buf->ag306.tagId[0]);
-+	    sscanf(buf->ag306.rootAddress,"%u", &rootfsaddr);
-+	    sscanf(buf->ag306.rootLength, "%u", &rootfslen);
-+	    sscanf(buf->ag306.kernelAddress, "%u", &kerneladdr);
-+	    sscanf(buf->ag306.kernelLength, "%u", &kernellen);
-+	    sscanf(buf->ag306.totalLength, "%u", &totallen);
-+	    tagidcrc = *(uint32_t *)&(buf->ag306.tagIdCRC[0]);
-+	    tagversion = &(buf->ag306.tagVersion[0]);
-+	    boardid = &(buf->ag306.boardid[0]);
-+	    break;
-+	  case 3:
-+	    matchtagid = "bc221";
-+	    tagid = &(buf->bc221.tagId[0]);
-+	    sscanf(buf->bc221.rootAddress,"%u", &rootfsaddr);
-+	    sscanf(buf->bc221.rootLength, "%u", &rootfslen);
-+	    sscanf(buf->bc221.kernelAddress, "%u", &kerneladdr);
-+	    sscanf(buf->bc221.kernelLength, "%u", &kernellen);
-+	    sscanf(buf->bc221.totalLength, "%u", &totallen);
-+	    tagidcrc = *(uint32_t *)&(buf->bc221.tagIdCRC[0]);
-+	    tagversion = &(buf->bc221.tagVersion[0]);
-+	    boardid = &(buf->bc221.boardid[0]);
-+	    break;
-+	  case 4:
-+	    matchtagid = "bc310";
-+	    tagid = &(buf->bc310.tagId[0]);
-+	    sscanf(buf->bc310.rootAddress,"%u", &rootfsaddr);
-+	    sscanf(buf->bc310.rootLength, "%u", &rootfslen);
-+	    sscanf(buf->bc310.kernelAddress, "%u", &kerneladdr);
-+	    sscanf(buf->bc310.kernelLength, "%u", &kernellen);
-+	    sscanf(buf->bc310.totalLength, "%u", &totallen);
-+	    tagidcrc = *(uint32_t *)&(buf->bc310.tagIdCRC[0]);
-+	    tagversion = &(buf->bc310.tagVersion[0]);
-+	    boardid = &(buf->bc310.boardid[0]);
-+	    break;
-+	  }
-+	  if (strncmp(tagid, matchtagid, TAGID_LEN) != 0) {
-+	    continue;
-+	  }
++	printk(KERN_INFO PFX "CFE boot tag found with version %s and board type %s\n",tagversion, boardid);
 +
-+	  calctagidcrc = htonl(tagcrc32(IMAGETAG_CRC_START, tagid, TAGID_LEN));
-+	  if (tagidcrc == calctagidcrc) {
-+	    tagid_match = true;
-+	    break;
-+	  }
-+	}
-+
-+	if (!tagid_match) {
-+	    tagid = "bcram";
-+	    sscanf(buf->bccfe.rootAddress,"%u", &rootfsaddr);
-+	    sscanf(buf->bccfe.rootLength, "%u", &rootfslen);
-+	    sscanf(buf->bccfe.kernelAddress, "%u", &kerneladdr);
-+	    sscanf(buf->bccfe.kernelLength, "%u", &kernellen);
-+	    sscanf(buf->bccfe.totalLength, "%u", &totallen);
-+	    tagidcrc = *(uint32_t *)&(buf->bccfe.tagIdCRC[0]);
-+	    tagversion = &(buf->bccfe.tagVersion[0]);
-+	    boardid = &(buf->bccfe.boardid[0]);
-+	}
-+
-+	printk(KERN_INFO PFX "CFE boot tag found with version %s, board type %s, and tagid %s.\n",tagversion,boardid,tagid);
-+
-+	rootfsaddr = rootfsaddr - EXTENDED_SIZE;
 +	kerneladdr = kerneladdr - EXTENDED_SIZE;
-+	spareaddr = roundup(totallen,master->erasesize) + master->erasesize;
++	rootfsaddr = kerneladdr + kernellen;
++	spareaddr = roundup(totallen, master->erasesize) + master->erasesize;
 +	sparelen = master->size - spareaddr - master->erasesize;
++	rootfslen = spareaddr - rootfsaddr;
 +
 +	/* Determine number of partitions */
 +	namelen = 8;
@@ -342,9 +217,9 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
 +	parts[curpart].name = "linux";
 +	parts[curpart].offset = parts[0].size;
 +	parts[curpart].size = master->size - parts[0].size - parts[3].size;
-+ 
++
 +	for (i = 0; i < nrparts; i++)
-+		printk(KERN_INFO PFX "Partition %d is %s offset %lx and length %lx\n", i, parts[i].name, parts[i].offset, parts[i].size);
++		printk(KERN_INFO PFX "Partition %d is %s offset %lx and length %lx\n", i, parts[i].name, (long unsigned int)(parts[i].offset), (long unsigned int)(parts[i].size));
 +
 + 	printk(KERN_INFO PFX "Spare partition is %x offset and length %x\n", spareaddr, sparelen);
 +	*pparts = parts;
@@ -375,7 +250,7 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
 +	char *part_type;
 +	struct resource *r;
 +
-+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 
++	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 +	bcm963xx_map.phys = r->start;
 +	bcm963xx_map.size = (r->end - r->start) + 1;
 +	bcm963xx_map.virt = ioremap(r->start, r->end - r->start + 1);
@@ -473,9 +348,11 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
 +MODULE_DESCRIPTION("Broadcom BCM63xx MTD partition parser/mapping for CFE and RedBoot");
 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 +MODULE_AUTHOR("Mike Albon <malbon@openwrt.org>");
---- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
-+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -722,20 +722,6 @@ static int board_get_mac_address(u8 *mac
+Index: linux-2.6.32.10/arch/mips/bcm63xx/boards/board_bcm963xx.c
+===================================================================
+--- linux-2.6.32.10.orig/arch/mips/bcm63xx/boards/board_bcm963xx.c	2010-03-29 06:35:59.927292275 -0400
++++ linux-2.6.32.10/arch/mips/bcm63xx/boards/board_bcm963xx.c	2010-03-29 06:37:35.178541753 -0400
+@@ -722,20 +722,6 @@
  	return 0;
  }
  
@@ -496,7 +373,7 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
  static struct resource mtd_resources[] = {
  	{
  		.start		= 0,	/* filled at runtime */
-@@ -745,12 +731,9 @@ static struct resource mtd_resources[] =
+@@ -745,12 +731,9 @@
  };
  
  static struct platform_device mtd_dev = {

target/linux/generic-2.4/patches/629-netlink_types_h.patch

@@ -9,3 +9,14 @@
  #define NETLINK_ROUTE		0	/* Routing/device hook				*/
  #define NETLINK_SKIP		1	/* Reserved for ENskip  			*/
  #define NETLINK_USERSOCK	2	/* Reserved for user mode socket protocols 	*/
+--- a/include/linux/filter.h	2010-02-01 22:04:46.000000000 +0100
++++ b/include/linux/filter.h	2010-03-29 20:57:08.000000000 +0200
+@@ -5,6 +5,8 @@
+ #ifndef __LINUX_FILTER_H__
+ #define __LINUX_FILTER_H__
+ 
++#include <linux/types.h>
++
+ /*
+  * Current version of the filter code architecture.
+  */

target/linux/generic-2.6/config-2.6.32

@@ -550,6 +550,7 @@ CONFIG_EXPERIMENTAL=y
 # CONFIG_EXT4_DEBUG is not set
 # CONFIG_EXT4DEV_FS is not set
 # CONFIG_EXT4_FS is not set
+# CONFIG_EXT4_FS_XATTR is not set
 CONFIG_EXTRA_FIRMWARE=""
 CONFIG_EXTRA_TARGETS=""
 # CONFIG_EZX_PCAP is not set

target/linux/ifxmips/Makefile

@@ -16,7 +16,8 @@ LINUX_VERSION:=2.6.30.10
 CFLAGS=-Os -pipe -mips32r2 -mtune=mips32r2 -funit-at-a-time
 
 include $(INCLUDE_DIR)/target.mk
-DEFAULT_PACKAGES+=kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl ifxmips-dsl-api ifxmips-dsl-control
+DEFAULT_PACKAGES+=uboot-lantiq
+#kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl ifxmips-dsl-api ifxmips-dsl-control ifx-tapidemo
 
 define Target/Description
 	Build firmware images for Infineon Mips Controllers

target/linux/ifxmips/extract.py

@@ -0,0 +1,9 @@
+#!/usr/bin/python
+from sys import stdin, stdout
+while True:
+	c = stdin.read(2)
+	if len(c) < 2:
+		break
+	n1, n2 = ord(c[0]), ord(c[1])
+	stdout.write(chr(((n2 & 15) << 4) + ((n2 & 240) >> 4)))
+	stdout.write(chr(((n1 & 15) << 4) + ((n1 & 240) >> 4)))

target/linux/ifxmips/extract.sh

@@ -0,0 +1,42 @@
+#!/bin/sh
+
+DIR="$1/"
+FILE="$1/$2"
+
+echo "This tool downloads the arcor a800 firmware release and extracts the voip firmware for the danube."
+echo "Please only do so if it is legal in your country"
+
+[ ! -f ${FILE} ] && {
+	echo ${FILE} is missing
+	exit 1
+}
+
+[ -f ${DIR}/ifxmips_fw_decode.tar.bz2 -a ! -f ${DIR}voip_coef.bin ] && {
+	[ ! -f ${DIR}decode_ifx_fw ] && {
+		tar xjf ${DIR}ifxmips_fw_decode.tar.bz2 ifxmips_fw_decode/decode.c -O > ${DIR}decode.c
+		gcc -o ${DIR}decode_ifx_fw ${DIR}decode.c
+	}
+	[ ! -f ${DIR}voip_coef.lzma ] && {
+		${DIR}decode_ifx_fw $FILE ${DIR}voip_coef.lzma
+	}
+	lzma d ${DIR}voip_coef.lzma ${DIR}voip_coef.bin
+}
+[ ! -f ${DIR}dsl_a.bin ] && {
+	dd if=${FILE} of=${DIR}dsl1.lzma bs=1 skip=2168832 count=150724
+	lzma d ${DIR}dsl2.lzma ${DIR}dsl_a.bin
+}
+
+[ ! -f ${DIR}dsl_b.bin ] && {
+	dd if=${FILE} of=${DIR}dsl2.lzma bs=1 skip=2320384 count=148343
+	lzma d ${DIR}dsl1.lzma ${DIR}dsl_b.bin
+}
+
+[ ! -f ${DIR}voip.bin ] && {
+	dd if=${FILE} of=${DIR}voip.lzma bs=1 skip=2468864 count=452105
+	lzma d ${DIR}voip.lzma ${DIR}voip.bin
+}
+exit 0
+
+# get lzma offsets
+# hexdump -C arcor_A800_452CPW_FW_1.02.206\(20081201\).bin | grep "5d 00 00 80"
+# hexdump -C arcor_A800_452CPW_FW_1.02.206\(20081201\).bin | grep "00 d5 08 00"

target/linux/ifxmips/files/arch/mips/ifxmips/Makefile

@@ -1 +1 @@
-obj-y := reset.o prom.o setup.o irq.o dma-core.o pmu.o board.o clock.o gpio.o
+obj-y := reset.o prom.o setup.o irq.o dma-core.o pmu.o board.o clock.o gpio.o timer.o

target/linux/ifxmips/files/arch/mips/ifxmips/timer.c

@@ -13,11 +13,11 @@
 #include <asm/irq.h>
 #include <asm/div64.h>
 
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
-#include <asm/mach-ifxmips/cgu.h>
-#include <asm/ifxmips/ifxmips_gptu.h>
-#include <asm/ifxmips/ifxmips_pmu.h>
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+#include <ifxmips_cgu.h>
+#include <ifxmips_gptu.h>
+#include <ifxmips_pmu.h>
 
 #define MAX_NUM_OF_32BIT_TIMER_BLOCKS	6
 

target/linux/ramips/Makefile

@@ -16,7 +16,7 @@ FEATURES:=squashfs broken
 LINUX_VERSION:=2.6.32.10
 
 include $(INCLUDE_DIR)/target.mk
-DEFAULT_PACKAGES+=kmod-leds-gpio
+DEFAULT_PACKAGES+=kmod-leds-gpio wpad-mini
 
 define Target/Description
 	Build firmware images for Ralink RT288x/RT305x based boards.