qi-hardware/openwrt-xburst
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Merge branch 'xburst' of projects.qi-hardware.com:openwrt-xburst into xburst

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This commit is contained in:
Mirko Vogt 2009-11-21 13:48:01 +01:00
commit 1689628529
40 changed files with 295 additions and 630 deletions
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7
Config.in
View File

@ -87,6 +87,13 @@ menu "Target Images"
help help
Create some bootable ISO image Create some bootable ISO image
config TARGET_ROOTFS_UBIFS
bool "ubifs"
default y if USES_UBIFS
depends !TARGET_ROOTFS_INITRAMFS
help
Build a ubifs root filesystem
comment "Image Options" comment "Image Options"
source "target/linux/*/image/Config.in" source "target/linux/*/image/Config.in"

10
include/image.mk
View File

@ -82,6 +82,14 @@ ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y)
( cd $(TARGET_DIR); find . | cpio -o -H newc | gzip -9 >$(BIN_DIR)/openwrt-$(BOARD)-rootfs.cpio.gz ) ( cd $(TARGET_DIR); find . | cpio -o -H newc | gzip -9 >$(BIN_DIR)/openwrt-$(BOARD)-rootfs.cpio.gz )
endef endef
endif endif
ifeq ($(CONFIG_TARGET_ROOTFS_UBIFS),y)
define Image/mkfs/ubifs
$(CP) ./ubinize.cfg $(KDIR)
mkfs.ubifs $(UBIFS_OPTS) -o $(KDIR)/root.ubifs -d $(TARGET_DIR)
(cd $(KDIR); \
ubinize $(UBINIZE_OPTS) -o $(BIN_DIR)/openwrt-$(BOARD)-rootfs.ubi ubinize.cfg)
endef
endif
else else
define Image/BuildKernel define Image/BuildKernel
cp $(KDIR)/vmlinux.elf $(BIN_DIR)/openwrt-$(BOARD)-vmlinux.elf cp $(KDIR)/vmlinux.elf $(BIN_DIR)/openwrt-$(BOARD)-vmlinux.elf
@ -146,6 +154,7 @@ ifneq ($(IB),1)
$(call Image/mkfs/cpiogz) $(call Image/mkfs/cpiogz)
$(call Image/mkfs/ext2) $(call Image/mkfs/ext2)
$(call Image/mkfs/iso) $(call Image/mkfs/iso)
$(call Image/mkfs/ubifs)
$(call Image/Checksum) $(call Image/Checksum)
else else
install: compile install-targets install: compile install-targets
@ -156,6 +165,7 @@ else
$(call Image/mkfs/cpiogz) $(call Image/mkfs/cpiogz)
$(call Image/mkfs/ext2) $(call Image/mkfs/ext2)
$(call Image/mkfs/iso) $(call Image/mkfs/iso)
$(call Image/mkfs/ubifs)
$(call Image/Checksum) $(call Image/Checksum)
endif endif

10
target/linux/xburst/config-2.6.31
View File

@ -137,6 +137,7 @@ CONFIG_HW_CONSOLE=y
CONFIG_INET_DIAG=y CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y CONFIG_INET_TCP_DIAG=y
CONFIG_INPUT=y CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_GPIO_BUTTONS is not set # CONFIG_INPUT_GPIO_BUTTONS is not set
CONFIG_INPUT_KEYBOARD=y CONFIG_INPUT_KEYBOARD=y
# CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_YEALINK is not set
@ -150,6 +151,7 @@ CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_RARP is not set # CONFIG_IP_PNP_RARP is not set
CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU=y
CONFIG_JBD=y CONFIG_JBD=y
# CONFIG_JFFS2_FS is not set
CONFIG_JZ4740_ADC=y CONFIG_JZ4740_ADC=y
CONFIG_JZ4740_QI_LB60=y CONFIG_JZ4740_QI_LB60=y
CONFIG_JZRISC=y CONFIG_JZRISC=y
@ -163,7 +165,6 @@ CONFIG_KEYBOARD_MATRIX=y
# CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_XTKBD is not set
CONFIG_LBDAF=y
CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_GPM940B0=y CONFIG_LCD_GPM940B0=y
# CONFIG_LCD_ILI9320 is not set # CONFIG_LCD_ILI9320 is not set
@ -192,6 +193,7 @@ CONFIG_MACH_JZ=y
# CONFIG_MACH_TX49XX is not set # CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set # CONFIG_MACH_VR41XX is not set
# CONFIG_MIKROTIK_RB532 is not set # CONFIG_MIKROTIK_RB532 is not set
# CONFIG_MINI_FO is not set
CONFIG_MIPS=y CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set # CONFIG_MIPS_COBALT is not set
# CONFIG_MIPS_FPU_EMU is not set # CONFIG_MIPS_FPU_EMU is not set
@ -225,6 +227,7 @@ CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_NET_SCHED is not set # CONFIG_NET_SCHED is not set
# CONFIG_NEW_LEDS is not set # CONFIG_NEW_LEDS is not set
CONFIG_NLS=y CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NO_IOPORT is not set # CONFIG_NO_IOPORT is not set
# CONFIG_NXP_STB220 is not set # CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set # CONFIG_NXP_STB225 is not set
@ -252,7 +255,7 @@ CONFIG_SCHED_OMIT_FRAME_POINTER=y
# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_DMA is not set
CONFIG_SDIO_UART=y CONFIG_SDIO_UART=y
CONFIG_SECCOMP=y CONFIG_SECCOMP=y
# CONFIG_SERIAL_8250_EXTENDED is not set # CONFIG_SERIAL_8250 is not set
CONFIG_SERIO=y CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set # CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_LIBPS2=y
@ -296,6 +299,7 @@ CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y CONFIG_SPI_MASTER=y
# CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_SPIDEV is not set
# CONFIG_SQUASHFS is not set
CONFIG_SUSPEND=y CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y CONFIG_SUSPEND_FREEZER=y
# CONFIG_SYN_COOKIES is not set # CONFIG_SYN_COOKIES is not set
@ -308,7 +312,7 @@ CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
CONFIG_TCP_CONG_CUBIC=y CONFIG_TCP_CONG_CUBIC=y
CONFIG_TRAD_SIGNALS=y CONFIG_TRAD_SIGNALS=y
CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS=y
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UBIFS_FS_DEBUG is not set # CONFIG_UBIFS_FS_DEBUG is not set
CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_LZO=y
# CONFIG_UBIFS_FS_XATTR is not set # CONFIG_UBIFS_FS_XATTR is not set

26
target/linux/xburst/files-2.6.31/arch/mips/include/asm/jzsoc.h
View File

@ -1,26 +0,0 @@
/*
* linux/include/asm-mips/jzsoc.h
*
* Ingenic's JZXXXX SoC common include.
*
* Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
*
* Author: <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_JZSOC_H__
#define __ASM_JZSOC_H__
/*
* SoC include
*/
#ifdef CONFIG_SOC_JZ4740
#include <asm/mach-jz4740/jz4740.h>
#endif
#endif /* __ASM_JZSOC_H__ */

69
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/board-dipper.h
View File

@ -1,69 +0,0 @@
/*
* linux/include/asm-mips/mach-jz4740/board-dipper.h
*
* JZ4725-based (16bit) Dipper board ver 1.x definition.
*
* Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
*
* Author: <lhhuang@ingenic.cn>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_JZ4725_DIPPER_H__
#define __ASM_JZ4725_DIPPER_H__
/*======================================================================
* Frequencies of on-board oscillators
*/
#define JZ_EXTAL 12000000 /* Main extal freq: 12 MHz */
#define JZ_EXTAL2 32768 /* RTC extal freq: 32.768 KHz */
/*======================================================================
* GPIO JZ4725
*/
#define GPIO_SD_VCC_EN_N 85 /* GPC21 */
#define GPIO_SD_CD_N 91 /* GPC27 */
#define GPIO_SD_WP 112 /* GPD16 */
#define GPIO_USB_DETE 124 /* GPD28 */
#define GPIO_DC_DETE_N 103 /* GPD7 */
#define GPIO_CHARG_STAT_N 86 /* GPC22 */
#define GPIO_DISP_OFF_N 118 /* GPD22 */
#define GPIO_UDC_HOTPLUG GPIO_USB_DETE
/*======================================================================
* MMC/SD
*/
#define MSC_WP_PIN GPIO_SD_WP
#define MSC_HOTPLUG_PIN GPIO_SD_CD_N
#define MSC_HOTPLUG_IRQ (IRQ_GPIO_0 + GPIO_SD_CD_N)
#define __msc_init_io() \
do { \
__gpio_as_output(GPIO_SD_VCC_EN_N); \
__gpio_as_input(GPIO_SD_CD_N); \
} while (0)
#define __msc_enable_power() \
do { \
__gpio_clear_pin(GPIO_SD_VCC_EN_N); \
} while (0)
#define __msc_disable_power() \
do { \
__gpio_set_pin(GPIO_SD_VCC_EN_N); \
} while (0)
#define __msc_card_detected(s) \
({ \
int detected = 1; \
if (__gpio_get_pin(GPIO_SD_CD_N)) \
detected = 0; \
detected; \
})
#endif /* __ASM_JZ4740_DIPPER_H__ */

56
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/board-leo.h
View File

@ -1,56 +0,0 @@
#ifndef __ASM_JZ4740_LEO_H__
#define __ASM_JZ4740_LEO_H__
/*
* Define your board specific codes here !!!
*/
/*======================================================================
* Frequencies of on-board oscillators
*/
#define JZ_EXTAL 12000000 /* Main extal freq: 12 MHz */
#define JZ_EXTAL2 32768 /* RTC extal freq: 32.768 KHz */
/*======================================================================
* GPIO
*/
#define GPIO_DISP_OFF_N 100
#define GPIO_SD_VCC_EN_N 119
#define GPIO_SD_CD_N 120
#define GPIO_SD_WP 111
/*======================================================================
* MMC/SD
*/
#define MSC_WP_PIN GPIO_SD_WP
#define MSC_HOTPLUG_PIN GPIO_SD_CD_N
#define MSC_HOTPLUG_IRQ (IRQ_GPIO_0 + GPIO_SD_CD_N)
#define __msc_init_io() \
do { \
__gpio_as_output(GPIO_SD_VCC_EN_N); \
__gpio_as_input(GPIO_SD_CD_N); \
} while (0)
#define __msc_enable_power() \
do { \
__gpio_clear_pin(GPIO_SD_VCC_EN_N); \
} while (0)
#define __msc_disable_power() \
do { \
__gpio_set_pin(GPIO_SD_VCC_EN_N); \
} while (0)
#define __msc_card_detected(s) \
({ \
int detected = 1; \
__gpio_as_input(GPIO_SD_CD_N); \
if (__gpio_get_pin(GPIO_SD_CD_N)) \
detected = 0; \
detected; \
})
#endif /* __ASM_JZ4740_BOARD_LEO_H__ */

70
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/board-lyra.h
View File

@ -1,70 +0,0 @@
/*
* linux/include/asm-mips/mach-jz4740/board-lyra.h
*
* JZ4740-based LYRA board ver 2.x definition.
*
* Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
*
* Author: <lhhuang@ingenic.cn>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_JZ4740_LYRA_H__
#define __ASM_JZ4740_LYRA_H__
/*======================================================================
* Frequencies of on-board oscillators
*/
#define JZ_EXTAL 12000000 /* Main extal freq: 12 MHz */
#define JZ_EXTAL2 32768 /* RTC extal freq: 32.768 KHz */
/*======================================================================
* GPIO
*/
#define GPIO_SD_VCC_EN_N 113 /* GPD17 */
#define GPIO_SD_CD_N 110 /* GPD14 */
#define GPIO_SD_WP 112 /* GPD16 */
#define GPIO_USB_DETE 102 /* GPD6 */
#define GPIO_DC_DETE_N 103 /* GPD7 */
#define GPIO_CHARG_STAT_N 111 /* GPD15 */
#define GPIO_DISP_OFF_N 118 /* GPD22 */
#define GPIO_LED_EN 124 /* GPD28 */
#define GPIO_UDC_HOTPLUG GPIO_USB_DETE
/*======================================================================
* MMC/SD
*/
#define MSC_WP_PIN GPIO_SD_WP
#define MSC_HOTPLUG_PIN GPIO_SD_CD_N
#define MSC_HOTPLUG_IRQ (IRQ_GPIO_0 + GPIO_SD_CD_N)
#define __msc_init_io() \
do { \
__gpio_as_output(GPIO_SD_VCC_EN_N); \
__gpio_as_input(GPIO_SD_CD_N); \
} while (0)
#define __msc_enable_power() \
do { \
__gpio_clear_pin(GPIO_SD_VCC_EN_N); \
} while (0)
#define __msc_disable_power() \
do { \
__gpio_set_pin(GPIO_SD_VCC_EN_N); \
} while (0)
#define __msc_card_detected(s) \
({ \
int detected = 1; \
if (!(__gpio_get_pin(GPIO_SD_CD_N))) \
detected = 0; \
detected; \
})
#endif /* __ASM_JZ4740_LYRA_H__ */

70
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/board-pavo.h
View File

@ -1,70 +0,0 @@
/*
* linux/include/asm-mips/mach-jz4740/board-pavo.h
*
* JZ4730-based PAVO board ver 2.x definition.
*
* Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
*
* Author: <lhhuang@ingenic.cn>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_JZ4740_PAVO_H__
#define __ASM_JZ4740_PAVO_H__
/*======================================================================
* Frequencies of on-board oscillators
*/
#define JZ_EXTAL 12000000 /* Main extal freq: 12 MHz */
#define JZ_EXTAL2 32768 /* RTC extal freq: 32.768 KHz */
/*======================================================================
* GPIO
*/
#define GPIO_SD_VCC_EN_N 113 /* GPD17 */
#define GPIO_SD_CD_N 110 /* GPD14 */
#define GPIO_SD_WP 112 /* GPD16 */
#define GPIO_USB_DETE 102 /* GPD6 */
#define GPIO_DC_DETE_N 103 /* GPD7 */
#define GPIO_CHARG_STAT_N 111 /* GPD15 */
#define GPIO_DISP_OFF_N 118 /* GPD22 */
#define GPIO_LED_EN 124 /* GPD28 */
#define GPIO_UDC_HOTPLUG GPIO_USB_DETE
/*======================================================================
* MMC/SD
*/
#define MSC_WP_PIN GPIO_SD_WP
#define MSC_HOTPLUG_PIN GPIO_SD_CD_N
#define MSC_HOTPLUG_IRQ (IRQ_GPIO_0 + GPIO_SD_CD_N)
#define __msc_init_io() \
do { \
__gpio_as_output(GPIO_SD_VCC_EN_N); \
__gpio_as_input(GPIO_SD_CD_N); \
} while (0)
#define __msc_enable_power() \
do { \
__gpio_clear_pin(GPIO_SD_VCC_EN_N); \
} while (0)
#define __msc_disable_power() \
do { \
__gpio_set_pin(GPIO_SD_VCC_EN_N); \
} while (0)
#define __msc_card_detected(s) \
({ \
int detected = 1; \
if (__gpio_get_pin(GPIO_SD_CD_N)) \
detected = 0; \
detected; \
})
#endif /* __ASM_JZ4740_PAVO_H__ */

2
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h
View File

@ -59,7 +59,7 @@
*/ */
#define MSC_WP_PIN GPIO_SD_WP #define MSC_WP_PIN GPIO_SD_WP
#define MSC_HOTPLUG_PIN GPIO_SD_CD_N #define MSC_HOTPLUG_PIN GPIO_SD_CD_N
#define MSC_HOTPLUG_IRQ (IRQ_GPIO_0 + GPIO_SD_CD_N) #define MSC_HOTPLUG_IRQ (JZ_IRQ_GPIO(GPIO_SD_CD_N))
#define __msc_init_io() \ #define __msc_init_io() \
do { \ do { \

67
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/board-virgo.h
View File

@ -1,67 +0,0 @@
/*
* linux/include/asm-mips/mach-jz4740/board-virgo.h
*
* JZ4720-based VIRGO board ver 1.x definition.
*
* Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
*
* Author: <lhhuang@ingenic.cn>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_JZ4720_VIRGO_H__
#define __ASM_JZ4720_VIRGO_H__
/*======================================================================
* Frequencies of on-board oscillators
*/
#define JZ_EXTAL 12000000 /* Main extal freq: 12 MHz */
#define JZ_EXTAL2 32768 /* RTC extal freq: 32.768 KHz */
/*======================================================================
* GPIO VIRGO(JZ4720)
*/
#define GPIO_SD_VCC_EN_N 115 /* GPD19 */
#define GPIO_SD_CD_N 116 /* GPD20 */
#define GPIO_USB_DETE 114 /* GPD18 */
#define GPIO_DC_DETE_N 120 /* GPD24 */
#define GPIO_DISP_OFF_N 118 /* GPD22 */
#define GPIO_LED_EN 117 /* GPD21 */
#define GPIO_UDC_HOTPLUG GPIO_USB_DETE
/*======================================================================
* MMC/SD
*/
#define MSC_HOTPLUG_PIN GPIO_SD_CD_N
#define MSC_HOTPLUG_IRQ (IRQ_GPIO_0 + GPIO_SD_CD_N)
#define __msc_init_io() \
do { \
__gpio_as_output(GPIO_SD_VCC_EN_N); \
__gpio_as_input(GPIO_SD_CD_N); \
} while (0)
#define __msc_enable_power() \
do { \
__gpio_clear_pin(GPIO_SD_VCC_EN_N); \
} while (0)
#define __msc_disable_power() \
do { \
__gpio_set_pin(GPIO_SD_VCC_EN_N); \
} while (0)
#define __msc_card_detected(s) \
({ \
int detected = 1; \
if (__gpio_get_pin(GPIO_SD_CD_N)) \
detected = 0; \
detected; \
})
#endif /* __ASM_JZ4720_VIRGO_H__ */

2
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/clock.h
View File

@ -15,6 +15,8 @@
#ifndef __ASM_JZ4740_CLOCK_H__ #ifndef __ASM_JZ4740_CLOCK_H__
#define __ASM_JZ4740_CLOCK_H__ #define __ASM_JZ4740_CLOCK_H__
#include <asm/mach-jz4740/ops.h>
#ifndef JZ_EXTAL #ifndef JZ_EXTAL
//#define JZ_EXTAL 3686400 /* 3.6864 MHz */ //#define JZ_EXTAL 3686400 /* 3.6864 MHz */
#define JZ_EXTAL 12000000 /* 3.6864 MHz */ #define JZ_EXTAL 12000000 /* 3.6864 MHz */

4
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/dma.h
View File

@ -19,7 +19,8 @@
#include <asm/io.h> /* need byte IO */ #include <asm/io.h> /* need byte IO */
#include <linux/spinlock.h> /* And spinlocks */ #include <linux/spinlock.h> /* And spinlocks */
#include <linux/delay.h> #include <linux/delay.h>
#include <asm/system.h> #include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/ops.h>
/* /*
* Descriptor structure for JZ4740 DMA engine * Descriptor structure for JZ4740 DMA engine
@ -167,7 +168,6 @@ extern void disable_dma(unsigned int dmanr);
extern void set_dma_addr(unsigned int dmanr, unsigned int phyaddr); extern void set_dma_addr(unsigned int dmanr, unsigned int phyaddr);
extern void set_dma_count(unsigned int dmanr, unsigned int bytecnt); extern void set_dma_count(unsigned int dmanr, unsigned int bytecnt);
extern void set_dma_mode(unsigned int dmanr, unsigned int mode); extern void set_dma_mode(unsigned int dmanr, unsigned int mode);
extern void jz_set_oss_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
extern void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt); extern void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
extern unsigned int get_dma_residue(unsigned int dmanr); extern unsigned int get_dma_residue(unsigned int dmanr);

40
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/irq.h Normal file
View File

@ -0,0 +1,40 @@
#ifndef __JZ4740_IRQ_H__
#define __JZ4740_IRQ_H__
#define MIPS_CPU_IRQ_BASE 0
#define JZ_IRQ_BASE 8
// 1st-level interrupts
#define JZ_IRQ(x) (JZ_IRQ_BASE + (x))
#define JZ_IRQ_I2C JZ_IRQ(1)
#define JZ_IRQ_UHC JZ_IRQ(3)
#define JZ_IRQ_UART1 JZ_IRQ(8)
#define JZ_IRQ_UART0 JZ_IRQ(9)
#define JZ_IRQ_SADC JZ_IRQ(12)
#define JZ_IRQ_MSC JZ_IRQ(14)
#define JZ_IRQ_RTC JZ_IRQ(15)
#define JZ_IRQ_SSI JZ_IRQ(16)
#define JZ_IRQ_CIM JZ_IRQ(17)
#define JZ_IRQ_AIC JZ_IRQ(18)
#define JZ_IRQ_ETH JZ_IRQ(19)
#define JZ_IRQ_DMAC JZ_IRQ(20)
#define JZ_IRQ_TCU2 JZ_IRQ(21)
#define JZ_IRQ_TCU1 JZ_IRQ(22)
#define JZ_IRQ_TCU0 JZ_IRQ(23)
#define JZ_IRQ_UDC JZ_IRQ(24)
#define JZ_IRQ_GPIO3 JZ_IRQ(25)
#define JZ_IRQ_GPIO2 JZ_IRQ(26)
#define JZ_IRQ_GPIO1 JZ_IRQ(27)
#define JZ_IRQ_GPIO0 JZ_IRQ(28)
#define JZ_IRQ_IPU JZ_IRQ(29)
#define JZ_IRQ_LCD JZ_IRQ(30)
/* 2nd-level interrupts */
#define JZ_IRQ_DMA(x) ((x) + JZ_IRQ(32)) /* 32 to 37 for DMAC channel 0 to 5 */
#define JZ_IRQ_INTC_GPIO(x) (JZ_IRQ_GPIO0 - (x))
#define JZ_IRQ_GPIO(x) (JZ_IRQ(48) + (x))
#define NR_IRQS (JZ_IRQ_GPIO(127) + 1)
#endif

20
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/jz4740.h
View File

@ -18,30 +18,10 @@
#include <asm/mach-jz4740/regs.h> #include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/ops.h> #include <asm/mach-jz4740/ops.h>
#include <asm/mach-jz4740/dma.h> #include <asm/mach-jz4740/dma.h>
#include <asm/mach-jz4740/misc.h>
/*------------------------------------------------------------------ /*------------------------------------------------------------------
* Platform definitions * Platform definitions
*/ */
#ifdef CONFIG_JZ4740_PAVO
#include <asm/mach-jz4740/board-pavo.h>
#endif
#ifdef CONFIG_JZ4740_LEO
#include <asm/mach-jz4740/board-leo.h>
#endif
#ifdef CONFIG_JZ4740_LYRA
#include <asm/mach-jz4740/board-lyra.h>
#endif
#ifdef CONFIG_JZ4725_DIPPER
#include <asm/mach-jz4740/board-dipper.h>
#endif
#ifdef CONFIG_JZ4720_VIRGO
#include <asm/mach-jz4740/board-virgo.h>
#endif
#ifdef CONFIG_JZ4740_QI_LB60 #ifdef CONFIG_JZ4740_QI_LB60
#include <asm/mach-jz4740/board-qi_lb60.h> #include <asm/mach-jz4740/board-qi_lb60.h>

43
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/misc.h
View File

@ -1,43 +0,0 @@
/*
* linux/include/asm-mips/mach-jz4740/misc.h
*
* Ingenic's JZ4740 common include.
*
* Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
*
* Author: <yliu@ingenic.cn>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_JZ4740_MISC_H__
#define __ASM_JZ4740_MISC_H__
/*==========================================================
* I2C
*===========================================================*/
#define I2C_EEPROM_DEV 0xA /* b'1010 */
#define I2C_RTC_DEV 0xD /* b'1101 */
#define DIMM0_SPD_ADDR 0
#define DIMM1_SPD_ADDR 1
#define DIMM2_SPD_ADDR 2
#define DIMM3_SPD_ADDR 3
#define JZ_HCI_ADDR 7
#define DIMM_SPD_LEN 128
#define JZ_HCI_LEN 512 /* 4K bits E2PROM */
#define I2C_RTC_LEN 16
#define HCI_MAC_OFFSET 64
extern void i2c_open(void);
extern void i2c_close(void);
extern void i2c_setclk(unsigned int i2cclk);
extern int i2c_read(unsigned char device, unsigned char *buf,
unsigned char address, int count);
extern int i2c_write(unsigned char device, unsigned char *buf,
unsigned char address, int count);
#endif /* __ASM_JZ4740_MISC_H__ */

2
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/ops.h
View File

@ -16,6 +16,8 @@
#ifndef __JZ4740_OPS_H__ #ifndef __JZ4740_OPS_H__
#define __JZ4740_OPS_H__ #define __JZ4740_OPS_H__
#include <asm/mach-jz4740/regs.h>
/* /*
* Definition of Module Operations * Definition of Module Operations
*/ */

33
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/regs.h
View File

@ -68,39 +68,6 @@
#define REG_INTC_IMCR REG32(INTC_IMCR) #define REG_INTC_IMCR REG32(INTC_IMCR)
#define REG_INTC_IPR REG32(INTC_IPR) #define REG_INTC_IPR REG32(INTC_IPR)
// 1st-level interrupts
#define JZ_IRQ_BASE 8
#define JZ_IRQ(x) (JZ_IRQ_BASE + (x))
#define JZ_IRQ_I2C JZ_IRQ(1)
#define JZ_IRQ_UHC JZ_IRQ(3)
#define JZ_IRQ_UART1 JZ_IRQ(8)
#define JZ_IRQ_UART0 JZ_IRQ(9)
#define JZ_IRQ_SADC JZ_IRQ(12)
#define JZ_IRQ_MSC JZ_IRQ(14)
#define JZ_IRQ_RTC JZ_IRQ(15)
#define JZ_IRQ_SSI JZ_IRQ(16)
#define JZ_IRQ_CIM JZ_IRQ(17)
#define JZ_IRQ_AIC JZ_IRQ(18)
#define JZ_IRQ_ETH JZ_IRQ(19)
#define JZ_IRQ_DMAC JZ_IRQ(20)
#define JZ_IRQ_TCU2 JZ_IRQ(21)
#define JZ_IRQ_TCU1 JZ_IRQ(22)
#define JZ_IRQ_TCU0 JZ_IRQ(23)
#define JZ_IRQ_UDC JZ_IRQ(24)
#define JZ_IRQ_GPIO3 JZ_IRQ(25)
#define JZ_IRQ_GPIO2 JZ_IRQ(26)
#define JZ_IRQ_GPIO1 JZ_IRQ(27)
#define JZ_IRQ_GPIO0 JZ_IRQ(28)
#define JZ_IRQ_IPU JZ_IRQ(29)
#define JZ_IRQ_LCD JZ_IRQ(30)
/* 2nd-level interrupts */
#define JZ_IRQ_DMA(x) ((x) + JZ_IRQ(32)) /* 32 to 37 for DMAC channel 0 to 5 */
#define IRQ_GPIO_0 JZ_IRQ(48) /* 48 to 175 for GPIO pin 0 to 127 */
#define JZ_IRQ_INTC_GPIO(x) (JZ_IRQ_GPIO0 - (x))
#define JZ_IRQ_GPIO(x) (IRQ_GPIO_0 + (x))
#define NUM_DMA 6 #define NUM_DMA 6
#define NUM_GPIO 128 #define NUM_GPIO 128
/************************************************************************* /*************************************************************************

20
target/linux/xburst/files-2.6.31/arch/mips/jz4740/board-qi_lb60.c
View File

@ -7,8 +7,8 @@
* Author: Xiangfu Liu <xiangfu@qi-hardware.com> * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 3 as * it under the terms of the GNU General Public License version 2 or later
* published by the Free Software Foundation. * as published by the Free Software Foundation.
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
@ -28,6 +28,7 @@
#include <linux/spi/spi_gpio.h> #include <linux/spi/spi_gpio.h>
#include <linux/power_supply.h> #include <linux/power_supply.h>
#include <linux/power/jz4740-battery.h> #include <linux/power/jz4740-battery.h>
#include <linux/mmc/jz4740_mmc.h>
/* NAND */ /* NAND */
@ -325,12 +326,12 @@ static struct platform_device qi_lb60_gpio_keys = {
.platform_data = &qi_lb60_gpio_keys_data, .platform_data = &qi_lb60_gpio_keys_data,
} }
}; };
/*
static struct jz_mmc_platform_data jz_mmc_pdata = { static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = {
.card_detect_gpio = JZ_GPIO_PORTD(0), .gpio_card_detect = JZ_GPIO_PORTD(0),
.read_only_gpio = JZ_GPIO_PORTD(16), .gpio_read_only = JZ_GPIO_PORTD(16),
.power_gpio = JZ_GPIO_PORTD(2), .gpio_power = JZ_GPIO_PORTD(2),
};*/ };
static struct platform_device *jz_platform_devices[] __initdata = { static struct platform_device *jz_platform_devices[] __initdata = {
&jz4740_usb_ohci_device, &jz4740_usb_ohci_device,
@ -362,6 +363,7 @@ static int __init qi_lb60_init_platform_devices(void)
jz4740_framebuffer_device.dev.platform_data = &qi_lb60_fb_pdata; jz4740_framebuffer_device.dev.platform_data = &qi_lb60_fb_pdata;
jz4740_nand_device.dev.platform_data = &qi_lb60_nand_pdata; jz4740_nand_device.dev.platform_data = &qi_lb60_nand_pdata;
jz4740_battery_device.dev.platform_data = &qi_lb60_battery_pdata; jz4740_battery_device.dev.platform_data = &qi_lb60_battery_pdata;
jz4740_mmc_device.dev.platform_data = &qi_lb60_mmc_pdata;
spi_register_board_info(qi_lb60_spi_board_info, spi_register_board_info(qi_lb60_spi_board_info,
ARRAY_SIZE(qi_lb60_spi_board_info)); ARRAY_SIZE(qi_lb60_spi_board_info));
@ -371,12 +373,14 @@ static int __init qi_lb60_init_platform_devices(void)
} }
extern int jz_gpiolib_init(void); extern int jz_gpiolib_init(void);
extern int jz_init_clocks(unsigned long extal);
static int __init qi_lb60_board_setup(void) static int __init qi_lb60_board_setup(void)
{ {
printk("Qi Hardware JZ4740 QI_LB60 setup\n"); printk("Qi Hardware JZ4740 QI_LB60 setup\n");
if (jz_gpiolib_init()) if (jz_gpiolib_init())
panic("Failed to initalize jz gpio\n"); panic("Failed to initalize jz gpio\n");
jz_init_clocks(12000000);
board_gpio_setup(); board_gpio_setup();

6
target/linux/xburst/files-2.6.31/arch/mips/jz4740/clock.c
View File

@ -473,6 +473,8 @@ static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate)
jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET, jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET,
JZ_CLOCK_CTRL_LDIV_MASK); JZ_CLOCK_CTRL_LDIV_MASK);
return 0;
} }
static unsigned long jz_clk_ldclk_get_rate(struct clk *clk) static unsigned long jz_clk_ldclk_get_rate(struct clk *clk)
@ -704,8 +706,8 @@ struct clk *clk_get(struct device *dev, const char *name)
struct clk *clk; struct clk *clk;
list_for_each_entry(clk, &jz_clocks, list) { list_for_each_entry(clk, &jz_clocks, list) {
if (strcmp(clk->name, name)) if (strcmp(clk->name, name) == 0)
return clk; return clk;
} }
return ERR_PTR(-ENOENT); return ERR_PTR(-ENOENT);
} }

24
target/linux/xburst/files-2.6.31/arch/mips/jz4740/cpufreq.c
View File

@ -17,7 +17,8 @@
#include <linux/cpufreq.h> #include <linux/cpufreq.h>
#include <asm/jzsoc.h> #include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/clock.h>
#include <asm/processor.h> #include <asm/processor.h>
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \ #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
@ -70,24 +71,6 @@ struct dpm_regs {
u32 pll_up_flag; /* New PLL freq is higher than current or not */ u32 pll_up_flag; /* New PLL freq is higher than current or not */
}; };
extern jz_clocks_t jz_clocks;
static void jz_update_clocks(void)
{
/* Next clocks must be updated if we have changed
* the PLL or divisors.
*/
jz_clocks.cclk = __cpm_get_cclk();
jz_clocks.hclk = __cpm_get_hclk();
jz_clocks.mclk = __cpm_get_mclk();
jz_clocks.pclk = __cpm_get_pclk();
jz_clocks.lcdclk = __cpm_get_lcdclk();
jz_clocks.pixclk = __cpm_get_pixclk();
jz_clocks.i2sclk = __cpm_get_i2sclk();
jz_clocks.usbclk = __cpm_get_usbclk();
jz_clocks.mscclk = __cpm_get_mscclk();
}
static void static void
jz_init_boot_config(void) jz_init_boot_config(void)
{ {
@ -434,9 +417,6 @@ static void jz4740_transition(struct dpm_regs *regs)
REG_LCD_CTRL &= ~LCD_CTRL_DIS; REG_LCD_CTRL &= ~LCD_CTRL_DIS;
REG_LCD_CTRL |= LCD_CTRL_ENA; REG_LCD_CTRL |= LCD_CTRL_ENA;
#endif #endif
/* Update system clocks */
jz_update_clocks();
} }
extern unsigned int idle_times; extern unsigned int idle_times;

40
target/linux/xburst/files-2.6.31/arch/mips/jz4740/dma.c
View File

@ -21,14 +21,14 @@
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/sched.h> #include <linux/sched.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/soundcard.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/jzsoc.h> #include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/ops.h>
#include <asm/mach-jz4740/dma.h>
#define JZ_REG_DMA_SRC_ADDR(x) ((x) * 0x20 + 0x00) #define JZ_REG_DMA_SRC_ADDR(x) ((x) * 0x20 + 0x00)
#define JZ_REG_DMA_DEST_ADDR(x) ((x) * 0x20 + 0x04) #define JZ_REG_DMA_DEST_ADDR(x) ((x) * 0x20 + 0x04)
@ -501,39 +501,6 @@ unsigned int get_dma_residue(unsigned int dmanr)
return count; return count;
} }
void jz_set_oss_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt)
{
struct jz_dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
switch (audio_fmt) {
case AFMT_U8:
/* burst mode : 32BIT */
break;
case AFMT_S16_LE:
/* burst mode : 16BYTE */
if (mode == DMA_MODE_READ) {
chan->mode = DMA_AIC_32_16BYTE_RX_CMD | DMA_MODE_READ;
chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
mode &= DMA_MODE_MASK;
chan->mode |= DMAC_DCMD_DAI;
chan->mode &= ~DMAC_DCMD_SAI;
} else if (mode == DMA_MODE_WRITE) {
chan->mode = DMA_AIC_32_16BYTE_TX_CMD | DMA_MODE_WRITE;
chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
mode &= DMA_MODE_MASK;
chan->mode |= DMAC_DCMD_SAI;
chan->mode &= ~DMAC_DCMD_DAI;
} else
printk("oss_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
jz_dma_write(JZ_REG_DMA_CMD(chan->io), chan->mode & ~DMA_MODE_MASK);
jz_dma_write(JZ_REG_DMA_TYPE(chan->io), chan->source);
break;
}
}
void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt) void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt)
{ {
@ -912,7 +879,6 @@ EXPORT_SYMBOL(jz_set_dma_dest_width);
EXPORT_SYMBOL(jz_set_dma_block_size); EXPORT_SYMBOL(jz_set_dma_block_size);
EXPORT_SYMBOL(jz_set_dma_mode); EXPORT_SYMBOL(jz_set_dma_mode);
EXPORT_SYMBOL(set_dma_mode); EXPORT_SYMBOL(set_dma_mode);
EXPORT_SYMBOL(jz_set_oss_dma);
EXPORT_SYMBOL(jz_set_alsa_dma); EXPORT_SYMBOL(jz_set_alsa_dma);
EXPORT_SYMBOL(set_dma_addr); EXPORT_SYMBOL(set_dma_addr);
EXPORT_SYMBOL(set_dma_count); EXPORT_SYMBOL(set_dma_count);

43
target/linux/xburst/files-2.6.31/arch/mips/jz4740/gpio.c
View File

@ -59,9 +59,9 @@
#define CHIP_TO_DATA_SELECT_REG(chip) CHIP_TO_REG(chip, 0x50) #define CHIP_TO_DATA_SELECT_REG(chip) CHIP_TO_REG(chip, 0x50)
#define CHIP_TO_DATA_SELECT_SET_REG(chip) CHIP_TO_REG(chip, 0x54) #define CHIP_TO_DATA_SELECT_SET_REG(chip) CHIP_TO_REG(chip, 0x54)
#define CHIP_TO_DATA_SELECT_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x58) #define CHIP_TO_DATA_SELECT_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x58)
#define CHIP_TO_DATA_DIRECION_REG(chip) CHIP_TO_REG(chip, 0x60) #define CHIP_TO_DIRECION_REG(chip) CHIP_TO_REG(chip, 0x60)
#define CHIP_TO_DATA_DIRECTION_SET_REG(chip) CHIP_TO_REG(chip, 0x64) #define CHIP_TO_DIRECTION_SET_REG(chip) CHIP_TO_REG(chip, 0x64)
#define CHIP_TO_DATA_DIRECTION_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x68) #define CHIP_TO_DIRECTION_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x68)
#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f) #define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
@ -94,6 +94,7 @@ struct jz_gpio_chip {
uint32_t saved[4]; uint32_t saved[4];
struct gpio_chip gpio_chip; struct gpio_chip gpio_chip;
struct irq_chip irq_chip; struct irq_chip irq_chip;
uint32_t edge_trigger_both;
}; };
static struct jz_gpio_chip *jz_irq_to_chip(unsigned int irq) static struct jz_gpio_chip *jz_irq_to_chip(unsigned int irq)
@ -186,7 +187,7 @@ static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
{ {
writel(BIT(gpio), CHIP_TO_DATA_DIRECTION_SET_REG(chip)); writel(BIT(gpio), CHIP_TO_DIRECTION_SET_REG(chip));
jz_gpio_set_value(chip, gpio, value); jz_gpio_set_value(chip, gpio, value);
return 0; return 0;
@ -194,7 +195,7 @@ static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int v
static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{ {
writel(BIT(gpio), CHIP_TO_DATA_DIRECTION_CLEAR_REG(chip)); writel(BIT(gpio), CHIP_TO_DIRECTION_CLEAR_REG(chip));
return 0; return 0;
} }
@ -205,6 +206,7 @@ static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
#define IRQ_TO_REG(irq, reg) GPIO_TO_REG(IRQ_TO_GPIO(irq), reg) #define IRQ_TO_REG(irq, reg) GPIO_TO_REG(IRQ_TO_GPIO(irq), reg)
#define IRQ_TO_PIN_REG(irq) IRQ_TO_REG(irq, 0x00)
#define IRQ_TO_MASK_REG(irq) IRQ_TO_REG(irq, 0x20) #define IRQ_TO_MASK_REG(irq) IRQ_TO_REG(irq, 0x20)
#define IRQ_TO_MASK_SET_REG(irq) IRQ_TO_REG(irq, 0x24) #define IRQ_TO_MASK_SET_REG(irq) IRQ_TO_REG(irq, 0x24)
#define IRQ_TO_MASK_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x28) #define IRQ_TO_MASK_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x28)
@ -226,14 +228,28 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
uint32_t flag; uint32_t flag;
unsigned int gpio_irq; unsigned int gpio_irq;
unsigned int gpio_bank; unsigned int gpio_bank;
struct jz_gpio_chip *chip = get_irq_desc_data(desc);
gpio_bank = JZ_IRQ_GPIO0 - irq; gpio_bank = JZ_IRQ_GPIO0 - irq;
flag = readl(jz_gpio_base + (gpio_bank << 8) + 0x80); flag = readl(jz_gpio_base + (gpio_bank << 8) + 0x80);
gpio_irq = ffs(flag); gpio_irq = ffs(flag) - 1;
if (chip->edge_trigger_both & BIT(gpio_irq)) {
uint32_t value = readl(CHIP_TO_PIN_REG(&chip->gpio_chip));
if (value & BIT(gpio_irq)) {
writel(BIT(gpio_irq),
CHIP_TO_DIRECTION_CLEAR_REG(&chip->gpio_chip));
} else {
writel(BIT(gpio_irq),
CHIP_TO_DIRECTION_SET_REG(&chip->gpio_chip));
}
}
gpio_irq += (gpio_bank << 5) + JZ_IRQ_GPIO(0);
gpio_irq += (gpio_bank << 5) + JZ_IRQ_GPIO(0) - 1;
generic_handle_irq(gpio_irq); generic_handle_irq(gpio_irq);
}; };
@ -276,11 +292,22 @@ static void jz_gpio_irq_ack(unsigned int irq)
static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
{ {
uint32_t mask; uint32_t mask;
struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
spin_lock(&jz_gpio_lock); spin_lock(&jz_gpio_lock);
mask = readl(IRQ_TO_MASK_REG(irq)); mask = readl(IRQ_TO_MASK_REG(irq));
writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_CLEAR_REG(irq)); writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_CLEAR_REG(irq));
if (flow_type == IRQ_TYPE_EDGE_BOTH) {
uint32_t value = readl(IRQ_TO_PIN_REG(irq));
if (value & IRQ_TO_BIT(irq))
flow_type = IRQ_TYPE_EDGE_FALLING;
else
flow_type = IRQ_TYPE_EDGE_RISING;
chip->edge_trigger_both |= IRQ_TO_BIT(irq);
} else {
chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
}
switch(flow_type) { switch(flow_type) {
case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_EDGE_RISING:
@ -288,7 +315,6 @@ static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_SET_REG(irq)); writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_SET_REG(irq));
break; break;
case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_EDGE_BOTH:
writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_CLEAR_REG(irq)); writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_CLEAR_REG(irq));
writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_SET_REG(irq)); writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_SET_REG(irq));
break; break;
@ -376,6 +402,7 @@ int __init jz_gpiolib_init(void)
for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) { for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
gpiochip_add(&chip->gpio_chip); gpiochip_add(&chip->gpio_chip);
chip->irq = JZ_IRQ_INTC_GPIO(i); chip->irq = JZ_IRQ_INTC_GPIO(i);
set_irq_data(chip->irq, chip);
set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler); set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio;
++irq) { ++irq) {

14
target/linux/xburst/files-2.6.31/arch/mips/jz4740/irq.c
View File

@ -11,28 +11,20 @@
* Free Software Foundation; either version 2 of the License, or (at your * Free Software Foundation; either version 2 of the License, or (at your
* option) any later version. * option) any later version.
*/ */
#include <asm/mach-jz4740/irq.h>
#include <linux/irq.h>
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/irq.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/timex.h> #include <linux/timex.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/random.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/jzsoc.h>
#include <asm/mach-generic/irq.h>
#include <asm/irq_cpu.h> #include <asm/irq_cpu.h>
static void __iomem *jz_intc_base; static void __iomem *jz_intc_base;

5
target/linux/xburst/files-2.6.31/arch/mips/jz4740/platform.c
View File

@ -15,7 +15,8 @@
#include <linux/resource.h> #include <linux/resource.h>
#include <asm/mach-jz4740/platform.h> #include <asm/mach-jz4740/platform.h>
#include <asm/jzsoc.h> #include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/irq.h>
/* OHCI (USB full speed host controller) */ /* OHCI (USB full speed host controller) */
static struct resource jz4740_usb_ohci_resources[] = { static struct resource jz4740_usb_ohci_resources[] = {
@ -89,7 +90,7 @@ static struct resource jz4740_mmc_resources[] = {
static u64 jz4740_mmc_dmamask = ~(u32)0; static u64 jz4740_mmc_dmamask = ~(u32)0;
struct platform_device jz4740_mmc_device = { struct platform_device jz4740_mmc_device = {
.name = "jz-mmc", .name = "jz4740-mmc",
.id = 0, .id = 0,
.dev = { .dev = {
.dma_mask = &jz4740_mmc_dmamask, .dma_mask = &jz4740_mmc_dmamask,

5
target/linux/xburst/files-2.6.31/arch/mips/jz4740/pm.c
View File

@ -23,9 +23,9 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/pm.h> #include <linux/pm.h>
#include <linux/sysctl.h> #include <linux/delay.h>
#include <linux/suspend.h> #include <linux/suspend.h>
#include <asm/jzsoc.h> #include <asm/mach-jz4740/regs.h>
extern void jz4740_intc_suspend(void); extern void jz4740_intc_suspend(void);
extern void jz4740_intc_resume(void); extern void jz4740_intc_resume(void);
@ -37,7 +37,6 @@ static int jz_pm_enter(suspend_state_t state)
unsigned long delta; unsigned long delta;
unsigned long nfcsr = REG_EMC_NFCSR; unsigned long nfcsr = REG_EMC_NFCSR;
uint32_t scr = REG_CPM_SCR; uint32_t scr = REG_CPM_SCR;
uint32_t sleep_gpio_save[7*3];
/* Preserve current time */ /* Preserve current time */
delta = xtime.tv_sec - REG_RTC_RSR; delta = xtime.tv_sec - REG_RTC_RSR;

4
target/linux/xburst/files-2.6.31/arch/mips/jz4740/proc.c
View File

@ -29,7 +29,9 @@
#include <linux/page-flags.h> #include <linux/page-flags.h>
#include <asm/uaccess.h> #include <asm/uaccess.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/jzsoc.h> #include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/clock.h>
#include <asm/mach-jz4740/ops.h>
//#define DEBUG 1 //#define DEBUG 1
#undef DEBUG #undef DEBUG

2
target/linux/xburst/files-2.6.31/arch/mips/jz4740/prom.c
View File

@ -40,7 +40,7 @@
#include <linux/string.h> #include <linux/string.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/jzsoc.h> #include <asm/mach-jz4740/regs.h>
/* #define DEBUG_CMDLINE */ /* #define DEBUG_CMDLINE */

3
target/linux/xburst/files-2.6.31/arch/mips/jz4740/reset.c
View File

@ -17,7 +17,8 @@
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/reboot.h> #include <asm/reboot.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/jzsoc.h> #include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/jz4740.h>
void jz_restart(char *command) void jz_restart(char *command)
{ {

48
target/linux/xburst/files-2.6.31/arch/mips/jz4740/setup.c
View File

@ -37,17 +37,10 @@
#include <asm/reboot.h> #include <asm/reboot.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/time.h> #include <asm/time.h>
#include <asm/jzsoc.h> #include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/ops.h>
#ifdef CONFIG_PM #include <asm/mach-jz4740/clock.h>
#include <asm/suspend.h> #include <asm/mach-jz4740/serial.h>
#endif
#ifdef CONFIG_PC_KEYB
#include <asm/keyboard.h>
#endif
jz_clocks_t jz_clocks;
extern char * __init prom_getcmdline(void); extern char * __init prom_getcmdline(void);
extern void __init jz_board_setup(void); extern void __init jz_board_setup(void);
@ -58,40 +51,13 @@ extern void jz_time_init(void);
static void __init sysclocks_setup(void) static void __init sysclocks_setup(void)
{ {
#ifndef CONFIG_MIPS_JZ_EMURUS /* FPGA */ #if 0
jz_clocks.cclk = __cpm_get_cclk();
jz_clocks.hclk = __cpm_get_hclk();
jz_clocks.pclk = __cpm_get_pclk();
jz_clocks.mclk = __cpm_get_mclk();
jz_clocks.lcdclk = __cpm_get_lcdclk();
jz_clocks.pixclk = __cpm_get_pixclk();
jz_clocks.i2sclk = __cpm_get_i2sclk();
jz_clocks.usbclk = __cpm_get_usbclk();
jz_clocks.mscclk = __cpm_get_mscclk();
jz_clocks.extalclk = __cpm_get_extalclk();
jz_clocks.rtcclk = __cpm_get_rtcclk();
#else
#define FPGACLK 8000000
jz_clocks.cclk = FPGACLK;
jz_clocks.hclk = FPGACLK;
jz_clocks.pclk = FPGACLK;
jz_clocks.mclk = FPGACLK;
jz_clocks.lcdclk = FPGACLK;
jz_clocks.pixclk = FPGACLK;
jz_clocks.i2sclk = FPGACLK;
jz_clocks.usbclk = FPGACLK;
jz_clocks.mscclk = FPGACLK;
jz_clocks.extalclk = FPGACLK;
jz_clocks.rtcclk = FPGACLK;
#endif
printk("CPU clock: %dMHz, System clock: %dMHz, Peripheral clock: %dMHz, Memory clock: %dMHz\n", printk("CPU clock: %dMHz, System clock: %dMHz, Peripheral clock: %dMHz, Memory clock: %dMHz\n",
(jz_clocks.cclk + 500000) / 1000000, (jz_clocks.cclk + 500000) / 1000000,
(jz_clocks.hclk + 500000) / 1000000, (jz_clocks.hclk + 500000) / 1000000,
(jz_clocks.pclk + 500000) / 1000000, (jz_clocks.pclk + 500000) / 1000000,
(jz_clocks.mclk + 500000) / 1000000); (jz_clocks.mclk + 500000) / 1000000);
#endif
} }
static void __init soc_cpm_setup(void) static void __init soc_cpm_setup(void)
@ -139,7 +105,7 @@ static void __init jz_serial_setup(void)
s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
s.iotype = SERIAL_IO_MEM; s.iotype = SERIAL_IO_MEM;
s.regshift = 2; s.regshift = 2;
s.uartclk = jz_clocks.extalclk ; s.uartclk = JZ_EXTAL;
s.line = 0; s.line = 0;
s.membase = (u8 *)UART0_BASE; s.membase = (u8 *)UART0_BASE;

3
target/linux/xburst/files-2.6.31/arch/mips/jz4740/time.c
View File

@ -26,7 +26,8 @@
#include <linux/clockchips.h> #include <linux/clockchips.h>
#include <asm/time.h> #include <asm/time.h>
#include <asm/jzsoc.h> #include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/jz4740.h>
/* This is for machines which generate the exact clock. */ /* This is for machines which generate the exact clock. */

2
target/linux/xburst/files-2.6.31/drivers/mmc/host/jz_mmc.c
View File

@ -27,7 +27,7 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/scatterlist.h> #include <asm/scatterlist.h>
#include <asm/jzsoc.h> #include <asm/mach-jz4740/jz4740.h>
#include "jz_mmc.h" #include "jz_mmc.h"

3
target/linux/xburst/files-2.6.31/drivers/usb/gadget/jz4740_udc.c
View File

@ -37,7 +37,8 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/jzsoc.h> #include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/clock.h>
#include "jz4740_udc.h" #include "jz4740_udc.h"

88
target/linux/xburst/files-2.6.31/drivers/video/backlight/gpm940b0.c
View File

@ -17,11 +17,13 @@
#include <linux/spi/spi.h> #include <linux/spi/spi.h>
#include <linux/lcd.h> #include <linux/lcd.h>
#include <linux/backlight.h> #include <linux/backlight.h>
#include <linux/delay.h>
struct gpm940b0 { struct gpm940b0 {
struct spi_device *spi; struct spi_device *spi;
struct lcd_device *lcd; struct lcd_device *lcd;
struct backlight_device *bl; struct backlight_device *bl;
unsigned enabled:1;
}; };
static int gpm940b0_write_reg(struct spi_device *spi, uint8_t reg, static int gpm940b0_write_reg(struct spi_device *spi, uint8_t reg,
@ -34,17 +36,32 @@ static int gpm940b0_write_reg(struct spi_device *spi, uint8_t reg,
return spi_write(spi, buf, sizeof(buf)); return spi_write(spi, buf, sizeof(buf));
} }
static void gpm940b0_power_disable(struct gpm940b0 *gpm940b0)
{
int ret = gpm940b0_write_reg(gpm940b0->spi, 0x5, 0xc6) ;
if (ret < 0)
printk("Failed to disable power: %d\n", ret);
}
static void gpm940b0_power_enable(struct gpm940b0 *gpm940b0)
{
gpm940b0_write_reg(gpm940b0->spi, 0x5, 0xc7);
}
static int gpm940b0_set_power(struct lcd_device *lcd, int power) static int gpm940b0_set_power(struct lcd_device *lcd, int power)
{ {
struct gpm940b0 *gpm940b0 = lcd_get_data(lcd); struct gpm940b0 *gpm940b0 = lcd_get_data(lcd);
switch (power) { switch (power) {
case FB_BLANK_UNBLANK: case FB_BLANK_UNBLANK:
gpm940b0_write_reg(gpm940b0->spi, 0x05, 0x5f); gpm940b0->enabled = 1;
break; gpm940b0_power_enable(gpm940b0);
break;
default: default:
gpm940b0_write_reg(gpm940b0->spi, 0x05, 0x5e); gpm940b0->enabled = 0;
break; gpm940b0_power_disable(gpm940b0);
break;
} }
return 0; return 0;
} }
@ -64,18 +81,21 @@ static int gpm940b0_set_mode(struct lcd_device *lcd, struct fb_videomode *mode)
return 0; return 0;
} }
/*
int gpm940b0_bl_update_status(struct backlight_device *bl) int gpm940b0_bl_update_status(struct backlight_device *bl)
{ {
struct gpm940b0 *gpm940b0 = bl_get_data(bl); struct gpm940b0 *gpm940b0 = bl_get_data(bl);
/* The datasheet suggest that this is not possible on the giantplus module gpm940b0->reg5 &= ~0x38;
gpm940b0_write_reg(gpm940b0->spi, 21, bl->props.brightness);*/ gpm940b0->reg5 |= ((bl->props.brightness << 3) & 0x38);
gpm940b0_write_reg(gpm940b0->spi, 0x5, gpm940b0->reg5);
return 0; return 0;
} }*/
static size_t reg_write(struct device *dev, struct device_attribute *attr, static ssize_t reg_write(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count) const char *buf, size_t count)
{ {
char *buf2; char *buf2;
uint32_t reg = simple_strtoul(buf, &buf2, 10); uint32_t reg = simple_strtoul(buf, &buf2, 10);
@ -97,10 +117,12 @@ static struct lcd_ops gpm940b0_lcd_ops = {
.set_mode = gpm940b0_set_mode, .set_mode = gpm940b0_set_mode,
}; };
#if 0
static struct backlight_ops gpm940b0_bl_ops = { static struct backlight_ops gpm940b0_bl_ops = {
/* .get_brightness = gpm940b0_bl_get_brightness,*/ /* .get_brightness = gpm940b0_bl_get_brightness,*/
.update_status = gpm940b0_bl_update_status, .update_status = gpm940b0_bl_update_status,
}; };
#endif
static int __devinit gpm940b0_probe(struct spi_device *spi) static int __devinit gpm940b0_probe(struct spi_device *spi)
{ {
@ -120,7 +142,7 @@ static int __devinit gpm940b0_probe(struct spi_device *spi)
gpm940b0->spi = spi; gpm940b0->spi = spi;
gpm940b0->lcd = lcd_device_register("gpm940b0-lcd", &spi->dev, gpm940b0, gpm940b0->lcd = lcd_device_register("gpm940b0-lcd", &spi->dev, gpm940b0,
&gpm940b0_lcd_ops); &gpm940b0_lcd_ops);
if (IS_ERR(gpm940b0->lcd)) { if (IS_ERR(gpm940b0->lcd)) {
ret = PTR_ERR(gpm940b0->lcd); ret = PTR_ERR(gpm940b0->lcd);
@ -130,6 +152,7 @@ static int __devinit gpm940b0_probe(struct spi_device *spi)
gpm940b0->lcd->props.max_contrast = 255; gpm940b0->lcd->props.max_contrast = 255;
#if 0
gpm940b0->bl = backlight_device_register("gpm940b0-bl", &spi->dev, gpm940b0, gpm940b0->bl = backlight_device_register("gpm940b0-bl", &spi->dev, gpm940b0,
&gpm940b0_bl_ops); &gpm940b0_bl_ops);
@ -138,26 +161,36 @@ static int __devinit gpm940b0_probe(struct spi_device *spi)
dev_err(&spi->dev, "Failed to register backlight device: %d\n", ret); dev_err(&spi->dev, "Failed to register backlight device: %d\n", ret);
gpm940b0->bl = NULL; gpm940b0->bl = NULL;
} else { } else {
gpm940b0->bl->props.max_brightness = 15; gpm940b0->bl->props.max_brightness = 8;
gpm940b0->bl->props.brightness = 0; gpm940b0->bl->props.brightness = 0;
gpm940b0->bl->props.power = FB_BLANK_UNBLANK; gpm940b0->bl->props.power = FB_BLANK_UNBLANK;
} }
device_create_file(&spi->dev, &dev_attr_reg); #endif
ret = device_create_file(&spi->dev, &dev_attr_reg);
if (ret)
goto err_unregister_lcd;
gpm940b0->enabled = 1;
dev_set_drvdata(&spi->dev, gpm940b0); dev_set_drvdata(&spi->dev, gpm940b0);
gpm940b0_write_reg(spi, 0x13, 0x01); gpm940b0_write_reg(spi, 0x13, 0x01);
gpm940b0_write_reg(spi, 0x05, 0x5f); gpm940b0_write_reg(spi, 0x5, 0xc7);
return 0; return 0;
err_unregister_lcd:
lcd_device_unregister(gpm940b0->lcd);
err_free_gpm940b0: err_free_gpm940b0:
kfree(gpm940b0);
return ret; return ret;
} }
static int __devexit gpm940b0_remove(struct spi_device *spi) static int __devexit gpm940b0_remove(struct spi_device *spi)
{ {
struct gpm940b0 *gpm940b0 = spi_get_drvdata(spi); struct gpm940b0 *gpm940b0 = spi_get_drvdata(spi);
#if 0
if (gpm940b0->bl) if (gpm940b0->bl)
backlight_device_unregister(gpm940b0->bl); backlight_device_unregister(gpm940b0->bl);
#endif
lcd_device_unregister(gpm940b0->lcd); lcd_device_unregister(gpm940b0->lcd);
@ -166,6 +199,31 @@ static int __devexit gpm940b0_remove(struct spi_device *spi)
return 0; return 0;
} }
#ifdef CONFIG_PM
static int gpm940b0_suspend(struct spi_device *spi, pm_message_t state)
{
struct gpm940b0 *gpm940b0 = spi_get_drvdata(spi);
if (gpm940b0->enabled) {
gpm940b0_power_disable(gpm940b0);
mdelay(10);
}
return 0;
}
static int gpm940b0_resume(struct spi_device *spi)
{
struct gpm940b0 *gpm940b0 = spi_get_drvdata(spi);
if (gpm940b0->enabled)
gpm940b0_power_enable(gpm940b0);
return 0;
}
#else
#define gpm940b0_suspend NULL
#define gpm940b0_resume NULL
#endif
static struct spi_driver gpm940b0_driver = { static struct spi_driver gpm940b0_driver = {
.driver = { .driver = {
.name = "gpm940b0", .name = "gpm940b0",
@ -173,6 +231,8 @@ static struct spi_driver gpm940b0_driver = {
}, },
.probe = gpm940b0_probe, .probe = gpm940b0_probe,
.remove = __devexit_p(gpm940b0_remove), .remove = __devexit_p(gpm940b0_remove),
.suspend = gpm940b0_suspend,
.resume = gpm940b0_resume,
}; };
static int __init gpm940b0_init(void) static int __init gpm940b0_init(void)
@ -190,4 +250,4 @@ module_exit(gpm940b0_exit)
MODULE_AUTHOR("Lars-Peter Clausen"); MODULE_AUTHOR("Lars-Peter Clausen");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("LCD and backlight controll for Giantplus GPM940B0"); MODULE_DESCRIPTION("LCD and backlight controll for Giantplus GPM940B0");
MODULE_ALIAS("i2c:gpm940b0"); MODULE_ALIAS("spi:gpm940b0");

3
target/linux/xburst/files-2.6.31/sound/soc/jz4740/jz4740-i2s.c
View File

@ -18,6 +18,9 @@
#include <sound/initval.h> #include <sound/initval.h>
#include <sound/soc.h> #include <sound/soc.h>
#include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/ops.h>
#include "jz4740-pcm.h" #include "jz4740-pcm.h"
#include "jz4740-i2s.h" #include "jz4740-i2s.h"

2
target/linux/xburst/files-2.6.31/sound/soc/jz4740/jz4740-pcm.h
View File

@ -8,7 +8,7 @@
#ifndef _JZ4740_PCM_H #ifndef _JZ4740_PCM_H
#define _JZ4740_PCM_H #define _JZ4740_PCM_H
#include <asm/jzsoc.h> #include <asm/mach-jz4740/dma.h>
#define ST_RUNNING (1<<0) #define ST_RUNNING (1<<0)
#define ST_OPENED (1<<1) #define ST_OPENED (1<<1)

3
target/linux/xburst/image/Makefile
View File

@ -9,6 +9,9 @@ include $(INCLUDE_DIR)/image.mk
JFFS2_BLOCKSIZE=256k 512k JFFS2_BLOCKSIZE=256k 512k
UBIFS_OPTS = -m 4096 -e 516096 -c 4095
UBINIZE_OPTS = -m 4096 -p 512KiB
ifneq ($(CONFIG_XBURST_UBOOT),) ifneq ($(CONFIG_XBURST_UBOOT),)
define Build/Clean define Build/Clean
$(MAKE) -C u-boot clean $(MAKE) -C u-boot clean

24
target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch
View File

@ -1,13 +1,13 @@
From 0e135685e7045f606feb6ffc8f2b159e87fcd389 Mon Sep 17 00:00:00 2001 From 23f08521fd9f997876d5e90354b9ad957bb4e982 Mon Sep 17 00:00:00 2001
From: Xiangfu Liu <xiangfu@qi-hardware.com> From: Xiangfu Liu <xiangfu@qi-hardware.com>
Date: Fri, 30 Oct 2009 14:49:02 +0800 Date: Wed, 18 Nov 2009 23:23:56 +0800
Subject: [PATCH] add new file Subject: [PATCH 1/2] add new file
--- ---
board/qi_lb60/Makefile | 38 + board/qi_lb60/Makefile | 38 +
board/qi_lb60/config.mk | 31 + board/qi_lb60/config.mk | 31 +
board/qi_lb60/flash.c | 50 + board/qi_lb60/flash.c | 50 +
board/qi_lb60/qi_lb60.c | 103 + board/qi_lb60/qi_lb60.c | 105 +
board/qi_lb60/u-boot-nand.lds | 63 + board/qi_lb60/u-boot-nand.lds | 63 +
board/qi_lb60/u-boot.lds | 63 + board/qi_lb60/u-boot.lds | 63 +
cpu/mips/jz4740.c | 574 +++++ cpu/mips/jz4740.c | 574 +++++
@ -33,7 +33,7 @@ Subject: [PATCH] add new file
nand_spl/board/qi_lb60/config.mk | 34 + nand_spl/board/qi_lb60/config.mk | 34 +
nand_spl/board/qi_lb60/u-boot.lds | 63 + nand_spl/board/qi_lb60/u-boot.lds | 63 +
nand_spl/nand_boot_jz4740.c | 456 ++++ nand_spl/nand_boot_jz4740.c | 456 ++++
29 files changed, 13573 insertions(+), 0 deletions(-) 29 files changed, 13575 insertions(+), 0 deletions(-)
create mode 100644 board/qi_lb60/Makefile create mode 100644 board/qi_lb60/Makefile
create mode 100644 board/qi_lb60/config.mk create mode 100644 board/qi_lb60/config.mk
create mode 100644 board/qi_lb60/flash.c create mode 100644 board/qi_lb60/flash.c
@ -203,10 +203,10 @@ index 0000000..891c604
+} +}
diff --git a/board/qi_lb60/qi_lb60.c b/board/qi_lb60/qi_lb60.c diff --git a/board/qi_lb60/qi_lb60.c b/board/qi_lb60/qi_lb60.c
new file mode 100644 new file mode 100644
index 0000000..572d22b index 0000000..d13f2ab
--- /dev/null --- /dev/null
+++ b/board/qi_lb60/qi_lb60.c +++ b/board/qi_lb60/qi_lb60.c
@@ -0,0 +1,103 @@ @@ -0,0 +1,105 @@
+/* +/*
+ * Authors: Xiangfu Liu <xiangfu.z@gmail.com> + * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
+ * + *
@ -291,6 +291,8 @@ index 0000000..572d22b
+ __cpm_stop_i2c(); + __cpm_stop_i2c();
+ __cpm_stop_ssi(); + __cpm_stop_ssi();
+ __cpm_stop_uart1(); + __cpm_stop_uart1();
+ __cpm_stop_sadc();
+ __cpm_stop_uhc();
+} +}
+ +
+void board_early_init(void) +void board_early_init(void)
@ -12913,7 +12915,7 @@ index 0000000..2840bc0
+#endif /* __JZ4740_H__ */ +#endif /* __JZ4740_H__ */
diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
new file mode 100644 new file mode 100644
index 0000000..e78d17f index 0000000..02af607
--- /dev/null --- /dev/null
+++ b/include/configs/qi_lb60.h +++ b/include/configs/qi_lb60.h
@@ -0,0 +1,213 @@ @@ -0,0 +1,213 @@
@ -12963,8 +12965,8 @@ index 0000000..e78d17f
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL) +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
+#define CONFIG_BOOTDELAY 0 +#define CONFIG_BOOTDELAY 0
+#define CONFIG_BOOTFILE "uImage" /* file to load */ +#define CONFIG_BOOTFILE "uImage" /* file to load */
+#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 rootfstype=jffs2 root=/dev/mtdblock2 rw rootwait" +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
+#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x300000;bootm" +#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
+ +
+/* +/*
+ * Command line configuration. + * Command line configuration.
@ -13812,5 +13814,5 @@ index 0000000..924a47a
+ (*uboot)(); + (*uboot)();
+} +}
-- --
1.6.0.4 1.6.3.3

8
target/linux/xburst/image/u-boot/patches/0002-add-xburst-support.patch
View File

@ -1,7 +1,7 @@
From 7d8029d27d53b04b223a638de4fc726f6c68359f Mon Sep 17 00:00:00 2001 From 7f32a7a2ec1cf7472684869a5cec40013134c92b Mon Sep 17 00:00:00 2001
From: Xiangfu Liu <xiangfu@qi-hardware.com> From: Xiangfu Liu <xiangfu@qi-hardware.com>
Date: Wed, 21 Oct 2009 11:02:22 +0800 Date: Wed, 18 Nov 2009 23:24:14 +0800
Subject: [PATCH] add qi_lb60 support Subject: [PATCH 2/2] add-xburst-support
--- ---
Makefile | 10 + Makefile | 10 +
@ -1585,5 +1585,5 @@ index 07e356d..4654bf4 100644
+ +
+#endif /* !CONFIG_JzRISC */ +#endif /* !CONFIG_JzRISC */
-- --
1.6.0.4 1.6.3.3

30
target/linux/xburst/image/u-boot/patches/0003-disable-init-gpio-as-uart0.patch Normal file
View File

@ -0,0 +1,30 @@
From 6901dd7d88680eb08b9bd3000244aa8003d0de9f Mon Sep 17 00:00:00 2001
From: Xiangfu Liu <xiangfu@qi-hardware.com>
Date: Fri, 20 Nov 2009 23:29:31 +0800
Subject: [PATCH] disable init gpio as uart0
---
board/qi_lb60/qi_lb60.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/qi_lb60/qi_lb60.c b/board/qi_lb60/qi_lb60.c
index d13f2ab..d87619c 100644
--- a/board/qi_lb60/qi_lb60.c
+++ b/board/qi_lb60/qi_lb60.c
@@ -25,9 +25,11 @@ static void gpio_init(void)
__gpio_as_sdram_32bit();
/*
- * Initialize UART0 pins
+ * Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the
+ * same gpio, init the gpio as uart0 cause a keyboard bug. so for
+ * end user we disable the uart0
*/
- __gpio_as_uart0();
+ /* __gpio_as_uart0(); */
/*
* Initialize LCD pins
--
1.6.3.3

14
target/linux/xburst/image/ubinize.cfg Normal file
View File

@ -0,0 +1,14 @@
[rootfs]
# Volume mode (other option is static)
mode=ubi
# Source image
image=root.ubifs
# Volume ID in UBI image
vol_id=0
# Allow for dynamic resize
vol_type=dynamic
# Volume name
vol_name=rootfs
# Autoresize volume at first mount
vol_flags=autoresize