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[ar71xx] add AR7240 specific frequency detection

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16645 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg 2009-07-01 19:34:59 +00:00
parent fc8502c631
commit 16e84ace7d
2 changed files with 39 additions and 0 deletions
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28
target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
View File

@ -33,6 +33,7 @@
#define AR71XX_SYS_TYPE_LEN 64 #define AR71XX_SYS_TYPE_LEN 64
#define AR71XX_BASE_FREQ 40000000 #define AR71XX_BASE_FREQ 40000000
#define AR91XX_BASE_FREQ 5000000 #define AR91XX_BASE_FREQ 5000000
#define AR724X_BASE_FREQ 5000000
enum ar71xx_mach_type ar71xx_mach; enum ar71xx_mach_type ar71xx_mach;
@ -206,6 +207,29 @@ static void __init ar71xx_detect_sys_frequency(void)
ar71xx_ahb_freq = ar71xx_cpu_freq / div; ar71xx_ahb_freq = ar71xx_cpu_freq / div;
} }
static void __init ar724x_detect_sys_frequency(void)
{
u32 pll;
u32 freq;
u32 div;
pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
freq = div * AR724X_BASE_FREQ;
div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
freq *= div;
ar71xx_cpu_freq = freq;
div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
ar71xx_ddr_freq = freq / div;
div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
ar71xx_ahb_freq = ar71xx_cpu_freq / div;
}
static void __init detect_sys_frequency(void) static void __init detect_sys_frequency(void)
{ {
switch (ar71xx_soc) { switch (ar71xx_soc) {
@ -215,6 +239,10 @@ static void __init detect_sys_frequency(void)
ar71xx_detect_sys_frequency(); ar71xx_detect_sys_frequency();
break; break;
case AR71XX_SOC_AR7240:
ar724x_detect_sys_frequency();
break;
case AR71XX_SOC_AR9130: case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132: case AR71XX_SOC_AR9132:
ar91xx_detect_sys_frequency(); ar91xx_detect_sys_frequency();

11
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
View File

@ -157,6 +157,17 @@ extern enum ar71xx_mach_type ar71xx_mach;
#define AR71XX_ETH0_PLL_SHIFT 17 #define AR71XX_ETH0_PLL_SHIFT 17
#define AR71XX_ETH1_PLL_SHIFT 19 #define AR71XX_ETH1_PLL_SHIFT 19
#define AR724X_PLL_REG_CPU_CONFIG 0x00
#define AR724X_PLL_DIV_SHIFT 0
#define AR724X_PLL_DIV_MASK 0x3ff
#define AR724X_PLL_REF_DIV_SHIFT 10
#define AR724X_PLL_REF_DIV_MASK 0xf
#define AR724X_AHB_DIV_SHIFT 19
#define AR724X_AHB_DIV_MASK 0x1
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
#define AR91XX_PLL_REG_CPU_CONFIG 0x00 #define AR91XX_PLL_REG_CPU_CONFIG 0x00
#define AR91XX_PLL_REG_ETH_CONFIG 0x04 #define AR91XX_PLL_REG_ETH_CONFIG 0x04
#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14