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[ar71xx] add AR7240 specific definitions
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16644 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -103,45 +103,66 @@ static void __init ar71xx_detect_mem_size(void)
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static void __init ar71xx_detect_sys_type(void)
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{
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char *chip;
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char *chip = "????";
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u32 id;
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u32 rev;
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u32 major;
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u32 minor;
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u32 rev = 0;
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id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & REV_ID_MASK;
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rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
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id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
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major = id & REV_ID_MAJOR_MASK;
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switch (id & REV_ID_CHIP_MASK) {
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case REV_ID_CHIP_AR7130:
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ar71xx_soc = AR71XX_SOC_AR7130;
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chip = "7130";
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switch (major) {
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case REV_ID_MAJOR_AR71XX:
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minor = id & AR71XX_REV_ID_MINOR_MASK;
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rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
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rev &= AR71XX_REV_ID_REVISION_MASK;
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switch (minor) {
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case AR71XX_REV_ID_MINOR_AR7130:
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ar71xx_soc = AR71XX_SOC_AR7130;
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chip = "7130";
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break;
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case AR71XX_REV_ID_MINOR_AR7141:
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ar71xx_soc = AR71XX_SOC_AR7141;
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chip = "7141";
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break;
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case AR71XX_REV_ID_MINOR_AR7161:
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ar71xx_soc = AR71XX_SOC_AR7161;
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chip = "7161";
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break;
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}
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break;
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case REV_ID_CHIP_AR7141:
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ar71xx_soc = AR71XX_SOC_AR7141;
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chip = "7141";
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case REV_ID_MAJOR_AR724X:
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ar71xx_soc = AR71XX_SOC_AR7240;
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chip = "7240";
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rev = (id & AR724X_REV_ID_REVISION_MASK);
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break;
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case REV_ID_CHIP_AR7161:
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ar71xx_soc = AR71XX_SOC_AR7161;
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chip = "7161";
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break;
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case REV_ID_MAJOR_AR913X:
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minor = id & AR91XX_REV_ID_MINOR_MASK;
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rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
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rev &= AR91XX_REV_ID_REVISION_MASK;
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switch (minor) {
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case AR91XX_REV_ID_MINOR_AR9130:
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ar71xx_soc = AR71XX_SOC_AR9130;
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chip = "9130";
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break;
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case REV_ID_CHIP_AR9130:
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ar71xx_soc = AR71XX_SOC_AR9130;
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chip = "9130";
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break;
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case REV_ID_CHIP_AR9132:
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ar71xx_soc = AR71XX_SOC_AR9132;
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chip = "9132";
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case AR91XX_REV_ID_MINOR_AR9132:
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ar71xx_soc = AR71XX_SOC_AR9132;
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chip = "9132";
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break;
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}
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break;
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default:
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panic("ar71xx: unknown chip id:0x%02x\n", id);
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panic("ar71xx: unknown chip id:0x%08x\n", id);
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}
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sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)",
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chip, rev, id);
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sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
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}
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static void __init ar91xx_detect_sys_frequency(void)
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@ -103,6 +103,7 @@ enum ar71xx_soc_type {
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AR71XX_SOC_AR7130,
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AR71XX_SOC_AR7141,
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AR71XX_SOC_AR7161,
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AR71XX_SOC_AR7240,
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AR71XX_SOC_AR9130,
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AR71XX_SOC_AR9132
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};
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@ -389,16 +390,25 @@ void ar71xx_ddr_flush(u32 reg);
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#define RESET_MODULE_PCI_BUS BIT(1)
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#define RESET_MODULE_PCI_CORE BIT(0)
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#define REV_ID_MASK 0xff
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#define REV_ID_CHIP_MASK 0xf3
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#define REV_ID_CHIP_AR7130 0xa0
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#define REV_ID_CHIP_AR7141 0xa1
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#define REV_ID_CHIP_AR7161 0xa2
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#define REV_ID_CHIP_AR9130 0xb0
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#define REV_ID_CHIP_AR9132 0xb1
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#define REV_ID_MAJOR_MASK 0xf0
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#define REV_ID_MAJOR_AR71XX 0xa0
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#define REV_ID_MAJOR_AR913X 0xb0
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#define REV_ID_MAJOR_AR724X 0xc0
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#define REV_ID_REVISION_MASK 0x3
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#define REV_ID_REVISION_SHIFT 2
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#define AR71XX_REV_ID_MINOR_MASK 0x3
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#define AR71XX_REV_ID_MINOR_AR7130 0x0
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#define AR71XX_REV_ID_MINOR_AR7141 0x1
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#define AR71XX_REV_ID_MINOR_AR7161 0x2
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#define AR71XX_REV_ID_REVISION_MASK 0x3
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#define AR71XX_REV_ID_REVISION_SHIFT 2
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#define AR91XX_REV_ID_MINOR_MASK 0x3
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#define AR91XX_REV_ID_MINOR_AR9130 0x0
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#define AR91XX_REV_ID_MINOR_AR9132 0x1
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#define AR91XX_REV_ID_REVISION_MASK 0x3
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#define AR91XX_REV_ID_REVISION_SHIFT 2
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#define AR724X_REV_ID_REVISION_MASK 0x3
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extern void __iomem *ar71xx_reset_base;
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