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[ar71xx] add AR7240 specific frequency detection
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16645 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -33,6 +33,7 @@
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#define AR71XX_SYS_TYPE_LEN 64
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#define AR71XX_SYS_TYPE_LEN 64
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#define AR71XX_BASE_FREQ 40000000
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#define AR71XX_BASE_FREQ 40000000
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#define AR91XX_BASE_FREQ 5000000
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#define AR91XX_BASE_FREQ 5000000
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#define AR724X_BASE_FREQ 5000000
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enum ar71xx_mach_type ar71xx_mach;
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enum ar71xx_mach_type ar71xx_mach;
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@ -206,6 +207,29 @@ static void __init ar71xx_detect_sys_frequency(void)
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ar71xx_ahb_freq = ar71xx_cpu_freq / div;
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ar71xx_ahb_freq = ar71xx_cpu_freq / div;
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}
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}
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static void __init ar724x_detect_sys_frequency(void)
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{
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u32 pll;
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u32 freq;
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u32 div;
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pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
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freq = div * AR724X_BASE_FREQ;
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div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
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freq *= div;
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ar71xx_cpu_freq = freq;
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div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
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ar71xx_ddr_freq = freq / div;
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div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
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ar71xx_ahb_freq = ar71xx_cpu_freq / div;
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}
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static void __init detect_sys_frequency(void)
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static void __init detect_sys_frequency(void)
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{
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{
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switch (ar71xx_soc) {
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switch (ar71xx_soc) {
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@ -215,6 +239,10 @@ static void __init detect_sys_frequency(void)
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ar71xx_detect_sys_frequency();
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ar71xx_detect_sys_frequency();
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break;
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break;
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case AR71XX_SOC_AR7240:
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ar724x_detect_sys_frequency();
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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case AR71XX_SOC_AR9132:
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ar91xx_detect_sys_frequency();
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ar91xx_detect_sys_frequency();
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@ -157,6 +157,17 @@ extern enum ar71xx_mach_type ar71xx_mach;
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#define AR71XX_ETH0_PLL_SHIFT 17
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#define AR71XX_ETH0_PLL_SHIFT 17
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#define AR71XX_ETH1_PLL_SHIFT 19
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#define AR71XX_ETH1_PLL_SHIFT 19
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#define AR724X_PLL_REG_CPU_CONFIG 0x00
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#define AR724X_PLL_DIV_SHIFT 0
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#define AR724X_PLL_DIV_MASK 0x3ff
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#define AR724X_PLL_REF_DIV_SHIFT 10
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#define AR724X_PLL_REF_DIV_MASK 0xf
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#define AR724X_AHB_DIV_SHIFT 19
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#define AR724X_AHB_DIV_MASK 0x1
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#define AR724X_DDR_DIV_SHIFT 22
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#define AR724X_DDR_DIV_MASK 0x3
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#define AR91XX_PLL_REG_CPU_CONFIG 0x00
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#define AR91XX_PLL_REG_CPU_CONFIG 0x00
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#define AR91XX_PLL_REG_ETH_CONFIG 0x04
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#define AR91XX_PLL_REG_ETH_CONFIG 0x04
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#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
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#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
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