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[ar71xx] add AR7240 specific PCI code
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16674 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
parent
8bed461529
commit
191909b36e
@ -38,15 +38,48 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
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int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
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{
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return ar71xx_pcibios_map_irq(dev, slot, pin);
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int ret = 0;
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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ret = ar71xx_pcibios_map_irq(dev, slot, pin);
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break;
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case AR71XX_SOC_AR7240:
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ret = ar724x_pcibios_map_irq(dev, slot, pin);
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break;
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default:
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break;
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}
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return ret;
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}
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int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
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{
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int ret = 0;
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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board_be_handler = ar71xx_be_handler;
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ret = ar71xx_pcibios_init();
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break;
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case AR71XX_SOC_AR7240:
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ret = ar724x_pcibios_init();
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break;
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default:
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return 0;
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}
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ar71xx_pci_nr_irqs = nr_irqs;
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ar71xx_pci_irq_map = map;
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board_be_handler = ar71xx_be_handler;
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return ar71xx_pcibios_init();
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return ret;
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}
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@ -345,8 +345,8 @@ void ar71xx_ddr_flush(u32 reg);
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#define PCI_IDSEL_ADL_START 17
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#define AR7240_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN4_OFFS)
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#define AR7240_PCI_CFG_SIZE 0x100
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#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000)
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#define AR724X_PCI_CFG_SIZE 0x1000
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#define AR724X_PCI_REG_INT_STATUS 0x4c
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#define AR724X_PCI_REG_INT_MASK 0x50
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@ -30,6 +30,10 @@ int ar71xx_pcibios_init(void) __init;
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int ar71xx_pci_be_handler(int is_fixup);
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int ar724x_pcibios_map_irq(const struct pci_dev *dev,
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uint8_t slot, uint8_t pin) __init;
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int ar724x_pcibios_init(void) __init;
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int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) __init;
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#endif /* __ASM_MACH_AR71XX_PCI_H */
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201
target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c
Normal file
201
target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c
Normal file
@ -0,0 +1,201 @@
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/*
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* Atheros AR724x PCI host controller driver
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*
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/resource.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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#include <asm/mach-ar71xx/pci.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, args...) printk(KERN_INFO fmt, ## args)
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#else
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#define DBG(fmt, args...)
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#endif
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static void __iomem *ar724x_pci_localcfg_base;
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static void __iomem *ar724x_pci_devcfg_base;
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static DEFINE_SPINLOCK(ar724x_pci_lock);
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static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
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{
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unsigned long flags;
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u32 data;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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data &= 0xFF;
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break;
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case 2:
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if (where & 2)
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data >>= 16;
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data &= 0xFFFF;
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break;
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}
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*value = data;
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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}
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static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
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{
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unsigned long flags;
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u32 data;
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int s;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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s = ((where & 3) << 3);
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data &= ~(0xFF << s);
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data |= ((value & 0xFF) << s);
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break;
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case 2:
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s = ((where & 2) << 4);
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data &= ~(0xFFFF << s);
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data |= ((value & 0xFFFF) << s);
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break;
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case 4:
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data = value;
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break;
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}
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__raw_writel(data, base + (where & ~3));
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/* flush write */
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(void)__raw_readl(base + (where & ~3));
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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}
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static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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if (bus->number != 0 || devfn != 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
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DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
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where, size, *value);
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/*
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* WAR for BAR issue - We are unable to access the PCI device space
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* if we set the BAR with proper base address
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*/
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if ((where == 0x10) && (size == 4))
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ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
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return PCIBIOS_SUCCESSFUL;
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}
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static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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if (bus->number != 0 || devfn != 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
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where, size, value);
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ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
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return PCIBIOS_SUCCESSFUL;
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}
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int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
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uint8_t pin)
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{
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int irq = -1;
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int i;
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for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
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struct ar71xx_pci_irq *entry;
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entry = &ar71xx_pci_irq_map[i];
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if (entry->slot == slot && entry->pin == pin) {
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irq = entry->irq;
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break;
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}
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}
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if (irq < 0)
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printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
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pin, pci_name((struct pci_dev *)dev));
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else
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printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
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irq, pin, pci_name((struct pci_dev *)dev));
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return irq;
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}
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static struct pci_ops ar724x_pci_ops = {
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.read = ar724x_pci_read_config,
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.write = ar724x_pci_write_config,
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};
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static struct resource ar724x_pci_io_resource = {
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.name = "PCI IO space",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_IO,
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};
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static struct resource ar724x_pci_mem_resource = {
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.name = "PCI memory space",
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.start = AR71XX_PCI_MEM_BASE,
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.end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_controller ar724x_pci_controller = {
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.pci_ops = &ar724x_pci_ops,
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.mem_resource = &ar724x_pci_mem_resource,
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.io_resource = &ar724x_pci_io_resource,
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};
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int __init ar724x_pcibios_init(void)
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{
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u32 t;
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ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
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AR724X_PCI_CRP_SIZE);
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ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
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AR724X_PCI_CFG_SIZE);
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/* setup COMMAND register */
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t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
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PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
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ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
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register_pci_controller(&ar724x_pci_controller);
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return 0;
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}
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