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ar71xx: ag71xx: fix ARP frame reception on AR934x switch ports

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30926 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg 2012-03-13 17:29:38 +00:00
parent 0fced5df74
commit 1d9a77e99f
1 changed files with 35 additions and 11 deletions
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46
target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
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@ -207,6 +207,17 @@
#define AR934X_REG_OPER_MODE1 0x08 #define AR934X_REG_OPER_MODE1 0x08
#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28) #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
#define AR934X_REG_FLOOD_MASK 0x2c
#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
#define AR934X_REG_QM_CTRL 0x3c
#define AR934X_QM_CTRL_ARP_EN BIT(15)
#define AR934X_REG_AT_CTRL 0x5c
#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
#define AR934X_AT_CTRL_AGE_EN BIT(17)
#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08) #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
@ -556,17 +567,30 @@ static void ar7240sw_setup(struct ar7240sw *as)
/* Setup TAG priority mapping */ /* Setup TAG priority mapping */
ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50); ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
/* Enable ARP frame acknowledge, aging, MAC replacing */ if (sw_is_ar934x(as)) {
ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL, /* Enable aging, MAC replacing */
AR7240_AT_CTRL_RESERVED | ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
0x2b /* 5 min age time */ | 0x2b /* 5 min age time */ |
AR7240_AT_CTRL_AGE_EN | AR934X_AT_CTRL_AGE_EN |
AR7240_AT_CTRL_ARP_EN | AR934X_AT_CTRL_LEARN_CHANGE);
AR7240_AT_CTRL_LEARN_CHANGE); /* Enable ARP frame acknowledge */
ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
/* Enable Broadcast frames transmitted to the CPU */ AR934X_QM_CTRL_ARP_EN);
ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK, /* Enable Broadcast frames transmitted to the CPU */
AR7240_FLOOD_MASK_BROAD_TO_CPU); ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
AR934X_FLOOD_MASK_BC_DP(0));
} else {
/* Enable ARP frame acknowledge, aging, MAC replacing */
ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
AR7240_AT_CTRL_RESERVED |
0x2b /* 5 min age time */ |
AR7240_AT_CTRL_AGE_EN |
AR7240_AT_CTRL_ARP_EN |
AR7240_AT_CTRL_LEARN_CHANGE);
/* Enable Broadcast frames transmitted to the CPU */
ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
AR7240_FLOOD_MASK_BROAD_TO_CPU);
}
/* setup MTU */ /* setup MTU */
ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M, ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,