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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-20 03:48:38 +03:00
add minor code cleanup and a core reset for internal sb devices that need it
git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@2718 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -11221,8 +11221,8 @@ diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c
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+}
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diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
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--- linux.old/arch/mips/bcm947xx/pci.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux.dev/arch/mips/bcm947xx/pci.c 2005-12-18 04:44:18.736590500 +0100
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@@ -0,0 +1,91 @@
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+++ linux.dev/arch/mips/bcm947xx/pci.c 2005-12-18 07:01:36.731635000 +0100
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@@ -0,0 +1,215 @@
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/pci.h>
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@ -11237,8 +11237,11 @@ diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
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+#include <sbmips.h>
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+#include <sbconfig.h>
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+#include <sbpci.h>
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+#include <bcmdevs.h>
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+#include <pcicfg.h>
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+
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+extern sb_t *sbh;
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+extern spinlock_t sbh_lock;
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+
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+
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+static int
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@ -11246,7 +11249,12 @@ diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
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+ int reg, int size, u32 *val)
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+{
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+ int ret;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&sbh_lock, flags);
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+ ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
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+ spin_unlock_irqrestore(&sbh_lock, flags);
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+
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+ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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+}
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+
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@ -11255,7 +11263,12 @@ diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
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+ int reg, int size, u32 val)
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+{
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+ int ret;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&sbh_lock, flags);
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+ ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
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+ spin_unlock_irqrestore(&sbh_lock, flags);
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+
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+ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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+}
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+
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@ -11308,12 +11321,123 @@ diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
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+
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+void bcm47xx_pci_init(void)
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+{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&sbh_lock, flags);
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+ sbpci_init(sbh);
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+ spin_unlock_irqrestore(&sbh_lock, flags);
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+
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+ set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
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+
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+ register_pci_controller(&bcm47xx_sb_pci_controller);
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+ register_pci_controller(&bcm47xx_ext_pci_controller);
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+}
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+
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+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ u8 irq;
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+
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+ if (dev->bus->number == 1)
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+ return 2;
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+
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+ pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
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+ return irq + 2;
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+}
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+
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+u32 pci_iobase = 0x100;
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+u32 pci_membase = SB_PCI_DMA;
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+
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+static void bcm47xx_fixup_device(struct pci_dev *d)
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+{
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+ struct resource *res;
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+ int pos, size;
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+ u32 *base;
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+
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+ if (d->bus->number == 0)
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+ return;
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+
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+ printk("PCI: Fixing up device %s\n", pci_name(d));
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+
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+ /* Fix up resource bases */
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+ for (pos = 0; pos < 6; pos++) {
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+ res = &d->resource[pos];
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+ base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
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+ if (res->end) {
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+ size = res->end - res->start + 1;
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+ if (*base & (size - 1))
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+ *base = (*base + size) & ~(size - 1);
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+ res->start = *base;
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+ res->end = res->start + size - 1;
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+ *base += size;
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+ pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
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+ }
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+ /* Fix up PCI bridge BAR0 only */
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+ if (d->bus->number == 1 && PCI_SLOT(d->devfn) == 0)
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+ break;
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+ }
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+ /* Fix up interrupt lines */
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+ if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
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+ d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
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+ pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
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+}
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+
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+
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+static void bcm47xx_fixup_bridge(struct pci_dev *dev)
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+{
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+ if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
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+ return;
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+
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+ printk("PCI: fixing up bridge\n");
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+
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+ /* Enable PCI bridge bus mastering and memory space */
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+ pci_set_master(dev);
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+ pcibios_enable_device(dev, ~0);
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+
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+ /* Enable PCI bridge BAR1 prefetch and burst */
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+ pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
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+}
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+
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+/* Do platform specific device initialization at pci_enable_device() time */
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+int pcibios_plat_dev_init(struct pci_dev *dev)
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+{
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+ uint coreidx;
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+ unsigned long flags;
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+
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+ bcm47xx_fixup_device(dev);
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+
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+ /* These cores come out of reset enabled */
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+ if ((dev->bus->number != 0) ||
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+ (dev->device == SB_MIPS) ||
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+ (dev->device == SB_MIPS33) ||
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+ (dev->device == SB_EXTIF) ||
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+ (dev->device == SB_CC))
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+ return 0;
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+
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+ /* Do a core reset */
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+ spin_lock_irqsave(&sbh_lock, flags);
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+ coreidx = sb_coreidx(sbh);
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+ if (sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)) && (sb_coreid(sbh) == SB_USB)) {
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+ /*
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+ * The USB core requires a special bit to be set during core
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+ * reset to enable host (OHCI) mode. Resetting the SB core in
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+ * pcibios_enable_device() is a hack for compatibility with
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+ * vanilla usb-ohci so that it does not have to know about
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+ * SB. A driver that wants to use the USB core in device mode
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+ * should know about SB and should reset the bit back to 0
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+ * after calling pcibios_enable_device().
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+ */
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+ sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
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+ sb_core_reset(sbh, 1 << 29);
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+ } else {
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+ sb_core_reset(sbh, 0);
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+ }
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+ sb_setcoreidx(sbh, coreidx);
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+ spin_unlock_irqrestore(&sbh_lock, flags);
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+
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+ return 0;
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+}
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+
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+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcm47xx_fixup_bridge);
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diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
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--- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux.dev/arch/mips/bcm947xx/prom.c 2005-12-15 12:57:27.877187750 +0100
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@ -11379,8 +11503,8 @@ diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.
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+}
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diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
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--- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux.dev/arch/mips/bcm947xx/setup.c 2005-12-18 04:58:53.946564750 +0100
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@@ -0,0 +1,155 @@
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+++ linux.dev/arch/mips/bcm947xx/setup.c 2005-12-18 06:34:52.106215250 +0100
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@@ -0,0 +1,157 @@
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+/*
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+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
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+ * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
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@ -11431,6 +11555,7 @@ diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setu
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+extern void bcm47xx_time_init(void);
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+extern void bcm47xx_timer_setup(struct irqaction *irq);
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+void *sbh;
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+spinlock_t sbh_lock = SPIN_LOCK_UNLOCKED;
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+int boardflags;
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+
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+static int ser_line = 0;
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@ -11535,6 +11660,7 @@ diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setu
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+}
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+
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+EXPORT_SYMBOL(sbh);
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+EXPORT_SYMBOL(sbh_lock);
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+EXPORT_SYMBOL(boardflags);
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diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
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--- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
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@ -11683,99 +11809,6 @@ diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
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tlbw(p);
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break;
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diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
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--- linux.old/arch/mips/pci/Makefile 2005-12-15 13:26:49.814003000 +0100
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+++ linux.dev/arch/mips/pci/Makefile 2005-12-15 14:27:26.439319250 +0100
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@@ -18,6 +18,7 @@
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obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
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obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
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obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
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+obj-$(CONFIG_BCM947XX) += fixup-bcm47xx.o
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#
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# These are still pretty much in the old state, watch, go blind.
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diff -urN linux.old/arch/mips/pci/fixup-bcm47xx.c linux.dev/arch/mips/pci/fixup-bcm47xx.c
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--- linux.old/arch/mips/pci/fixup-bcm47xx.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux.dev/arch/mips/pci/fixup-bcm47xx.c 2005-12-18 04:42:58.079549750 +0100
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@@ -0,0 +1,78 @@
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+#include <linux/init.h>
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+#include <linux/pci.h>
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+#include <typedefs.h>
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+#include <sbconfig.h>
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+#include <bcmdevs.h>
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+#include <pcicfg.h>
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+
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+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ u8 irq;
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+
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+ if (dev->bus->number == 1)
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+ return 2;
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+
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+ pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
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+ return irq + 2;
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+}
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+
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+u32 pci_iobase = 0x100;
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+u32 pci_membase = SB_PCI_DMA;
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+
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+static void bcm47xx_fixup_device(struct pci_dev *d)
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+{
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+ struct resource *res;
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+ int pos, size;
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+ u32 *base;
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+
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+ if (d->bus->number == 0)
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+ return;
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+
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+ printk("PCI: Fixing up device %s\n", pci_name(d));
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+
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+ /* Fix up resource bases */
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+ for (pos = 0; pos < 6; pos++) {
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+ res = &d->resource[pos];
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+ base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
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+ if (res->end) {
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+ size = res->end - res->start + 1;
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+ if (*base & (size - 1))
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+ *base = (*base + size) & ~(size - 1);
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+ res->start = *base;
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+ res->end = res->start + size - 1;
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+ *base += size;
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+ pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
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+ }
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+ /* Fix up PCI bridge BAR0 only */
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+ if (d->bus->number == 1 && PCI_SLOT(d->devfn) == 0)
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+ break;
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+ }
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+ /* Fix up interrupt lines */
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+ if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
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+ d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
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+ pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
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+}
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+
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+static void bcm47xx_fixup_bridge(struct pci_dev *dev)
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+{
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+ if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
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+ return;
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+
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+ printk("PCI: fixing up bridge\n");
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+
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+ /* Enable PCI bridge bus mastering and memory space */
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+ pci_set_master(dev);
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+ pcibios_enable_device(dev, ~0);
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+
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+ /* Enable PCI bridge BAR1 prefetch and burst */
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+ pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
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+}
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+
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+/* Do platform specific device initialization at pci_enable_device() time */
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+int pcibios_plat_dev_init(struct pci_dev *dev)
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+{
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+ bcm47xx_fixup_device(dev);
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+ return 0;
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+}
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+
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+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcm47xx_fixup_bridge);
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diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
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--- linux.old/include/asm-mips/bootinfo.h 2005-12-15 13:26:49.818001250 +0100
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+++ linux.dev/include/asm-mips/bootinfo.h 2005-12-15 12:57:27.969147500 +0100
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