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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 03:13:20 +02:00
Register the second uart on tnetd7300 and fix the watchdog register for 7200/7300, thanks to DerAgo (#2149)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8280 3c298f89-4303-0410-b956-a3cf2f4a3e73
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174f70763e
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@ -252,30 +252,40 @@ static struct platform_device vlynq_high = {
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* as xscale and, obviously, don't work...
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*/
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#if !defined(CONFIG_SERIAL_8250)
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static struct plat_serial8250_port uart0_data =
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{
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.mapbase = AR7_REGS_UART0,
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.irq = AR7_IRQ_UART0,
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.regshift = 2,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
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};
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static struct plat_serial8250_port uart1_data =
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{
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.mapbase = UR8_REGS_UART1,
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.irq = AR7_IRQ_UART1,
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.regshift = 2,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
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};
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static struct plat_serial8250_port uart_data[] = {
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{
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.mapbase = AR7_REGS_UART0,
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.irq = AR7_IRQ_UART0,
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.regshift = 2,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
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},
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{
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.mapbase = AR7_REGS_UART1,
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.irq = AR7_IRQ_UART1,
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.regshift = 2,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
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},
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{
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.flags = 0,
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},
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uart0_data,
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uart1_data,
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{ .flags = 0 }
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};
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static struct plat_serial8250_port uart_data_single[] = {
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uart0_data,
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{ .flags = 0 }
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};
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static struct platform_device uart = {
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.id = 0,
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.name = "serial8250",
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.dev.platform_data = uart_data,
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.dev.platform_data = uart_data_single
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};
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#endif
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@ -317,7 +327,8 @@ static int __init ar7_register_devices(void)
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{
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int res;
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#if defined(CONFIG_SERIAL_8250)
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#ifdef CONFIG_SERIAL_8250
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static struct uart_port uart_port[2];
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memset(uart_port, 0, sizeof(struct uart_port) * 2);
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@ -334,24 +345,38 @@ static int __init ar7_register_devices(void)
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if (res)
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return res;
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uart_port[1].type = PORT_AR7;
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uart_port[1].line = 1;
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uart_port[1].irq = AR7_IRQ_UART1;
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uart_port[1].uartclk = ar7_bus_freq() / 2;
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uart_port[1].iotype = UPIO_MEM;
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uart_port[1].mapbase = AR7_REGS_UART1;
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uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
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uart_port[1].regshift = 2;
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res = early_serial_setup(&uart_port[1]);
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if (res)
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return res;
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#else
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// Only TNETD73xx have a second serial port
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if (ar7_has_second_uart()) {
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uart_port[1].type = PORT_AR7;
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uart_port[1].line = 1;
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uart_port[1].irq = AR7_IRQ_UART1;
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uart_port[1].uartclk = ar7_bus_freq() / 2;
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uart_port[1].iotype = UPIO_MEM;
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uart_port[1].mapbase = UR8_REGS_UART1;
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uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
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uart_port[1].regshift = 2;
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res = early_serial_setup(&uart_port[1]);
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if (res)
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return res;
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}
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#else // !CONFIG_SERIAL_8250
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uart_data[0].uartclk = ar7_bus_freq() / 2;
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uart_data[1].uartclk = uart_data[0].uartclk;
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// Only TNETD73xx have a second serial port
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if (ar7_has_second_uart()) {
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uart.dev.platform_data = uart_data;
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}
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res = platform_device_register(&uart);
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if (res)
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return res;
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#endif
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#endif // CONFIG_SERIAL_8250
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res = platform_device_register(&physmap_flash);
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if (res)
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return res;
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@ -73,10 +73,27 @@ static unsigned expect_close;
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/* XXX currently fixed, allows max margin ~68.72 secs */
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#define prescale_value 0xFFFF
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// Offset of the WDT registers
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static unsigned long ar7_regs_wdt;
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// Pointer to the remapped WDT IO space
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static ar7_wdt_t *ar7_wdt;
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static void ar7_wdt_get_regs(void)
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{
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u16 chip_id = ar7_chip_id();
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switch (chip_id)
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{
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case AR7_CHIP_7100:
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case AR7_CHIP_7200:
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ar7_regs_wdt = AR7_REGS_WDT;
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break;
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default:
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ar7_regs_wdt = UR8_REGS_WDT;
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break;
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}
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}
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static void ar7_wdt_kick(u32 value)
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{
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volatile ar7_wdt_t *ar7_wdt = (ar7_wdt_t *)ioremap(AR7_REGS_WDT, sizeof(ar7_wdt_t));
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ar7_wdt->kick_lock = 0x5555;
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if ((ar7_wdt->kick_lock & 3) == 1) {
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ar7_wdt->kick_lock = 0xAAAA;
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@ -90,8 +107,6 @@ static void ar7_wdt_kick(u32 value)
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static void ar7_wdt_prescale(u32 value)
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{
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volatile ar7_wdt_t *ar7_wdt = (ar7_wdt_t *)ioremap(AR7_REGS_WDT, sizeof(ar7_wdt_t));
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ar7_wdt->prescale_lock = 0x5A5A;
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if ((ar7_wdt->prescale_lock & 3) == 1) {
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ar7_wdt->prescale_lock = 0xA5A5;
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@ -105,8 +120,6 @@ static void ar7_wdt_prescale(u32 value)
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static void ar7_wdt_change(u32 value)
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{
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volatile ar7_wdt_t *ar7_wdt = (ar7_wdt_t *)ioremap(AR7_REGS_WDT, sizeof(ar7_wdt_t));
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ar7_wdt->change_lock = 0x6666;
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if ((ar7_wdt->change_lock & 3) == 1) {
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ar7_wdt->change_lock = 0xBBBB;
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@ -120,8 +133,6 @@ static void ar7_wdt_change(u32 value)
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static void ar7_wdt_disable(u32 value)
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{
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volatile ar7_wdt_t *ar7_wdt = (ar7_wdt_t *)ioremap(AR7_REGS_WDT, sizeof(ar7_wdt_t));
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ar7_wdt->disable_lock = 0x7777;
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if ((ar7_wdt->disable_lock & 3) == 1) {
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ar7_wdt->disable_lock = 0xCCCC;
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@ -285,12 +296,16 @@ static struct miscdevice ar7_wdt_miscdev = {
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static int __init ar7_wdt_init(void)
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{
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int rc;
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ar7_wdt_get_regs();
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if (!request_mem_region(AR7_REGS_WDT, sizeof(ar7_wdt_t), LONGNAME)) {
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if (!request_mem_region(ar7_regs_wdt, sizeof(ar7_wdt_t), LONGNAME)) {
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printk(KERN_WARNING DRVNAME ": watchdog I/O region busy\n");
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return -EBUSY;
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}
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ar7_wdt = (ar7_wdt_t *)ioremap(ar7_regs_wdt, sizeof(ar7_wdt_t));
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ar7_wdt_disable_wdt();
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ar7_wdt_prescale(prescale_value);
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ar7_wdt_update_margin(margin);
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@ -313,7 +328,7 @@ static int __init ar7_wdt_init(void)
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out_register:
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misc_deregister(&ar7_wdt_miscdev);
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out_alloc:
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release_mem_region(AR7_REGS_WDT, sizeof(ar7_wdt_t));
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release_mem_region(ar7_regs_wdt, sizeof(ar7_wdt_t));
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out:
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return rc;
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}
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@ -322,7 +337,8 @@ static void __exit ar7_wdt_cleanup(void)
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{
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unregister_reboot_notifier(&ar7_wdt_notifier);
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misc_deregister(&ar7_wdt_miscdev);
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release_mem_region(AR7_REGS_WDT, sizeof(ar7_wdt_t));
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iounmap(ar7_wdt);
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release_mem_region(ar7_regs_wdt, sizeof(ar7_wdt_t));
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}
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module_init(ar7_wdt_init);
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@ -28,27 +28,21 @@
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#define AR7_REGS_BASE 0x08610000
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#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
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#define AR7_REGS_EMIF (AR7_REGS_BASE + 0x0800)
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#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
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#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
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#define AR7_REGS_WDT (AR7_REGS_BASE + 0x0b00)
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#define AR7_REGS_TIMER0 (AR7_REGS_BASE + 0x0c00)
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#define AR7_REGS_TIMER1 (AR7_REGS_BASE + 0x0d00)
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#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00) // 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock)
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#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
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#define AR7_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
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#define AR7_REGS_I2C (AR7_REGS_BASE + 0x1000)
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#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
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#define AR7_REGS_DMA (AR7_REGS_BASE + 0x1400)
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#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
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#define AR7_REGS_BIST (AR7_REGS_BASE + 0x1700)
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#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
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#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1A00)
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#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00)
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#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1E00)
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#define AR7_REGS_FSER (AR7_REGS_BASE + 0x2000)
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#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
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#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
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#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
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#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
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#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
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#define AR7_RESET_PEREPHERIAL 0x0
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#define AR7_RESET_SOFTWARE 0x4
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#define AR7_RESET_STATUS 0x8
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@ -64,8 +58,6 @@
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#define AR7_GPIO_DIR 0x8
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#define AR7_GPIO_ENABLE 0xC
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#define AR7_GPIO_BIT_STATUS_LED 8
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#define AR7_CHIP_7100 0x18
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#define AR7_CHIP_7200 0x2b
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#define AR7_CHIP_7300 0x05
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@ -131,6 +123,7 @@ static inline int ar7_has_high_cpmac(void)
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}
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}
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#define ar7_has_high_vlynq ar7_has_high_cpmac
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#define ar7_has_second_uart ar7_has_high_cpmac
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static inline void ar7_device_enable(u32 bit)
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{
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