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ramips: add register access functions into the rt288x pci code
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17918 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -4,25 +4,38 @@
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#include <linux/init.h>
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#include <asm/mach-ralink/rt288x.h>
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#include <asm/mach-ralink/rt288x_regs.h>
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#define RT2880_PCI_SLOT1_BASE 0x20000000
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#define RALINK_PCI_BASE 0xA0440000
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#define RT2880_PCI_PCICFG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0000))
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#define RT2880_PCI_ARBCTL ((unsigned long*)(RALINK_PCI_BASE + 0x0080))
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#define RT2880_PCI_BAR0SETUP_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0010))
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#define RT2880_PCI_CONFIG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0020))
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#define RT2880_PCI_CONFIG_DATA ((unsigned long*)(RALINK_PCI_BASE + 0x0024))
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#define RT2880_PCI_MEMBASE ((unsigned long*)(RALINK_PCI_BASE + 0x0028))
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#define RT2880_PCI_IOBASE ((unsigned long*)(RALINK_PCI_BASE + 0x002C))
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#define RT2880_PCI_IMBASEBAR0_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0018))
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#define RT2880_PCI_ID ((unsigned long*)(RALINK_PCI_BASE + 0x0030))
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#define RT2880_PCI_CLASS ((unsigned long*)(RALINK_PCI_BASE + 0x0034))
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#define RT2880_PCI_SUBID ((unsigned long*)(RALINK_PCI_BASE + 0x0038))
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#define RT2880_PCI_PCIMSK_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x000C))
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#define RT2880_PCI_REG_PCICFG_ADDR 0x00
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#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
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#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
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#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
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#define RT2880_PCI_REG_CONFIG_ADDR 0x20
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#define RT2880_PCI_REG_CONFIG_DATA 0x24
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#define RT2880_PCI_REG_MEMBASE 0x28
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#define RT2880_PCI_REG_IOBASE 0x2c
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#define RT2880_PCI_REG_ID 0x30
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#define RT2880_PCI_REG_CLASS 0x34
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#define RT2880_PCI_REG_SUBID 0x38
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#define RT2880_PCI_REG_ARBCTL 0x80
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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void __iomem *rt2880_pci_base;
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static u32 rt2880_pci_reg_read(u32 reg)
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{
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return readl(rt2880_pci_base + reg);
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}
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static void rt2880_pci_reg_write(u32 val, u32 reg)
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{
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writel(val, rt2880_pci_base + reg);
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}
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static int config_access(unsigned char access_type, struct pci_bus *bus,
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unsigned int devfn, unsigned char where, u32 *data)
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{
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@ -33,11 +46,11 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
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address = (bus->number << 16) | (slot << 11) | (func << 8) |
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(where & 0xfc) | 0x80000000;
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writel(address, RT2880_PCI_CONFIG_ADDR);
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rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
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if (access_type == PCI_ACCESS_WRITE)
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writel(*data, RT2880_PCI_CONFIG_DATA);
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rt2880_pci_reg_write(*data, RT2880_PCI_REG_CONFIG_DATA);
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else
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*data = readl(RT2880_PCI_CONFIG_DATA);
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*data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
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return 0;
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}
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@ -117,8 +130,8 @@ void inline read_config(unsigned long bus, unsigned long dev,
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address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
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0x80000000;
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writel(address, RT2880_PCI_CONFIG_ADDR);
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*val = readl(RT2880_PCI_CONFIG_DATA);
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rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
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*val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
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}
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void inline write_config(unsigned long bus, unsigned long dev,
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@ -129,8 +142,8 @@ void inline write_config(unsigned long bus, unsigned long dev,
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address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
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0x80000000;
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writel(address, RT2880_PCI_CONFIG_ADDR);
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writel(val, RT2880_PCI_CONFIG_DATA);
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rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
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rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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@ -174,18 +187,20 @@ static int __init rt2880_pci_init(void)
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unsigned long val = 0;
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int i;
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writel(0, RT2880_PCI_PCICFG_ADDR);
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rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
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rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
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for(i = 0; i < 0xfffff; i++) {}
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writel(0x79, RT2880_PCI_ARBCTL);
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writel(0x07FF0001, RT2880_PCI_BAR0SETUP_ADDR);
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writel(RT2880_PCI_SLOT1_BASE, RT2880_PCI_MEMBASE);
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writel(0x00460000, RT2880_PCI_IOBASE);
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writel(0x08000000, RT2880_PCI_IMBASEBAR0_ADDR);
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writel(0x08021814, RT2880_PCI_ID);
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writel(0x00800001, RT2880_PCI_CLASS);
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writel(0x28801814, RT2880_PCI_SUBID);
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writel(0x000c0000, RT2880_PCI_PCIMSK_ADDR);
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rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
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rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
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rt2880_pci_reg_write(RT2880_PCI_SLOT1_BASE, RT2880_PCI_REG_MEMBASE);
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rt2880_pci_reg_write(0x00460000, RT2880_PCI_REG_IOBASE);
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rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
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rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
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rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
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rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
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rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
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write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
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read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
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