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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-23 23:46:16 +02:00
[mcs814x] provide an early ioremap cookie of the system configuration register
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32489 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -16,6 +16,8 @@
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#include <mach/mcs814x.h>
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#include "common.h"
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#define KHZ 1000
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#define MHZ (KHZ * KHZ)
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@ -32,7 +34,7 @@ struct clk {
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unsigned long divider; /* clock divider */
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u32 usecount; /* reference count */
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struct clk_ops *ops; /* clock operation */
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void __iomem *enable_reg; /* clock enable register */
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u32 enable_reg; /* clock enable register */
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u32 enable_mask; /* clock enable mask */
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};
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@ -52,13 +54,13 @@ static int clk_local_onoff_enable(struct clk *clk, int enable)
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if (!clk->enable_reg)
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return 0;
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tmp = __raw_readl(clk->enable_reg);
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tmp = __raw_readl(mcs814x_sysdbg_base + clk->enable_reg);
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if (!enable)
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tmp &= ~clk->enable_mask;
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else
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tmp |= clk->enable_mask;
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__raw_writel(tmp, clk->enable_reg);
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__raw_writel(tmp, mcs814x_sysdbg_base + clk->enable_reg);
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return 0;
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}
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@ -117,19 +119,19 @@ static struct clk clk_wdt = {
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static struct clk clk_emac = {
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.ops = &default_clk_ops,
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.enable_reg = (void __iomem *)(_CONFADDR_SYSDBG + SYSDBG_SYSCTL),
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.enable_reg = SYSDBG_SYSCTL,
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.enable_mask = SYSCTL_EMAC,
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};
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static struct clk clk_ephy = {
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.ops = &default_clk_ops,
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.enable_reg = (void __iomem *)(_CONFADDR_SYSDBG + SYSDBG_PLL_CTL),
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.enable_mask = ~(1 << 0),
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.enable_reg = SYSDBG_PLL_CTL,
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.enable_mask = ~SYSCTL_EPHY, /* active low */
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};
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static struct clk clk_cipher = {
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.ops = &default_clk_ops,
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.enable_reg = (void __iomem *)(_CONFADDR_SYSDBG + SYSDBG_SYSCTL),
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.enable_reg = SYSDBG_SYSCTL,
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.enable_mask = SYSCTL_CIPHER,
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};
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@ -252,7 +254,7 @@ void __init mcs814x_clk_init(void)
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clkdev_add_table(mcs814x_chip_clks, ARRAY_SIZE(mcs814x_chip_clks));
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/* read the bootstrap registers to know the exact clocking scheme */
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bs1 = __raw_readl(_CONFADDR_SYSDBG + SYSDBG_BS1);
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bs1 = __raw_readl(mcs814x_sysdbg_base + SYSDBG_BS1);
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cpu_freq = (bs1 >> CPU_FREQ_SHIFT) & CPU_FREQ_MASK;
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pr_info("CPU frequency: %lu (kHz)\n", cpu_freq_table[cpu_freq]);
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@ -23,6 +23,8 @@
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#include <asm/pgtable.h>
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#include <asm/mach/map.h>
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void __iomem *mcs814x_sysdbg_base;
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static struct map_desc mcs814x_io_desc[] __initdata = {
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{
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.virtual = MCS814X_IO_BASE,
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@ -65,34 +67,34 @@ static void mcs814x_eth_hardware_filter_set(u8 value)
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{
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u32 reg;
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reg = __raw_readl(_CONFADDR_DBGLED);
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reg = __raw_readl(MCS814X_VIRT_BASE + MCS814X_DBGLED);
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if (value)
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reg |= 0x80;
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else
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reg &= ~0x80;
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__raw_writel(reg, _CONFADDR_DBGLED);
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__raw_writel(reg, MCS814X_VIRT_BASE + MCS814X_DBGLED);
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}
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static void mcs814x_eth_led_cfg_set(u8 cfg)
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{
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u32 reg;
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reg = __raw_readl(_CONFADDR_SYSDBG + SYSDBG_BS2);
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reg = __raw_readl(mcs814x_sysdbg_base + SYSDBG_BS2);
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reg &= ~LED_CFG_MASK;
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reg |= cfg;
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__raw_writel(reg, _CONFADDR_SYSDBG + SYSDBG_BS2);
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__raw_writel(reg, mcs814x_sysdbg_base + SYSDBG_BS2);
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}
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static void mcs814x_eth_buffer_shifting_set(u8 value)
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{
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u8 reg;
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reg = __raw_readb(_CONFADDR_SYSDBG + SYSDBG_SYSCTL_MAC);
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reg = __raw_readb(mcs814x_sysdbg_base + SYSDBG_SYSCTL_MAC);
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if (value)
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reg |= BUF_SHIFT_BIT;
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else
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reg &= ~BUF_SHIFT_BIT;
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__raw_writeb(reg, _CONFADDR_SYSDBG + SYSDBG_SYSCTL_MAC);
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__raw_writeb(reg, mcs814x_sysdbg_base + SYSDBG_SYSCTL_MAC);
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}
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static struct of_device_id mcs814x_eth_ids[] __initdata = {
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@ -130,7 +132,7 @@ void __init mcs814x_init_machine(void)
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u32 bs2, cpu_mode;
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int gpio;
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bs2 = __raw_readl(_CONFADDR_SYSDBG + SYSDBG_BS2);
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bs2 = __raw_readl(mcs814x_sysdbg_base + SYSDBG_BS2);
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cpu_mode = (bs2 >> CPU_MODE_SHIFT) & CPU_MODE_MASK;
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pr_info("CPU mode: %s\n", cpu_modes[cpu_mode].name);
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@ -148,9 +150,14 @@ void __init mcs814x_init_machine(void)
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void __init mcs814x_map_io(void)
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{
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iotable_init(mcs814x_io_desc, ARRAY_SIZE(mcs814x_io_desc));
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mcs814x_sysdbg_base = ioremap(MCS814X_IO_START + MCS814X_SYSDBG,
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MCS814X_SYSDBG_SIZE);
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if (!mcs814x_sysdbg_base)
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panic("unable to remap sysdbg base");
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}
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void mcs814x_restart(char mode, const char *cmd)
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{
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__raw_writel(~(1 << 31), _CONFADDR_SYSDBG);
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__raw_writel(~(1 << 31), mcs814x_sysdbg_base);
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}
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@ -10,5 +10,6 @@ void mcs814x_init_machine(void);
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void mcs814x_handle_irq(struct pt_regs *regs);
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void mcs814x_restart(char mode, const char *cmd);
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extern struct sys_timer mcs814x_timer;
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extern void __iomem *mcs814x_sysdbg_base;
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#endif /* __ARCH_MCS814X_COMMON_H */
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@ -1,10 +1,10 @@
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#include <mach/mcs814x.h>
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.macro addruart, rp, rv, tmp
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ldr \rp, =_PHYS_CONFADDR
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ldr \rv, =_VIRT_CONFADDR
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orr \rp, \rp, #_CONFOFFSET_UART
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orr \rv, \rv, #_CONFOFFSET_UART
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ldr \rp, =MCS814X_PHYS_BASE
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ldr \rv, =MCS814X_VIRT_BASE
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orr \rp, \rp, #MCS814X_UART
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orr \rv, \rv, #MCS814X_UART
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.endm
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#define UART_SHIFT 2
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@ -20,15 +20,13 @@
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#define MCS814X_IRQ_MASK 0x20
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#define MCS814X_IRQ_STS0 0x40
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#define _PHYS_CONFADDR 0x40000000
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#define _VIRT_CONFADDR MCS814X_IO_BASE
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#define MCS814X_PHYS_BASE 0x40000000
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#define MCS814X_VIRT_BASE MCS814X_IO_BASE
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#define _CONFOFFSET_UART 0x000DC000
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#define _CONFOFFSET_DBGLED 0x000EC000
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#define _CONFOFFSET_SYSDBG 0x000F8000
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#define _CONFADDR_DBGLED (_VIRT_CONFADDR + _CONFOFFSET_DBGLED)
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#define _CONFADDR_SYSDBG (_VIRT_CONFADDR + _CONFOFFSET_SYSDBG)
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#define MCS814X_UART 0x000DC000
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#define MCS814X_DBGLED 0x000EC000
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#define MCS814X_SYSDBG 0x000F8000
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#define MCS814X_SYSDBG_SIZE 0x50
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/* System configuration and bootstrap registers */
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#define SYSDBG_BS1 0x00
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@ -46,6 +44,7 @@
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#define SYSDBG_SYSCTL 0x08
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#define SYSCTL_EMAC (1 << 0)
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#define SYSCTL_EPHY (1 << 1) /* active low */
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#define SYSCTL_CIPHER (1 << 16)
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#define SYSDBG_PLL_CTL 0x3C
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@ -32,7 +32,7 @@ static inline void flush(void)
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static inline void arch_decomp_setup(void)
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{
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if (soc_is_mcs8140())
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uart_base = (void __iomem *)(_PHYS_CONFADDR + _CONFOFFSET_UART);
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uart_base = (void __iomem *)(MCS814X_PHYS_BASE +MCS814X_UART);
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}
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#define arch_decomp_wdog()
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