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ramips: rt305x: rename SYSTEM_CONFIG_* defines to RT305X_SYSCFG_*
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30889 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -61,15 +61,15 @@
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#define CHIP_ID_ID_SHIFT 8
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#define CHIP_ID_REV_MASK 0xff
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#define SYSTEM_CONFIG_CPUCLK_SHIFT 18
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#define SYSTEM_CONFIG_CPUCLK_MASK 0x1
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#define SYSTEM_CONFIG_CPUCLK_320 0x0
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#define SYSTEM_CONFIG_CPUCLK_384 0x1
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_SHIFT 2
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_MASK 0x3
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_NORMAL 0
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_WDT 1
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_BTCOEX 2
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#define RT305X_SYSCFG_CPUCLK_SHIFT 18
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#define RT305X_SYSCFG_CPUCLK_MASK 0x1
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#define RT305X_SYSCFG_CPUCLK_LOW 0x0
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#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
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#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
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#define RT305X_SYSCFG_SRAM_CS0_MODE_MASK 0x3
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#define RT305X_SYSCFG_SRAM_CS0_MODE_NORMAL 0
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#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 1
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#define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX 2
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#define RT305X_GPIO_MODE_I2C BIT(0)
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#define RT305X_GPIO_MODE_SPI BIT(1)
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@ -33,13 +33,13 @@ void __init rt305x_clocks_init(void)
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u32 t;
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t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
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t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
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t = ((t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK);
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switch (t) {
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case SYSTEM_CONFIG_CPUCLK_320:
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case RT305X_SYSCFG_CPUCLK_LOW:
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rt305x_cpu_clk.rate = 320000000;
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break;
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case SYSTEM_CONFIG_CPUCLK_384:
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case RT305X_SYSCFG_CPUCLK_HIGH:
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rt305x_cpu_clk.rate = 384000000;
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break;
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}
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@ -229,8 +229,8 @@ void __init rt305x_register_wdt(void)
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/* enable WDT reset output on pin SRAM_CS_N */
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t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
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t |= SYSTEM_CONFIG_SRAM_CS0_MODE_WDT <<
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SYSTEM_CONFIG_SRAM_CS0_MODE_SHIFT;
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t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
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RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
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rt305x_sysc_wr(t, SYSC_REG_SYSTEM_CONFIG);
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platform_device_register(&rt305x_wdt_device);
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