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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-20 04:32:05 +03:00
fix asus deluxe serial console (broken by v4 support patch)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@1798 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -10576,8 +10576,8 @@ diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.
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+}
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diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
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--- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux.dev/arch/mips/bcm947xx/sbmips.c 2005-08-27 02:46:21.265608528 +0200
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@@ -0,0 +1,1036 @@
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+++ linux.dev/arch/mips/bcm947xx/sbmips.c 2005-08-30 14:47:52.836470168 +0200
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@@ -0,0 +1,1040 @@
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+/*
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+ * BCM47XX Sonics SiliconBackplane MIPS core routines
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+ *
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@ -10690,12 +10690,18 @@ diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbm
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+ div = 1;
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+ /* Set the override bit so we don't divide it */
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+ W_REG(&cc->corecontrol, CC_UARTCLKO);
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+ } else if ((rev >= 3) && (pll == PLL_TYPE6)) {
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+ /* Fixed ALP clock */
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+ baud_base = 20000000;
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+ div = 2;
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+ /* Set the override bit so we don't divide it */
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+ W_REG(&cc->corecontrol, CC_UARTCLKO);
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+ W_REG(&cc->clkdiv, ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
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+ } else if (rev >= 3) {
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+ /* Internal backplane clock */
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+ baud_base = sb_clock(sbh);
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+ div = 2; /* Minimum divisor */
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+ W_REG(&cc->clkdiv,
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+ ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
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+ W_REG(&cc->clkdiv, ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
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+ } else {
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+ /* Fixed internal backplane clock */
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+ baud_base = 88000000;
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@ -10960,14 +10966,13 @@ diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbm
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+ tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
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+ W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
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+ } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
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+
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+//==================================tallest===============================================
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+ /* set register for external IO to control LED. */
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+ W_REG(&cc->prog_config, 0x11);
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+ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
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+ tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
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+ tmp = tmp | CEIL(240, ns); /* W0 = 120nS */
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+ W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
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+ W_REG(&cc->prog_config, 0x11);
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+ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
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+ tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
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+ tmp = tmp | CEIL(240, ns); /* W0 = 120nS */
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+ W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
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+//========================================================================================
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+ /* Set timing for the flash */
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+ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
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@ -10990,7 +10995,7 @@ diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbm
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+ W_REG(&cc->pcmcia_memwait, tmp);
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+ }
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+ }
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+
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+
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+ // Added by Chen-I & Yen for enabling 5350 EXTIF
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+ if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
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+ {
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@ -11587,8 +11592,7 @@ diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbm
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+ if (config & MEMC_CONFIG_DDR) {
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+ ret = (wr << 16) | (rd << 8) | dqsg;
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+ } else {
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+ if ( (rev > 0) || (sb_chip(sbh) == BCM5365_DEVICE_ID))
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+
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+ if ((rev > 0) || (sb_chip(sbh) == BCM5365_DEVICE_ID))
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+ cd = rd;
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+ else
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+ cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
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@ -16453,8 +16457,8 @@ diff -urN linux.old/drivers/net/hnd/linux_osl.c linux.dev/drivers/net/hnd/linux_
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+#endif /* BINOSL */
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diff -urN linux.old/drivers/net/hnd/sbutils.c linux.dev/drivers/net/hnd/sbutils.c
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--- linux.old/drivers/net/hnd/sbutils.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux.dev/drivers/net/hnd/sbutils.c 2005-08-27 03:11:17.525240184 +0200
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@@ -0,0 +1,2064 @@
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+++ linux.dev/drivers/net/hnd/sbutils.c 2005-08-30 15:09:39.322854048 +0200
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@@ -0,0 +1,2063 @@
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+/*
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+ * Misc utility routines for accessing chip-specific features
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+ * of the SiliconBackplane-based Broadcom chips.
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@ -16466,7 +16470,7 @@ diff -urN linux.old/drivers/net/hnd/sbutils.c linux.dev/drivers/net/hnd/sbutils.
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+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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+ * $Id$
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+ * $Id: sbutils.c,v 1.6 2005/03/07 08:35:32 kanki Exp $
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+ */
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+
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+#include <typedefs.h>
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@ -16486,7 +16490,7 @@ diff -urN linux.old/drivers/net/hnd/sbutils.c linux.dev/drivers/net/hnd/sbutils.
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+#define SB_ERROR(args)
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+
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+
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+#define CLOCK_BASE_5350 12500000 /* Specific to 5350*/
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+#define CLOCK_BASE_5350 12500000 /* Specific to 5350*/
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+
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+typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
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+typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
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@ -17937,13 +17941,8 @@ diff -urN linux.old/drivers/net/hnd/sbutils.c linux.dev/drivers/net/hnd/sbutils.
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+ n = R_REG(&cc->clockcontrol_n);
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+ if (pll_type == PLL_TYPE6)
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+ m = R_REG(&cc->clockcontrol_mips);
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+ else if (pll_type == PLL_TYPE3)
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+ {
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+ // Added by Chen-I for 5365
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+ if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
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+ m = R_REG(&cc->clockcontrol_sb);
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+ else m = R_REG(&cc->clockcontrol_m2);
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+ }
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+ else if ((pll_type == PLL_TYPE3) && (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID))
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+ m = R_REG(&cc->clockcontrol_m2);
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+ else
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+ m = R_REG(&cc->clockcontrol_sb);
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+ } else {
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@ -17951,11 +17950,15 @@ diff -urN linux.old/drivers/net/hnd/sbutils.c linux.dev/drivers/net/hnd/sbutils.
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+ return 0;
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+ }
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+
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+ /* calculate rate */
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+ rate = sb_clock_rate(pll_type, n, m);
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+ if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) {
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+ rate = 100000000;
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+ } else {
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+ /* calculate rate */
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+ rate = sb_clock_rate(pll_type, n, m);
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+ if (pll_type == PLL_TYPE3)
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+ rate = rate / 2;
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+ }
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+
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+ if (pll_type == PLL_TYPE3)
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+ rate = rate / 2;
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+
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+ /* switch back to previous core */
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+ sb_setcoreidx(sbh, idx);
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