mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 00:50:50 +02:00
cleanup more ifxmips ssc reg acceses
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9844 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
6fe1883dc8
commit
2c0b4a4917
@ -205,7 +205,7 @@ rx_int (struct ifx_ssc_port *info)
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{
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disable_irq(info->rxirq);
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wake_up_interruptible (&info->rwait);
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} else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) == 0))
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} else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (readl(IFXMIPS_SSC_RXCNT) == 0))
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{
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if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
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writel((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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@ -523,13 +523,13 @@ ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_
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enable_irq(info->rxirq);
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} else {
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local_irq_restore(flags);
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if (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
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if (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
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return -EBUSY;
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enable_irq(info->rxirq);
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if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
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WRITE_PERIPHERAL_REGISTER (len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
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writel(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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else
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
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writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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}
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__add_wait_queue (&info->rwait, &wait);
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@ -720,7 +720,7 @@ ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
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info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
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info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
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info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
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tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
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tmp = readl(IFXMIPS_SSC_SFCON);
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info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
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info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
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@ -733,7 +733,7 @@ ifx_ssc_frm_control_get (struct ifx_ssc_port *info)
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{
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unsigned long tmp;
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tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
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tmp = readl(IFXMIPS_SSC_SFCON);
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info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
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info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
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info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
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@ -759,7 +759,7 @@ ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
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return -EINVAL;
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// read interrupt bits (they're not changed here)
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tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON) &
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tmp = readl(IFXMIPS_SSC_SFCON) &
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(IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
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// set all values with respect to it's bit position (for data and pause
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@ -771,7 +771,7 @@ ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
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tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
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tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
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WRITE_PERIPHERAL_REGISTER(tmp, info->mapbase + IFX_SSC_SFCON);
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writel(tmp, IFXMIPS_SSC_SFCON);
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return 0;
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}
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@ -784,12 +784,12 @@ ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val)
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if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
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return -EINVAL;
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if ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_BUSY)
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|| (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
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if ((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)
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|| (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
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return -EBUSY;
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tmp = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
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WRITE_PERIPHERAL_REGISTER (tmp, info->mapbase + IFX_SSC_CON);
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tmp = (readl(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
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writel(tmp, IFXMIPS_SSC_SFCON);
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info->opts.modeRxTx = val;
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return 0;
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@ -839,20 +839,20 @@ ifx_ssc_sethwopts (struct ifx_ssc_port *info)
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local_irq_save (flags);
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WRITE_PERIPHERAL_REGISTER (bits, info->mapbase + IFX_SSC_CON);
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WRITE_PERIPHERAL_REGISTER ((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
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(info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), info->mapbase + IFX_SSC_GPOCON);
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writel(bits, IFXMIPS_SSC_CON);
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writel((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
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(info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), IFXMIPS_SSC_GPOCON);
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WRITE_PERIPHERAL_REGISTER (info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, info->mapbase + IFX_SSC_WHBGPOSTAT);
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writel(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT);
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//master mode
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if (opts->masterSelect)
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_MASTER_SELECT, info->mapbase + IFX_SSC_WHBSTATE);
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writel(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
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else
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, info->mapbase + IFX_SSC_WHBSTATE);
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writel(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
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// init serial framing
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WRITE_PERIPHERAL_REGISTER (0, info->mapbase + IFX_SSC_SFCON);
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writel(0, IFXMIPS_SSC_SFCON);
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/* set up the port pins */
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//check for general requirements to switch (external) pad/pin characteristics
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/* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
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@ -896,23 +896,23 @@ ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud)
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local_irq_save (flags);
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enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
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enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
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writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
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wmb();
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if (br > 0xffff || ((br == 0) &&
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((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
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((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
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local_irq_restore (flags);
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printk ("%s: invalid baudrate %u\n", __func__, baud);
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return -EINVAL;
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}
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WRITE_PERIPHERAL_REGISTER (br, info->mapbase + IFX_SSC_BR);
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writel(br, IFXMIPS_SSC_BR);
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if (enabled)
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
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writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
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local_irq_restore(flags);
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@ -926,8 +926,8 @@ ifx_ssc_hwinit (struct ifx_ssc_port *info)
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unsigned long flags;
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bool enabled;
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enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
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enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
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writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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if (ifx_ssc_sethwopts (info) < 0)
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{
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@ -944,16 +944,14 @@ ifx_ssc_hwinit (struct ifx_ssc_port *info)
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local_irq_save (flags);
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/* TX FIFO */
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WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE,
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info->mapbase + IFX_SSC_TXFCON);
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writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
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/* RX FIFO */
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WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE,
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info->mapbase + IFX_SSC_RXFCON);
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writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
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local_irq_restore (flags);
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if (enabled)
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
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writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
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return 0;
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}
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@ -1001,8 +999,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
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/* if the buffers are not empty then the port is */
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/* busy and we shouldn't change things on-the-fly! */
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if (!info->txbuf || !info->rxbuf ||
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(READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
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& IFX_SSC_STATE_BUSY)) {
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(readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) {
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ret_val = -EBUSY;
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break;
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}
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@ -1043,7 +1040,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
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ret_val = ifx_ssc_rxtx_mode_set (info, tmp);
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break;
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case IFX_SSC_RXTX_MODE_GET:
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tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) &
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tmp = readl(IFXMIPS_SSC_CON) &
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(~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
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if (from_kernel)
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*((unsigned int *) data) = tmp;
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@ -1067,29 +1064,25 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
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if (tmp > IFX_SSC_MAX_GPO_OUT)
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ret_val = -EINVAL;
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else
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WRITE_PERIPHERAL_REGISTER
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(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
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info->mapbase + IFX_SSC_WHBGPOSTAT);
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writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
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IFXMIPS_SSC_WHBGPOSTAT);
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break;
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case IFX_SSC_GPO_OUT_CLR:
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if (from_kernel)
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tmp = *((unsigned long *) data);
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else if (copy_from_user ((void *) &tmp,
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(void *) data, sizeof (tmp))) {
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else if (copy_from_user ((void *) &tmp, (void *) data, sizeof (tmp))) {
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ret_val = -EFAULT;
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break;
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}
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if (tmp > IFX_SSC_MAX_GPO_OUT)
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ret_val = -EINVAL;
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else {
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WRITE_PERIPHERAL_REGISTER
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(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
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info->mapbase + IFX_SSC_WHBGPOSTAT);
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writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
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IFXMIPS_SSC_WHBGPOSTAT);
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}
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break;
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case IFX_SSC_GPO_OUT_GET:
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tmp = READ_PERIPHERAL_REGISTER
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(info->mapbase + IFX_SSC_GPOSTAT);
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tmp = readl(IFXMIPS_SSC_GPOSTAT);
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if (from_kernel)
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*((unsigned int *) data) = tmp;
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else if (copy_to_user ((void *) data,
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@ -1133,7 +1126,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
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/* if the buffers are not empty then the port is */
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/* busy and we shouldn't change things on-the-fly! */
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if (!info->txbuf || !info->rxbuf ||
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(READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
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(readl(IFXMIPS_SSC_STATE)
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& IFX_SSC_STATE_BUSY)) {
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ret_val = -EBUSY;
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break;
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@ -1142,8 +1135,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
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memcpy ((void *) &info->opts, (void *) data,
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sizeof (struct ifx_ssc_hwopts));
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else if (copy_from_user ((void *) &info->opts,
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(void *) data,
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sizeof (struct ifx_ssc_hwopts))) {
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(void *) data, sizeof(struct ifx_ssc_hwopts))) {
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ret_val = -EFAULT;
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break;
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}
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@ -1240,14 +1232,14 @@ ifx_ssc_init (void)
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info->errirq = IFXMIPS_SSC_EIR;
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}
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, info->mapbase + IFX_SSC_CLC);
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writel(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC);
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init_waitqueue_head (&info->rwait);
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local_irq_save (flags);
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// init serial framing register
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_SFCON, info->mapbase + IFX_SSC_SFCON);
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writel(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON);
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ret_val = request_irq(info->txirq, ifx_ssc_tx_int, SA_INTERRUPT, "ifx_ssc_tx", info);
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if (ret_val)
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@ -1272,7 +1264,7 @@ ifx_ssc_init (void)
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local_irq_restore (flags);
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goto irqerr;
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}
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_IRNEN, info->mapbase + IFX_SSC_IRN_EN);
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writel(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN);
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enable_irq(info->txirq);
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enable_irq(info->rxirq);
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@ -1308,7 +1300,7 @@ ifx_ssc_cleanup_module (void)
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int i;
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for (i = 0; i < PORT_CNT; i++) {
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, isp[i].mapbase + IFX_SSC_WHBSTATE);
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writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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free_irq(isp[i].txirq, &isp[i]);
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free_irq(isp[i].rxirq, &isp[i]);
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free_irq(isp[i].errirq, &isp[i]);
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