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synced 2024-08-21 12:35:32 +03:00
[ar71xx] reorganize PCI code
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16672 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -10,6 +10,8 @@
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obj-y := prom.o irq.o setup.o devices.o gpio.o ar71xx.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_AR71XX_MACH_AP81) += mach-ap81.o
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obj-$(CONFIG_AR71XX_MACH_AP83) += mach-ap83.o
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obj-$(CONFIG_AR71XX_MACH_AW_NR580) += mach-aw-nr580.o
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52
target/linux/ar71xx/files/arch/mips/ar71xx/pci.c
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52
target/linux/ar71xx/files/arch/mips/ar71xx/pci.c
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@ -0,0 +1,52 @@
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/*
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* Atheros AR71xx PCI setup code
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <asm/mach-ar71xx/ar71xx.h>
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#include <asm/mach-ar71xx/pci.h>
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unsigned ar71xx_pci_nr_irqs __initdata;
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struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata;
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int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev);
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static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
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{
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int err = 0;
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err = ar71xx_pci_be_handler(is_fixup);
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return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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if (ar71xx_pci_plat_dev_init)
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return ar71xx_pci_plat_dev_init(dev);
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return 0;
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
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{
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return ar71xx_pcibios_map_irq(dev, slot, pin);
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}
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int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
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{
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ar71xx_pci_nr_irqs = nr_irqs;
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ar71xx_pci_irq_map = map;
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board_be_handler = ar71xx_be_handler;
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return ar71xx_pci_bios_init();
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}
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@ -12,15 +12,11 @@
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/serial_8250.h>
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#include <linux/bootmem.h>
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#include <asm/bootinfo.h>
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#include <asm/traps.h>
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#include <asm/time.h> /* for mips_hpt_frequency */
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#include <asm/reboot.h> /* for _machine_{restart,halt} */
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#include <asm/mips_machine.h>
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@ -49,11 +45,6 @@ EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
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enum ar71xx_soc_type ar71xx_soc;
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EXPORT_SYMBOL_GPL(ar71xx_soc);
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int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
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struct ar71xx_pci_irq *map) __initdata;
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int (*ar71xx_pci_be_handler)(int is_fixup);
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static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
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static void ar71xx_restart(char *command)
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@ -70,24 +61,6 @@ static void ar71xx_halt(void)
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cpu_wait();
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}
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static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
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{
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int err = 0;
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if (ar71xx_pci_be_handler)
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err = ar71xx_pci_be_handler(is_fixup);
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return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
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}
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int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
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{
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if (!ar71xx_pci_bios_init)
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return 0;
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return ar71xx_pci_bios_init(nr_irqs, map);
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}
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static void __init ar71xx_detect_mem_size(void)
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{
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unsigned long size;
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@ -316,8 +289,6 @@ void __init plat_mem_setup(void)
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_machine_halt = ar71xx_halt;
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pm_power_off = ar71xx_halt;
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board_be_handler = ar71xx_be_handler;
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ar71xx_early_serial_setup();
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}
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@ -1,7 +1,7 @@
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/*
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* Atheros AR71xx SoC specific PCI definitions
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*
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -12,17 +12,24 @@
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#ifndef __ASM_MACH_AR71XX_PCI_H
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#define __ASM_MACH_AR71XX_PCI_H
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struct pci_dev;
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struct ar71xx_pci_irq {
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int irq;
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u8 slot;
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u8 pin;
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};
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extern int (*ar71xx_pci_be_handler)(int is_fixup);
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extern int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
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struct ar71xx_pci_irq *map) __initdata;
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extern int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev);
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extern unsigned ar71xx_pci_nr_irqs __initdata;
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extern struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata;
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extern int ar71xx_pci_init(unsigned nr_irqs,
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struct ar71xx_pci_irq *map) __init;
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int ar71xx_pcibios_map_irq(const struct pci_dev *dev,
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uint8_t slot, uint8_t pin) __init;
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int ar71xx_pcibios_init(void) __init;
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int ar71xx_pci_be_handler(int is_fixup);
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int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) __init;
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#endif /* __ASM_MACH_AR71XX_PCI_H */
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@ -1,7 +1,7 @@
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/*
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* Atheros AR71xx PCI host controller driver
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*
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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@ -36,10 +36,7 @@
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#define PCI_IDSEL_BASE 0
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#endif
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static unsigned ar71xx_pci_nr_irqs;
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static struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata;
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static void __iomem *ar71xx_pcicfg_base;
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static DEFINE_SPINLOCK(ar71xx_pci_lock);
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static inline void ar71xx_pci_delay(void)
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@ -93,7 +90,7 @@ static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
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return ret;
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}
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static int __ar71xx_pci_be_handler(int is_fixup)
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int ar71xx_pci_be_handler(int is_fixup)
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{
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u32 pci_err;
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u32 ahb_err;
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@ -135,7 +132,7 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
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ar71xx_pcicfg_wr(PCI_REG_CFG_CBE,
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cmd | ar71xx_pci_get_ble(where, size, 0));
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return __ar71xx_pci_be_handler(1);
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return ar71xx_pci_be_handler(1);
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}
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static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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@ -243,10 +240,10 @@ static void ar71xx_pci_fixup(struct pci_dev *dev)
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pci_write_config_word(dev, PCI_COMMAND, t);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
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int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
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int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
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uint8_t pin)
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{
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int irq = -1;
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int i;
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@ -274,11 +271,6 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
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return irq;
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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static struct pci_ops ar71xx_pci_ops = {
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.read = ar71xx_pci_read_config,
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.write = ar71xx_pci_write_config,
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@ -304,8 +296,7 @@ static struct pci_controller ar71xx_pci_controller = {
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.io_resource = &ar71xx_pci_io_resource,
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};
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static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
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struct ar71xx_pci_irq *map)
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int __init ar71xx_pcibios_init(void)
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{
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ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
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ar71xx_pci_delay();
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@ -328,20 +319,9 @@ static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
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ar71xx_pci_delay();
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/* clear bus errors */
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(void)__ar71xx_pci_be_handler(1);
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ar71xx_pci_nr_irqs = nr_irqs;
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ar71xx_pci_irq_map = map;
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ar71xx_pci_be_handler = __ar71xx_pci_be_handler;
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(void)ar71xx_pci_be_handler(1);
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register_pci_controller(&ar71xx_pci_controller);
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return 0;
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}
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static int __init __ar71xx_pci_init(void)
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{
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ar71xx_pci_bios_init = __ar71xx_pci_bios_init;
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return 0;
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}
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pure_initcall(__ar71xx_pci_init);
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