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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-19 19:38:04 +03:00
more fixes for the crazy cpu cache issues on brcm47xx-2.6 (mainly affects 4704) - turns out some of the previous fixes were incorrect and a coherency setup functions was missing
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7865 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
parent
1f9285016a
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51aeb843d0
@ -1,7 +1,7 @@
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Index: linux-2.6.22-rc4/arch/mips/kernel/genex.S
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Index: linux-2.6.22-rc6/arch/mips/kernel/genex.S
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===================================================================
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--- linux-2.6.22-rc4.orig/arch/mips/kernel/genex.S 2007-06-10 21:32:12.000000000 +0100
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+++ linux-2.6.22-rc4/arch/mips/kernel/genex.S 2007-06-10 21:33:19.000000000 +0100
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--- linux-2.6.22-rc6.orig/arch/mips/kernel/genex.S 2007-07-04 01:52:47.812492000 +0200
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+++ linux-2.6.22-rc6/arch/mips/kernel/genex.S 2007-07-04 01:53:01.585352750 +0200
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@@ -51,6 +51,10 @@
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NESTED(except_vec3_generic, 0, sp)
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.set push
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@ -13,10 +13,10 @@ Index: linux-2.6.22-rc4/arch/mips/kernel/genex.S
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#if R5432_CP0_INTERRUPT_WAR
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mfc0 k0, CP0_INDEX
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#endif
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Index: linux-2.6.22-rc4/arch/mips/mm/c-r4k.c
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Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
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===================================================================
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--- linux-2.6.22-rc4.orig/arch/mips/mm/c-r4k.c 2007-06-10 21:33:17.000000000 +0100
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+++ linux-2.6.22-rc4/arch/mips/mm/c-r4k.c 2007-06-10 21:33:19.000000000 +0100
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--- linux-2.6.22-rc6.orig/arch/mips/mm/c-r4k.c 2007-07-04 01:53:01.545350250 +0200
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+++ linux-2.6.22-rc6/arch/mips/mm/c-r4k.c 2007-07-04 02:17:11.435962750 +0200
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@@ -29,6 +29,9 @@
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#include <asm/cacheflush.h> /* for run_uncached() */
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@ -76,11 +76,28 @@ Index: linux-2.6.22-rc4/arch/mips/mm/c-r4k.c
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if (dc_lsize)
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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if (!cpu_icache_snoops_remote_store && scache_size)
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@@ -1173,6 +1190,15 @@
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@@ -1144,6 +1161,17 @@
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* silly idea of putting something else there ...
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*/
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switch (current_cpu_data.cputype) {
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+ case CPU_BCM3302:
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+ {
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+ u32 cm;
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+ cm = read_c0_diag();
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+ /* Enable icache */
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+ cm |= (1 << 31);
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+ /* Enable dcache */
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+ cm |= (1 << 30);
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+ write_c0_diag(cm);
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+ }
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+ break;
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case CPU_R4000PC:
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case CPU_R4000SC:
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case CPU_R4000MC:
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@@ -1174,6 +1202,15 @@
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/* Default cache error handler for R4000 and R5000 family */
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set_uncached_handler (0x100, &except_vec2_generic, 0x80);
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+
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+ /* Check if special workarounds are required */
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+#ifdef CONFIG_BCM947XX
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+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
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@ -89,13 +106,28 @@ Index: linux-2.6.22-rc4/arch/mips/mm/c-r4k.c
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+ } else
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+#endif
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+ bcm4710 = 0;
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+
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probe_pcache();
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setup_scache();
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Index: linux-2.6.22-rc4/arch/mips/mm/tlbex.c
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@@ -1219,5 +1256,13 @@
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build_clear_page();
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build_copy_page();
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local_r4k___flush_cache_all(NULL);
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+#ifdef CONFIG_BCM947XX
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+ {
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+ static void (*_coherency_setup)(void);
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+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
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+ _coherency_setup();
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+ }
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+#else
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coherency_setup();
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+#endif
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}
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Index: linux-2.6.22-rc6/arch/mips/mm/tlbex.c
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===================================================================
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--- linux-2.6.22-rc4.orig/arch/mips/mm/tlbex.c 2007-06-10 21:33:12.000000000 +0100
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+++ linux-2.6.22-rc4/arch/mips/mm/tlbex.c 2007-06-10 21:33:19.000000000 +0100
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--- linux-2.6.22-rc6.orig/arch/mips/mm/tlbex.c 2007-07-04 01:53:01.193328250 +0200
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+++ linux-2.6.22-rc6/arch/mips/mm/tlbex.c 2007-07-04 02:17:26.112880000 +0200
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@@ -1229,6 +1229,10 @@
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#endif
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}
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@ -107,23 +139,22 @@ Index: linux-2.6.22-rc4/arch/mips/mm/tlbex.c
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static void __init build_r4000_tlb_refill_handler(void)
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{
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u32 *p = tlb_handler;
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@@ -1243,6 +1247,12 @@
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@@ -1243,6 +1247,11 @@
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memset(relocs, 0, sizeof(relocs));
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memset(final_handler, 0, sizeof(final_handler));
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+#ifdef CONFIG_BCM947XX
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+ if (bcm4710) {
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+ if (current_cpu_data.cputype == CPU_BCM3302)
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+ i_nop(&p);
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+ }
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+#endif
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+
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+
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/*
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* create the plain linear handler
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*/
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Index: linux-2.6.22-rc4/include/asm-mips/r4kcache.h
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Index: linux-2.6.22-rc6/include/asm-mips/r4kcache.h
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===================================================================
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--- linux-2.6.22-rc4.orig/include/asm-mips/r4kcache.h 2007-06-10 21:32:12.000000000 +0100
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+++ linux-2.6.22-rc4/include/asm-mips/r4kcache.h 2007-06-10 21:33:19.000000000 +0100
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--- linux-2.6.22-rc6.orig/include/asm-mips/r4kcache.h 2007-07-04 01:52:47.840493750 +0200
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+++ linux-2.6.22-rc6/include/asm-mips/r4kcache.h 2007-07-04 01:53:01.673358250 +0200
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@@ -17,6 +17,20 @@
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#include <asm/cpu-features.h>
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#include <asm/mipsmtregs.h>
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@ -326,11 +357,11 @@ Index: linux-2.6.22-rc4/include/asm-mips/r4kcache.h
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+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
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#endif /* _ASM_R4KCACHE_H */
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Index: linux-2.6.22-rc4/include/asm-mips/stackframe.h
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Index: linux-2.6.22-rc6/include/asm-mips/stackframe.h
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===================================================================
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--- linux-2.6.22-rc4.orig/include/asm-mips/stackframe.h 2007-06-10 21:32:12.000000000 +0100
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+++ linux-2.6.22-rc4/include/asm-mips/stackframe.h 2007-06-10 21:33:19.000000000 +0100
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@@ -352,6 +352,10 @@
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--- linux-2.6.22-rc6.orig/include/asm-mips/stackframe.h 2007-07-04 01:52:47.852494500 +0200
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+++ linux-2.6.22-rc6/include/asm-mips/stackframe.h 2007-07-04 01:53:01.697359750 +0200
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@@ -350,6 +350,10 @@
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.macro RESTORE_SP_AND_RET
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LONG_L sp, PT_R29(sp)
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.set mips3
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@ -1,7 +1,7 @@
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Index: linux-2.6.22-rc5/arch/mips/mm/init.c
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Index: linux-2.6.22-rc6/arch/mips/mm/init.c
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===================================================================
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--- linux-2.6.22-rc5.orig/arch/mips/mm/init.c 2007-06-27 23:40:06.406545264 +0200
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+++ linux-2.6.22-rc5/arch/mips/mm/init.c 2007-06-27 23:40:08.920163136 +0200
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--- linux-2.6.22-rc6.orig/arch/mips/mm/init.c 2007-07-04 02:17:11.423962000 +0200
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+++ linux-2.6.22-rc6/arch/mips/mm/init.c 2007-07-04 02:17:31.269202250 +0200
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@@ -207,7 +207,7 @@
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void *vfrom, *vto;
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@ -29,10 +29,10 @@ Index: linux-2.6.22-rc5/arch/mips/mm/init.c
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void *vfrom =
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kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
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memcpy(dst, vfrom, len);
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Index: linux-2.6.22-rc5/include/asm-mips/mach-bcm947xx/cpu-feature-overrides.h
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Index: linux-2.6.22-rc6/include/asm-mips/mach-bcm947xx/cpu-feature-overrides.h
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ linux-2.6.22-rc5/include/asm-mips/mach-bcm947xx/cpu-feature-overrides.h 2007-06-27 23:40:08.921162984 +0200
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+++ linux-2.6.22-rc6/include/asm-mips/mach-bcm947xx/cpu-feature-overrides.h 2007-07-04 02:17:31.273202500 +0200
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@@ -0,0 +1,13 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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@ -47,10 +47,10 @@ Index: linux-2.6.22-rc5/include/asm-mips/mach-bcm947xx/cpu-feature-overrides.h
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+#define cpu_use_kmap_coherent 0
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+
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+#endif /* __ASM_MACH_BCM947XX_CPU_FEATURE_OVERRIDES_H */
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Index: linux-2.6.22-rc5/include/asm-mips/cpu-features.h
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Index: linux-2.6.22-rc6/include/asm-mips/cpu-features.h
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===================================================================
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--- linux-2.6.22-rc5.orig/include/asm-mips/cpu-features.h 2007-06-27 23:40:06.419543288 +0200
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+++ linux-2.6.22-rc5/include/asm-mips/cpu-features.h 2007-06-27 23:40:08.921162984 +0200
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--- linux-2.6.22-rc6.orig/include/asm-mips/cpu-features.h 2007-07-04 02:17:11.455964000 +0200
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+++ linux-2.6.22-rc6/include/asm-mips/cpu-features.h 2007-07-04 02:17:31.305204500 +0200
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@@ -101,6 +101,9 @@
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#ifndef cpu_has_pindexed_dcache
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#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
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@ -61,34 +61,3 @@ Index: linux-2.6.22-rc5/include/asm-mips/cpu-features.h
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/*
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* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
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Index: linux-2.6.22-rc5/arch/mips/mm/c-r4k.c
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===================================================================
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--- linux-2.6.22-rc5.orig/arch/mips/mm/c-r4k.c 2007-06-27 23:40:45.883543848 +0200
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+++ linux-2.6.22-rc5/arch/mips/mm/c-r4k.c 2007-06-27 23:42:06.682260576 +0200
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@@ -339,7 +339,7 @@
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static void r4k_flush_cache_all(void)
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{
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- if (!cpu_has_dc_aliases)
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+ if (!cpu_has_dc_aliases || !cpu_use_kmap_coherent)
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return;
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r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
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@@ -380,7 +380,7 @@
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static void r4k_flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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- if (!cpu_has_dc_aliases)
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+ if (!cpu_has_dc_aliases || !cpu_use_kmap_coherent)
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return;
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r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
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@@ -412,7 +412,7 @@
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static void r4k_flush_cache_mm(struct mm_struct *mm)
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{
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- if (!cpu_has_dc_aliases)
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+ if (!cpu_has_dc_aliases || !cpu_use_kmap_coherent)
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return;
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r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
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