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[ar71xx] improve SoC detection
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13349 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -44,6 +44,9 @@ EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
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u32 ar71xx_ddr_freq;
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EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
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enum ar71xx_soc_type ar71xx_soc;
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EXPORT_SYMBOL_GPL(ar71xx_soc);
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int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
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struct ar71xx_pci_irq *map) __initdata;
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@ -105,21 +108,35 @@ static void __init ar71xx_detect_sys_type(void)
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id = ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK;
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rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
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switch (id & REV_ID_CHIP_MASK) {
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case REV_ID_CHIP_AR7130:
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ar71xx_soc = AR71XX_SOC_AR7130;
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chip = "7130";
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break;
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case REV_ID_CHIP_AR7141:
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ar71xx_soc = AR71XX_SOC_AR7141;
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chip = "7141";
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break;
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case REV_ID_CHIP_AR7161:
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ar71xx_soc = AR71XX_SOC_AR7161;
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chip = "7161";
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break;
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case REV_ID_CHIP_AR9130:
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ar71xx_soc = AR71XX_SOC_AR9130;
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chip = "9130";
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break;
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case REV_ID_CHIP_AR9132:
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ar71xx_soc = AR71XX_SOC_AR9132;
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chip = "9132";
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break;
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default:
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chip = "71xx";
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panic("ar71xx: unknown chip id:0x%02x\n", id);
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}
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sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)",
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@ -152,11 +169,6 @@ static void __init ar71xx_detect_sys_frequency(void)
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u32 freq;
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u32 div;
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if ((ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK) >=
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REV_ID_CHIP_AR9130) {
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return ar91xx_detect_sys_frequency();
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}
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pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
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div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
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@ -172,6 +184,25 @@ static void __init ar71xx_detect_sys_frequency(void)
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ar71xx_ahb_freq = ar71xx_cpu_freq / div;
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}
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static void __init detect_sys_frequency(void)
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{
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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ar71xx_detect_sys_frequency();
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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ar91xx_detect_sys_frequency();
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break;
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default:
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BUG();
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}
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}
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#ifdef CONFIG_AR71XX_EARLY_SERIAL
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static void __init ar71xx_early_serial_setup(void)
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{
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@ -222,7 +253,7 @@ void __init plat_mem_setup(void)
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ar71xx_detect_mem_size();
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ar71xx_detect_sys_type();
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ar71xx_detect_sys_frequency();
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detect_sys_frequency();
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_machine_restart = ar71xx_restart;
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_machine_halt = ar71xx_halt;
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@ -92,6 +92,17 @@ extern u32 ar71xx_ahb_freq;
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extern u32 ar71xx_cpu_freq;
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extern u32 ar71xx_ddr_freq;
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enum ar71xx_soc_type {
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AR71XX_SOC_UNKNOWN,
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AR71XX_SOC_AR7130,
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AR71XX_SOC_AR7141,
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AR71XX_SOC_AR7161,
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AR71XX_SOC_AR9130,
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AR71XX_SOC_AR9132
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};
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extern enum ar71xx_soc_type ar71xx_soc;
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/*
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* PLL block
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*/
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@ -321,6 +332,7 @@ extern void ar71xx_ddr_flush(u32 reg);
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#define REV_ID_CHIP_AR7141 0xa1
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#define REV_ID_CHIP_AR7161 0xa2
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#define REV_ID_CHIP_AR9130 0xb0
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#define REV_ID_CHIP_AR9132 0xb1
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#define REV_ID_REVISION_MASK 0x3
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#define REV_ID_REVISION_SHIFT 2
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