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[brcm63xx] more fixes for bcm6338, no need not to prevent reads from MPI registers now that we have it defined correctly
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16589 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -45,11 +45,11 @@ static struct board_info board;
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static struct board_info __initdata board_96338gw = {
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.name = "96338GW",
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.expected_cpu_id = 0x6338,
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.has_enet0 = 1,
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.enet0 = {
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.has_phy = 1,
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.use_internal_phy = 1,
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.force_speed_100 = 1,
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.force_duplex_full = 1,
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},
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.has_ohci0 = 1,
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@ -58,8 +58,12 @@ static struct board_info __initdata board_96338gw = {
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static struct board_info __initdata board_96338w = {
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.name = "96338W",
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.expected_cpu_id = 0x6338,
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.has_enet0 = 1,
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.enet0 = {
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.force_speed_100 = 1,
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.force_duplex_full = 1,
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}
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};
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#endif
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@ -326,7 +330,7 @@ void __init board_prom_init(void)
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/* read base address of boot chip select (0)
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* 6338/6345 does not have MPI but boots from standard
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* MIPS Flash address */
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if (BCMCPU_IS_6338() || BCMCPU_IS_6345())
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if (BCMCPU_IS_6345())
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val = 0x1fc00000;
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else {
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val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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@ -554,7 +558,7 @@ int __init board_register_devices(void)
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#endif
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/* read base address of boot chip select (0) */
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if (BCMCPU_IS_6338() || BCMCPU_IS_6345())
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if (BCMCPU_IS_6345())
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val = 0x1fc0000;
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else {
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val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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@ -123,7 +123,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
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#define BCM_6338_PERF_BASE (0xfffe0000)
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#define BCM_6338_BB_BASE (0xdeadbeef)
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#define BCM_6338_BB_BASE (0xfffe0100)
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#define BCM_6338_TIMER_BASE (0xfffe0200)
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#define BCM_6338_WDT_BASE (0xfffe021c)
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#define BCM_6338_UART0_BASE (0xfffe0300)
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@ -132,9 +132,9 @@ enum bcm63xx_regs_set {
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#define BCM_6338_UDC0_BASE (0xdeadbeef)
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#define BCM_6338_USBDMA_BASE (0xfffe2400)
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#define BCM_6338_OHCI0_BASE (0xdeadbeef)
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#define BCM_6338_OHCI_PRIV_BASE (0xdeadbeef)
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#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
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#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6338_MPI_BASE (0xdeadbeef)
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#define BCM_6338_MPI_BASE (0xfffe3160)
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#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
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#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
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#define BCM_6338_DSL_BASE (0xfffe1000)
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@ -142,7 +142,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_UBUS_BASE (0xdeadbeef)
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#define BCM_6338_ENET0_BASE (0xfffe2800)
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#define BCM_6338_ENET1_BASE (0xdeadbeef)
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#define BCM_6338_ENETDMA_BASE (0xfffe3800)
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#define BCM_6338_ENETDMA_BASE (0xfffe2400)
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#define BCM_6338_EHCI0_BASE (0xdeadbeef)
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#define BCM_6338_SDRAM_BASE (0xfffe3100)
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#define BCM_6338_MEMC_BASE (0xdeadbeef)
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@ -15,12 +15,17 @@
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/* Clock Control register */
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#define PERF_CKCTL_REG 0x4
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#define CKCTL_6338_ADSLPHY_EN (1 << 0)
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#define CKCTL_6338_MPI_EN (1 << 1)
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#define CKCTL_6338_DRAM_EN (1 << 2)
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#define CKCTL_6338_ENET_EN (1 << 4)
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#define CKCTL_6338_USBS_EN (1 << 4)
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#define CKCTL_6338_SAR_EN (1 << 5)
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#define CKCTL_6338_SPI_EN (1 << 9)
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#define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ENET_EN | \
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#define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
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CKCTL_6338_MPI_EN | \
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CKCTL_6338_ENET_EN | \
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CKCTL_6338_SAR_EN | \
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CKCTL_6338_SPI_EN)
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