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bcm47xx: Rename all SSB_PLLRES_ to SSB_PMURES_
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14374 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
79ee2bdad6
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@ -13,7 +13,7 @@ Index: linux-2.6.28.2/drivers/ssb/Makefile
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Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c 2009-02-02 20:57:13.000000000 +0100
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+++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c 2009-02-02 20:59:48.000000000 +0100
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@@ -0,0 +1,481 @@
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+/*
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+ * Sonics Silicon Backplane
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@ -119,15 +119,15 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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+ switch (bus->chip_id) {
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+ case 0x4328:
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+ chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
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+ ~(1 << SSB_PLLRES_4328_BB_PLL_PU));
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+ ~(1 << SSB_PMURES_4328_BB_PLL_PU));
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+ chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
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+ ~(1 << SSB_PLLRES_4328_BB_PLL_PU));
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+ ~(1 << SSB_PMURES_4328_BB_PLL_PU));
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+ break;
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+ case 0x5354:
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+ chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
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+ ~(1 << SSB_PLLRES_5354_BB_PLL_PU));
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+ ~(1 << SSB_PMURES_5354_BB_PLL_PU));
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+ chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
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+ ~(1 << SSB_PLLRES_5354_BB_PLL_PU));
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+ ~(1 << SSB_PMURES_5354_BB_PLL_PU));
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+ break;
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+ default:
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+ SSB_WARN_ON(1);
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@ -260,11 +260,11 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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+ switch (bus->chip_id) {
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+ case 0x4325:
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+ chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
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+ ~((1 << SSB_PLLRES_4325_BBPLL_PWRSW_PU) |
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+ (1 << SSB_PLLRES_4325_HT_AVAIL)));
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+ ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
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+ (1 << SSB_PMURES_4325_HT_AVAIL)));
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+ chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
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+ ~((1 << SSB_PLLRES_4325_BBPLL_PWRSW_PU) |
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+ (1 << SSB_PLLRES_4325_HT_AVAIL)));
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+ ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
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+ (1 << SSB_PMURES_4325_HT_AVAIL)));
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+ /* Adjust the BBPLL to 2 on all channels later. */
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+ buffer_strength = 0x222222;
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+ break;
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@ -332,51 +332,51 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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+};
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+
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+static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4328a0[] = {
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+ { .resource = SSB_PLLRES_4328_EXT_SWITCHER_PWM, .updown = 0x0101, },
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+ { .resource = SSB_PLLRES_4328_BB_SWITCHER_PWM, .updown = 0x1F01, },
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+ { .resource = SSB_PLLRES_4328_BB_SWITCHER_BURST, .updown = 0x010F, },
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+ { .resource = SSB_PLLRES_4328_BB_EXT_SWITCHER_BURST, .updown = 0x0101, },
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+ { .resource = SSB_PLLRES_4328_ILP_REQUEST, .updown = 0x0202, },
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+ { .resource = SSB_PLLRES_4328_RADIO_SWITCHER_PWM, .updown = 0x0F01, },
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+ { .resource = SSB_PLLRES_4328_RADIO_SWITCHER_BURST, .updown = 0x0F01, },
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+ { .resource = SSB_PLLRES_4328_ROM_SWITCH, .updown = 0x0101, },
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+ { .resource = SSB_PLLRES_4328_PA_REF_LDO, .updown = 0x0F01, },
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+ { .resource = SSB_PLLRES_4328_RADIO_LDO, .updown = 0x0F01, },
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+ { .resource = SSB_PLLRES_4328_AFE_LDO, .updown = 0x0F01, },
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+ { .resource = SSB_PLLRES_4328_PLL_LDO, .updown = 0x0F01, },
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+ { .resource = SSB_PLLRES_4328_BG_FILTBYP, .updown = 0x0101, },
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+ { .resource = SSB_PLLRES_4328_TX_FILTBYP, .updown = 0x0101, },
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+ { .resource = SSB_PLLRES_4328_RX_FILTBYP, .updown = 0x0101, },
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+ { .resource = SSB_PLLRES_4328_XTAL_PU, .updown = 0x0101, },
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+ { .resource = SSB_PLLRES_4328_XTAL_EN, .updown = 0xA001, },
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+ { .resource = SSB_PLLRES_4328_BB_PLL_FILTBYP, .updown = 0x0101, },
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+ { .resource = SSB_PLLRES_4328_RF_PLL_FILTBYP, .updown = 0x0101, },
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+ { .resource = SSB_PLLRES_4328_BB_PLL_PU, .updown = 0x0701, },
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+ { .resource = SSB_PMURES_4328_EXT_SWITCHER_PWM, .updown = 0x0101, },
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+ { .resource = SSB_PMURES_4328_BB_SWITCHER_PWM, .updown = 0x1F01, },
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+ { .resource = SSB_PMURES_4328_BB_SWITCHER_BURST, .updown = 0x010F, },
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+ { .resource = SSB_PMURES_4328_BB_EXT_SWITCHER_BURST, .updown = 0x0101, },
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+ { .resource = SSB_PMURES_4328_ILP_REQUEST, .updown = 0x0202, },
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+ { .resource = SSB_PMURES_4328_RADIO_SWITCHER_PWM, .updown = 0x0F01, },
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+ { .resource = SSB_PMURES_4328_RADIO_SWITCHER_BURST, .updown = 0x0F01, },
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+ { .resource = SSB_PMURES_4328_ROM_SWITCH, .updown = 0x0101, },
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+ { .resource = SSB_PMURES_4328_PA_REF_LDO, .updown = 0x0F01, },
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+ { .resource = SSB_PMURES_4328_RADIO_LDO, .updown = 0x0F01, },
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+ { .resource = SSB_PMURES_4328_AFE_LDO, .updown = 0x0F01, },
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+ { .resource = SSB_PMURES_4328_PLL_LDO, .updown = 0x0F01, },
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+ { .resource = SSB_PMURES_4328_BG_FILTBYP, .updown = 0x0101, },
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+ { .resource = SSB_PMURES_4328_TX_FILTBYP, .updown = 0x0101, },
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+ { .resource = SSB_PMURES_4328_RX_FILTBYP, .updown = 0x0101, },
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+ { .resource = SSB_PMURES_4328_XTAL_PU, .updown = 0x0101, },
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+ { .resource = SSB_PMURES_4328_XTAL_EN, .updown = 0xA001, },
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+ { .resource = SSB_PMURES_4328_BB_PLL_FILTBYP, .updown = 0x0101, },
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+ { .resource = SSB_PMURES_4328_RF_PLL_FILTBYP, .updown = 0x0101, },
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+ { .resource = SSB_PMURES_4328_BB_PLL_PU, .updown = 0x0701, },
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+};
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+
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+static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4328a0[] = {
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+ {
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+ /* Adjust ILP Request to avoid forcing EXT/BB into burst mode. */
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+ .resource = SSB_PLLRES_4328_ILP_REQUEST,
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+ .resource = SSB_PMURES_4328_ILP_REQUEST,
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+ .task = PMU_RES_DEP_SET,
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+ .depend = ((1 << SSB_PLLRES_4328_EXT_SWITCHER_PWM) |
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+ (1 << SSB_PLLRES_4328_BB_SWITCHER_PWM)),
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+ .depend = ((1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
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+ (1 << SSB_PMURES_4328_BB_SWITCHER_PWM)),
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+ },
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+};
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+
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+static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4325a0[] = {
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+ { .resource = SSB_PLLRES_4325_XTAL_PU, .updown = 0x1501, },
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+ { .resource = SSB_PMURES_4325_XTAL_PU, .updown = 0x1501, },
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+};
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+
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+static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4325a0[] = {
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+ {
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+ /* Adjust HT-Available dependencies. */
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+ .resource = SSB_PLLRES_4325_HT_AVAIL,
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+ .resource = SSB_PMURES_4325_HT_AVAIL,
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+ .task = PMU_RES_DEP_ADD,
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+ .depend = ((1 << SSB_PLLRES_4325_RX_PWRSW_PU) |
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+ (1 << SSB_PLLRES_4325_TX_PWRSW_PU) |
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+ (1 << SSB_PLLRES_4325_LOGEN_PWRSW_PU) |
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+ (1 << SSB_PLLRES_4325_AFE_PWRSW_PU)),
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+ .depend = ((1 << SSB_PMURES_4325_RX_PWRSW_PU) |
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+ (1 << SSB_PMURES_4325_TX_PWRSW_PU) |
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+ (1 << SSB_PMURES_4325_LOGEN_PWRSW_PU) |
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+ (1 << SSB_PMURES_4325_AFE_PWRSW_PU)),
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+ },
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+};
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+
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@ -399,11 +399,11 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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+ break;
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+ case 0x4325:
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+ /* Power OTP down later. */
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+ min_msk = (1 << SSB_PLLRES_4325_CBUCK_BURST) |
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+ (1 << SSB_PLLRES_4325_LNLDO2_PU);
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+ min_msk = (1 << SSB_PMURES_4325_CBUCK_BURST) |
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+ (1 << SSB_PMURES_4325_LNLDO2_PU);
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+ if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) &
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+ SSB_CHIPCO_CHST_4325_PMUTOP_2B)
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+ min_msk |= (1 << SSB_PLLRES_4325_CLDO_CBUCK_BURST);
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+ min_msk |= (1 << SSB_PMURES_4325_CLDO_CBUCK_BURST);
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+ /* The PLL may turn on, if it decides so. */
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+ max_msk = 0xFFFFF;
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+ updown_tab = pmu_res_updown_tab_4325a0;
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@ -412,9 +412,9 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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+ depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4325a0);
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+ break;
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+ case 0x4328:
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+ min_msk = (1 << SSB_PLLRES_4328_EXT_SWITCHER_PWM) |
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+ (1 << SSB_PLLRES_4328_BB_SWITCHER_PWM) |
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+ (1 << SSB_PLLRES_4328_XTAL_EN);
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+ min_msk = (1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
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+ (1 << SSB_PMURES_4328_BB_SWITCHER_PWM) |
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+ (1 << SSB_PMURES_4328_XTAL_EN);
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+ /* The PLL may turn on, if it decides so. */
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+ max_msk = 0xFFFFF;
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+ updown_tab = pmu_res_updown_tab_4328a0;
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@ -531,7 +531,7 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon.c
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Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
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===================================================================
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--- linux-2.6.28.2.orig/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-01 13:22:59.000000000 +0100
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+++ linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-01 21:09:37.000000000 +0100
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+++ linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-02 21:00:08.000000000 +0100
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@@ -181,6 +181,16 @@
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#define SSB_CHIPCO_PROG_WAITCNT 0x0124
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#define SSB_CHIPCO_FLASH_CFG 0x0128
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@ -620,89 +620,89 @@ Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
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+#define SSB_PMU1_PLLCTL5 5
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+
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+/* BCM4312 PLL resource numbers. */
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+#define SSB_PLLRES_4312_SWITCHER_BURST 0
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+#define SSB_PLLRES_4312_SWITCHER_PWM 1
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+#define SSB_PLLRES_4312_PA_REF_LDO 2
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+#define SSB_PLLRES_4312_CORE_LDO_BURST 3
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+#define SSB_PLLRES_4312_CORE_LDO_PWM 4
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+#define SSB_PLLRES_4312_RADIO_LDO 5
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+#define SSB_PLLRES_4312_ILP_REQUEST 6
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+#define SSB_PLLRES_4312_BG_FILTBYP 7
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+#define SSB_PLLRES_4312_TX_FILTBYP 8
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+#define SSB_PLLRES_4312_RX_FILTBYP 9
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+#define SSB_PLLRES_4312_XTAL_PU 10
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+#define SSB_PLLRES_4312_ALP_AVAIL 11
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+#define SSB_PLLRES_4312_BB_PLL_FILTBYP 12
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+#define SSB_PLLRES_4312_RF_PLL_FILTBYP 13
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+#define SSB_PLLRES_4312_HT_AVAIL 14
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+#define SSB_PMURES_4312_SWITCHER_BURST 0
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+#define SSB_PMURES_4312_SWITCHER_PWM 1
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+#define SSB_PMURES_4312_PA_REF_LDO 2
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+#define SSB_PMURES_4312_CORE_LDO_BURST 3
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+#define SSB_PMURES_4312_CORE_LDO_PWM 4
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+#define SSB_PMURES_4312_RADIO_LDO 5
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+#define SSB_PMURES_4312_ILP_REQUEST 6
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+#define SSB_PMURES_4312_BG_FILTBYP 7
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+#define SSB_PMURES_4312_TX_FILTBYP 8
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+#define SSB_PMURES_4312_RX_FILTBYP 9
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+#define SSB_PMURES_4312_XTAL_PU 10
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+#define SSB_PMURES_4312_ALP_AVAIL 11
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+#define SSB_PMURES_4312_BB_PLL_FILTBYP 12
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+#define SSB_PMURES_4312_RF_PLL_FILTBYP 13
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+#define SSB_PMURES_4312_HT_AVAIL 14
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+
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+/* BCM4325 PLL resource numbers. */
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+#define SSB_PLLRES_4325_BUCK_BOOST_BURST 0
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+#define SSB_PLLRES_4325_CBUCK_BURST 1
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+#define SSB_PLLRES_4325_CBUCK_PWM 2
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+#define SSB_PLLRES_4325_CLDO_CBUCK_BURST 3
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+#define SSB_PLLRES_4325_CLDO_CBUCK_PWM 4
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+#define SSB_PLLRES_4325_BUCK_BOOST_PWM 5
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+#define SSB_PLLRES_4325_ILP_REQUEST 6
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+#define SSB_PLLRES_4325_ABUCK_BURST 7
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+#define SSB_PLLRES_4325_ABUCK_PWM 8
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+#define SSB_PLLRES_4325_LNLDO1_PU 9
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+#define SSB_PLLRES_4325_LNLDO2_PU 10
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+#define SSB_PLLRES_4325_LNLDO3_PU 11
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+#define SSB_PLLRES_4325_LNLDO4_PU 12
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+#define SSB_PLLRES_4325_XTAL_PU 13
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+#define SSB_PLLRES_4325_ALP_AVAIL 14
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+#define SSB_PLLRES_4325_RX_PWRSW_PU 15
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+#define SSB_PLLRES_4325_TX_PWRSW_PU 16
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+#define SSB_PLLRES_4325_RFPLL_PWRSW_PU 17
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+#define SSB_PLLRES_4325_LOGEN_PWRSW_PU 18
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+#define SSB_PLLRES_4325_AFE_PWRSW_PU 19
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+#define SSB_PLLRES_4325_BBPLL_PWRSW_PU 20
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+#define SSB_PLLRES_4325_HT_AVAIL 21
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+#define SSB_PMURES_4325_BUCK_BOOST_BURST 0
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+#define SSB_PMURES_4325_CBUCK_BURST 1
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+#define SSB_PMURES_4325_CBUCK_PWM 2
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+#define SSB_PMURES_4325_CLDO_CBUCK_BURST 3
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+#define SSB_PMURES_4325_CLDO_CBUCK_PWM 4
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+#define SSB_PMURES_4325_BUCK_BOOST_PWM 5
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+#define SSB_PMURES_4325_ILP_REQUEST 6
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+#define SSB_PMURES_4325_ABUCK_BURST 7
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+#define SSB_PMURES_4325_ABUCK_PWM 8
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+#define SSB_PMURES_4325_LNLDO1_PU 9
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+#define SSB_PMURES_4325_LNLDO2_PU 10
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+#define SSB_PMURES_4325_LNLDO3_PU 11
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+#define SSB_PMURES_4325_LNLDO4_PU 12
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+#define SSB_PMURES_4325_XTAL_PU 13
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+#define SSB_PMURES_4325_ALP_AVAIL 14
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+#define SSB_PMURES_4325_RX_PWRSW_PU 15
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+#define SSB_PMURES_4325_TX_PWRSW_PU 16
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+#define SSB_PMURES_4325_RFPLL_PWRSW_PU 17
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+#define SSB_PMURES_4325_LOGEN_PWRSW_PU 18
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+#define SSB_PMURES_4325_AFE_PWRSW_PU 19
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+#define SSB_PMURES_4325_BBPLL_PWRSW_PU 20
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+#define SSB_PMURES_4325_HT_AVAIL 21
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+
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+/* BCM4328 PLL resource numbers. */
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+#define SSB_PLLRES_4328_EXT_SWITCHER_PWM 0
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+#define SSB_PLLRES_4328_BB_SWITCHER_PWM 1
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+#define SSB_PLLRES_4328_BB_SWITCHER_BURST 2
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+#define SSB_PLLRES_4328_BB_EXT_SWITCHER_BURST 3
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+#define SSB_PLLRES_4328_ILP_REQUEST 4
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+#define SSB_PLLRES_4328_RADIO_SWITCHER_PWM 5
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+#define SSB_PLLRES_4328_RADIO_SWITCHER_BURST 6
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+#define SSB_PLLRES_4328_ROM_SWITCH 7
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+#define SSB_PLLRES_4328_PA_REF_LDO 8
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+#define SSB_PLLRES_4328_RADIO_LDO 9
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+#define SSB_PLLRES_4328_AFE_LDO 10
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+#define SSB_PLLRES_4328_PLL_LDO 11
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+#define SSB_PLLRES_4328_BG_FILTBYP 12
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+#define SSB_PLLRES_4328_TX_FILTBYP 13
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+#define SSB_PLLRES_4328_RX_FILTBYP 14
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+#define SSB_PLLRES_4328_XTAL_PU 15
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+#define SSB_PLLRES_4328_XTAL_EN 16
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+#define SSB_PLLRES_4328_BB_PLL_FILTBYP 17
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+#define SSB_PLLRES_4328_RF_PLL_FILTBYP 18
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+#define SSB_PLLRES_4328_BB_PLL_PU 19
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+#define SSB_PMURES_4328_EXT_SWITCHER_PWM 0
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+#define SSB_PMURES_4328_BB_SWITCHER_PWM 1
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+#define SSB_PMURES_4328_BB_SWITCHER_BURST 2
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+#define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST 3
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+#define SSB_PMURES_4328_ILP_REQUEST 4
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+#define SSB_PMURES_4328_RADIO_SWITCHER_PWM 5
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+#define SSB_PMURES_4328_RADIO_SWITCHER_BURST 6
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+#define SSB_PMURES_4328_ROM_SWITCH 7
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+#define SSB_PMURES_4328_PA_REF_LDO 8
|
||||
+#define SSB_PMURES_4328_RADIO_LDO 9
|
||||
+#define SSB_PMURES_4328_AFE_LDO 10
|
||||
+#define SSB_PMURES_4328_PLL_LDO 11
|
||||
+#define SSB_PMURES_4328_BG_FILTBYP 12
|
||||
+#define SSB_PMURES_4328_TX_FILTBYP 13
|
||||
+#define SSB_PMURES_4328_RX_FILTBYP 14
|
||||
+#define SSB_PMURES_4328_XTAL_PU 15
|
||||
+#define SSB_PMURES_4328_XTAL_EN 16
|
||||
+#define SSB_PMURES_4328_BB_PLL_FILTBYP 17
|
||||
+#define SSB_PMURES_4328_RF_PLL_FILTBYP 18
|
||||
+#define SSB_PMURES_4328_BB_PLL_PU 19
|
||||
+
|
||||
+/* BCM5354 PLL resource numbers. */
|
||||
+#define SSB_PLLRES_5354_EXT_SWITCHER_PWM 0
|
||||
+#define SSB_PLLRES_5354_BB_SWITCHER_PWM 1
|
||||
+#define SSB_PLLRES_5354_BB_SWITCHER_BURST 2
|
||||
+#define SSB_PLLRES_5354_BB_EXT_SWITCHER_BURST 3
|
||||
+#define SSB_PLLRES_5354_ILP_REQUEST 4
|
||||
+#define SSB_PLLRES_5354_RADIO_SWITCHER_PWM 5
|
||||
+#define SSB_PLLRES_5354_RADIO_SWITCHER_BURST 6
|
||||
+#define SSB_PLLRES_5354_ROM_SWITCH 7
|
||||
+#define SSB_PLLRES_5354_PA_REF_LDO 8
|
||||
+#define SSB_PLLRES_5354_RADIO_LDO 9
|
||||
+#define SSB_PLLRES_5354_AFE_LDO 10
|
||||
+#define SSB_PLLRES_5354_PLL_LDO 11
|
||||
+#define SSB_PLLRES_5354_BG_FILTBYP 12
|
||||
+#define SSB_PLLRES_5354_TX_FILTBYP 13
|
||||
+#define SSB_PLLRES_5354_RX_FILTBYP 14
|
||||
+#define SSB_PLLRES_5354_XTAL_PU 15
|
||||
+#define SSB_PLLRES_5354_XTAL_EN 16
|
||||
+#define SSB_PLLRES_5354_BB_PLL_FILTBYP 17
|
||||
+#define SSB_PLLRES_5354_RF_PLL_FILTBYP 18
|
||||
+#define SSB_PLLRES_5354_BB_PLL_PU 19
|
||||
+#define SSB_PMURES_5354_EXT_SWITCHER_PWM 0
|
||||
+#define SSB_PMURES_5354_BB_SWITCHER_PWM 1
|
||||
+#define SSB_PMURES_5354_BB_SWITCHER_BURST 2
|
||||
+#define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST 3
|
||||
+#define SSB_PMURES_5354_ILP_REQUEST 4
|
||||
+#define SSB_PMURES_5354_RADIO_SWITCHER_PWM 5
|
||||
+#define SSB_PMURES_5354_RADIO_SWITCHER_BURST 6
|
||||
+#define SSB_PMURES_5354_ROM_SWITCH 7
|
||||
+#define SSB_PMURES_5354_PA_REF_LDO 8
|
||||
+#define SSB_PMURES_5354_RADIO_LDO 9
|
||||
+#define SSB_PMURES_5354_AFE_LDO 10
|
||||
+#define SSB_PMURES_5354_PLL_LDO 11
|
||||
+#define SSB_PMURES_5354_BG_FILTBYP 12
|
||||
+#define SSB_PMURES_5354_TX_FILTBYP 13
|
||||
+#define SSB_PMURES_5354_RX_FILTBYP 14
|
||||
+#define SSB_PMURES_5354_XTAL_PU 15
|
||||
+#define SSB_PMURES_5354_XTAL_EN 16
|
||||
+#define SSB_PMURES_5354_BB_PLL_FILTBYP 17
|
||||
+#define SSB_PMURES_5354_RF_PLL_FILTBYP 18
|
||||
+#define SSB_PMURES_5354_BB_PLL_PU 19
|
||||
+
|
||||
+
|
||||
+
|
||||
|
Loading…
Reference in New Issue
Block a user