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bcm47xx: Implement 4312 and part of 4325 PLL init.
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14373 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -13,8 +13,8 @@ Index: linux-2.6.28.2/drivers/ssb/Makefile
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Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c 2009-02-01 21:16:15.000000000 +0100
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@@ -0,0 +1,378 @@
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+++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c 2009-02-02 20:57:13.000000000 +0100
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@@ -0,0 +1,481 @@
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+/*
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+ * Sonics Silicon Backplane
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+ * Broadcom ChipCommon Power Management Unit driver
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@ -176,11 +176,116 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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+ chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
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+}
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+
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+struct pmu1_plltab_entry {
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+ u16 freq; /* Crystal frequency in kHz.*/
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+ u8 xf; /* Crystal frequency value for PMU control */
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+ u8 ndiv_int;
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+ u32 ndiv_frac;
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+ u8 p1div;
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+ u8 p2div;
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+};
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+
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+static const struct pmu1_plltab_entry pmu1_plltab[] = {
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+ { .freq = 12000, .xf = 1, .p1div = 3, .p2div = 22, .ndiv_int = 0x9, .ndiv_frac = 0xFFFFEF, },
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+ { .freq = 13000, .xf = 2, .p1div = 1, .p2div = 6, .ndiv_int = 0xb, .ndiv_frac = 0x483483, },
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+ { .freq = 14400, .xf = 3, .p1div = 1, .p2div = 10, .ndiv_int = 0xa, .ndiv_frac = 0x1C71C7, },
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+ { .freq = 15360, .xf = 4, .p1div = 1, .p2div = 5, .ndiv_int = 0xb, .ndiv_frac = 0x755555, },
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+ { .freq = 16200, .xf = 5, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x6E9E06, },
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+ { .freq = 16800, .xf = 6, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x3CF3CF, },
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+ { .freq = 19200, .xf = 7, .p1div = 1, .p2div = 9, .ndiv_int = 0x5, .ndiv_frac = 0x17B425, },
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+ { .freq = 19800, .xf = 8, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0xA57EB, },
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+ { .freq = 20000, .xf = 9, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0, },
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+ { .freq = 24000, .xf = 10, .p1div = 3, .p2div = 11, .ndiv_int = 0xa, .ndiv_frac = 0, },
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+ { .freq = 25000, .xf = 11, .p1div = 5, .p2div = 16, .ndiv_int = 0xb, .ndiv_frac = 0, },
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+ { .freq = 26000, .xf = 12, .p1div = 1, .p2div = 2, .ndiv_int = 0x10, .ndiv_frac = 0xEC4EC4, },
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+ { .freq = 30000, .xf = 13, .p1div = 3, .p2div = 8, .ndiv_int = 0xb, .ndiv_frac = 0, },
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+ { .freq = 38400, .xf = 14, .p1div = 1, .p2div = 5, .ndiv_int = 0x4, .ndiv_frac = 0x955555, },
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+ { .freq = 40000, .xf = 15, .p1div = 1, .p2div = 2, .ndiv_int = 0xb, .ndiv_frac = 0, },
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+};
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+
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+#define SSB_PMU1_DEFAULT_XTALFREQ 15360
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+
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+static const struct pmu1_plltab_entry * pmu1_plltab_find_entry(u32 crystalfreq)
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+{
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+ const struct pmu1_plltab_entry *e;
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+ unsigned int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(pmu1_plltab); i++) {
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+ e = &pmu1_plltab[i];
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+ if (e->freq == crystalfreq)
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+ return e;
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+ }
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+
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+ return NULL;
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+}
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+
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+/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
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+static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc,
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+ u32 crystalfreq)
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+{
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+ WARN_ON(1);
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+ struct ssb_bus *bus = cc->dev->bus;
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+ const struct pmu1_plltab_entry *e = NULL;
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+ u32 buffer_strength = 0;
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+ u32 tmp, pllctl, pmuctl;
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+ unsigned int i;
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+
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+ if (bus->chip_id == 0x4312) {
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+ /* We do not touch the BCM4312 PLL and assume
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+ * the default crystal settings work out-of-the-box. */
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+ cc->pmu.crystalfreq = 20000;
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+ return;
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+ }
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+
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+ if (crystalfreq)
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+ e = pmu1_plltab_find_entry(crystalfreq);
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+ if (!e)
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+ e = pmu1_plltab_find_entry(SSB_PMU1_DEFAULT_XTALFREQ);
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+ BUG_ON(!e);
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+ crystalfreq = e->freq;
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+ cc->pmu.crystalfreq = e->freq;
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+
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+ /* Check if the PLL already is programmed to this frequency. */
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+ pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
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+ if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
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+ /* We're already there... */
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+ return;
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+ }
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+
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+ ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
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+ (crystalfreq / 1000), (crystalfreq % 1000));
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+
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+WARN_ON(1); //TODO not fully implemented, yet.
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+return;
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+ /* First turn the PLL off. */
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+ switch (bus->chip_id) {
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+ case 0x4325:
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+ chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
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+ ~((1 << SSB_PLLRES_4325_BBPLL_PWRSW_PU) |
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+ (1 << SSB_PLLRES_4325_HT_AVAIL)));
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+ chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
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+ ~((1 << SSB_PLLRES_4325_BBPLL_PWRSW_PU) |
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+ (1 << SSB_PLLRES_4325_HT_AVAIL)));
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+ /* Adjust the BBPLL to 2 on all channels later. */
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+ buffer_strength = 0x222222;
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+ break;
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+ default:
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+ SSB_WARN_ON(1);
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+ }
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+ for (i = 1500; i; i--) {
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+ tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
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+ if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
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+ break;
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+ udelay(10);
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+ }
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+ tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
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+ if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
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+ ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
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+
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+ /* Set p1div and p2div. */
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+ pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
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+ //TODO
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
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+
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+ //TODO
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+}
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+
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@ -370,8 +475,6 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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+ struct ssb_bus *bus = cc->dev->bus;
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+ u32 pmucap;
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+
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+if (bus->chip_id != 0x5354) return; //FIXME currently only 5354 code implemented.
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+
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+ if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
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+ return;
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+
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