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fix whitespaces

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9846 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic 2007-12-22 20:57:09 +00:00
parent f570d01618
commit 664450823b
1 changed files with 20 additions and 19 deletions
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39
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
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@ -351,24 +351,25 @@
#define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800)
#define IFXMIPS_SSC_CLC ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0000))
#define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
#define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
#define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
#define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
#define IFXMIPS_SSC_TB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0020))
#define IFXMIPS_SSC_RXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0030))
#define IFXMIPS_SSC_TXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0034))
#define IFXMIPS_SSC_CON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0010))
#define IFXMIPS_SSC_GPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0074))
#define IFXMIPS_SSC_RB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0024))
#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
#define IFXMIPS_SSC_GPOCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0070))
#define IFXMIPS_SSC_BR ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0040))
#define IFXMIPS_SSC_RXREQ ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0080))
#define IFXMIPS_SSC_SFSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0064))
#define IFXMIPS_SSC_CLC ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0000))
#define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
#define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
#define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
#define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
#define IFXMIPS_SSC_TB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0020))
#define IFXMIPS_SSC_RXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0030))
#define IFXMIPS_SSC_TXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0034))
#define IFXMIPS_SSC_CON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0010))
#define IFXMIPS_SSC_GPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0074))
#define IFXMIPS_SSC_RB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0024))
#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
#define IFXMIPS_SSC_GPOCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0070))
#define IFXMIPS_SSC_BR ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0040))
#define IFXMIPS_SSC_RXREQ ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0080))
#define IFXMIPS_SSC_SFSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0064))
#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
#endif