mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 02:48:37 +02:00
[lantiq]
* fix pci support for more than 1 device * fixes ioport mappings * adds support for arcor easybox 803/arv752DWP22 * gpio direction was not set properly during a gpio_request() * usb compile warning bugfix, cleanup, git-svn-id: svn://svn.openwrt.org/openwrt/trunk@25072 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
parent
c2b8621119
commit
67251bb1a5
@ -60,6 +60,7 @@ define Image/BuildKernel
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$(call Image/BuildKernel/Template,EASY50712,$(xway_cmdline))
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$(call Image/BuildKernel/Template,EASY50812,$(xway_cmdline))
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$(call Image/BuildKernel/Template,ARV452,$(xway_cmdline))
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$(call Image/BuildKernel/Template,ARV752DPW22,$(xway_cmdline))
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$(call Image/BuildKernel/Template,NONE)
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endef
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@ -68,6 +69,7 @@ define Image/Build
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$(call Image/Build/$(1),$(1),EASY50712)
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$(call Image/Build/$(1),$(1),EASY50812)
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$(call Image/Build/$(1),$(1),ARV452)
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$(call Image/Build/$(1),$(1),ARV752DPW22)
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$(call Image/Build/$(1),$(1),NONE)
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$(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).rootfs
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endef
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@ -97,7 +97,7 @@
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+#endif
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
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@@ -0,0 +1,36 @@
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@@ -0,0 +1,51 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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@ -122,15 +122,30 @@
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+ int mii_mode;
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+};
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+
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+/* struct used to pass info to the pci core */
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+enum {
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+ PCI_CLOCK_INT = 0,
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+ PCI_CLOCK_EXT
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+};
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+#define PCI_EXIN0 0x0001
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+#define PCI_EXIN1 0x0002
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+#define PCI_EXIN2 0x0004
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+#define PCI_EXIN_SHIFT 0
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+
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+#define PCI_GNT1 0x0008
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+#define PCI_GNT2 0x0010
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+#define PCI_GNT3 0x0020
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+#define PCI_GNT_SHIFT 3
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+
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+#define PCI_REQ1 0x0040
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+#define PCI_REQ2 0x0080
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+#define PCI_REQ3 0x0100
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+#define PCI_REQ_SHIFT 6
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+
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+#define PCI_CLOCK_INT 0
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+#define PCI_CLOCK_EXT 1
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+
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+struct lq_pci_data {
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+ int clock;
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+ int req_mask;
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+ int gpio;
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+ int irq[16];
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+};
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+
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+extern int (*ifxmips_pci_plat_dev_init)(struct pci_dev *dev);
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+
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+#endif
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@ -23,7 +23,7 @@
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+endif
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/gpio_ebu.c
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@@ -0,0 +1,107 @@
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@@ -0,0 +1,116 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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@ -54,13 +54,9 @@
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+}
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+
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+static void
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+lq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
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+lq_ebu_apply(void)
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+{
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+ unsigned long flags;
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+ if(value)
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+ shadow |= (1 << offset);
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+ else
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+ shadow &= ~(1 << offset);
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+ spin_lock_irqsave(&ebu_lock, flags);
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+ lq_w32(LQ_EBU_BUSCON, LQ_EBU_BUSCON1);
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+ *((__u16*)virt) = shadow;
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@ -68,6 +64,16 @@
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+ spin_unlock_irqrestore(&ebu_lock, flags);
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+}
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+
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+static void
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+lq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
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+{
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+ if(value)
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+ shadow |= (1 << offset);
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+ else
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+ shadow &= ~(1 << offset);
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+ lq_ebu_apply();
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+}
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+
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+static struct gpio_chip
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+lq_ebu_chip =
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+{
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@ -108,7 +114,10 @@
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+
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+ ret = gpiochip_add(&lq_ebu_chip);
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+ if (!ret)
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+ {
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+ lq_ebu_apply();
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+ return 0;
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+ }
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+
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+err_release_mem_region:
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+ release_mem_region(res->start, resource_size(res));
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@ -130,7 +139,7 @@
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+ return platform_driver_register(&lq_ebu_driver);
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+}
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+
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+arch_initcall(init_lq_ebu);
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+postcore_initcall(init_lq_ebu);
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/gpio_leds.c
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@@ -0,0 +1,161 @@
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@ -294,10 +303,10 @@
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+ return ret;
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+}
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+
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+arch_initcall(init_lq_stp);
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+postcore_initcall(init_lq_stp);
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/mach-easy4010.c
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@@ -0,0 +1,79 @@
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@@ -0,0 +1,82 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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@ -353,7 +362,10 @@
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+
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+static struct lq_pci_data lq_pci_data = {
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+ .clock = PCI_CLOCK_INT,
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+ .req_mask = 0xf,
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+ .gpio = PCI_GNT1 | PCI_REQ1,
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+ .irq = {
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+ [14] = INT_NUM_IM0_IRL0 + 22,
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+ },
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+};
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+
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+static struct lq_eth_data lq_eth_data = {
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@ -379,7 +391,7 @@
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+ easy4010_init);
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/mach-easy50712.c
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@@ -0,0 +1,79 @@
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@@ -0,0 +1,82 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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@ -435,7 +447,10 @@
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+
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+static struct lq_pci_data lq_pci_data = {
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+ .clock = PCI_CLOCK_INT,
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+ .req_mask = 0xf,
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+ .gpio = PCI_GNT1 | PCI_REQ1,
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+ .irq = {
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+ [14] = INT_NUM_IM0_IRL0 + 22,
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+ },
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+};
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+
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+static struct lq_eth_data lq_eth_data = {
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@ -461,7 +476,7 @@
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+ easy50712_init);
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/mach-easy50812.c
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@@ -0,0 +1,78 @@
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@@ -0,0 +1,81 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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@ -517,7 +532,10 @@
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+
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+static struct lq_pci_data lq_pci_data = {
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+ .clock = PCI_CLOCK_INT,
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+ .req_mask = 0xf,
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+ .gpio = PCI_GNT1 | PCI_REQ1,
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+ .irq = {
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+ [14] = INT_NUM_IM0_IRL0 + 22,
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+ },
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+};
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+
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+static struct lq_eth_data lq_eth_data = {
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@ -878,7 +896,7 @@
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+}
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/devices.h
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@@ -0,0 +1,24 @@
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@@ -0,0 +1,25 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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@ -891,6 +909,7 @@
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+#define _LQ_DEVICES_H__
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+
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+#include <lantiq_platform.h>
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+#include <xway_irq.h>
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+
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+extern void __init lq_register_gpio(void);
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+extern void __init lq_register_gpio_stp(void);
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@ -2867,7 +2886,7 @@
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+
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/gpio.c
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@@ -0,0 +1,203 @@
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@@ -0,0 +1,206 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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@ -2944,7 +2963,10 @@
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+ printk("failed to register %s gpio\n", name);
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+ return -EBUSY;
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+ }
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+ gpio_direction_output(pin, dir);
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+ if(dir)
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+ gpio_direction_output(pin, 1);
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+ else
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+ gpio_direction_input(pin);
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+ if(pin >= PINS_PER_PORT)
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+ {
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+ pin -= PINS_PER_PORT;
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@ -3070,7 +3092,7 @@
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+ return ret;
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+}
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+
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+arch_initcall(lq_gpio_init);
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+postcore_initcall(lq_gpio_init);
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/reset.c
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@@ -0,0 +1,53 @@
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@ -1,6 +1,6 @@
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--- a/arch/mips/lantiq/setup.c
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+++ b/arch/mips/lantiq/setup.c
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@@ -13,7 +13,8 @@
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@@ -12,7 +12,8 @@
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#include <linux/ioport.h>
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#include <lantiq.h>
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@ -10,7 +10,15 @@
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void __init
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plat_mem_setup(void)
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@@ -46,3 +47,25 @@ plat_mem_setup(void)
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@@ -31,6 +32,7 @@
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ioport_resource.end = IOPORT_RESOURCE_END;
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iomem_resource.start = IOMEM_RESOURCE_START;
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iomem_resource.end = IOMEM_RESOURCE_END;
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+ set_io_port_base((unsigned long) KSEG1);
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while (*envp)
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{
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@@ -45,3 +47,25 @@
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memsize *= 1024 * 1024;
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add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
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}
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@ -1,6 +1,6 @@
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--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capc
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@@ -55,6 +55,7 @@
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obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
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obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
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@ -140,7 +140,7 @@
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+}
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--- /dev/null
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+++ b/arch/mips/pci/pci-lantiq.c
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@@ -0,0 +1,293 @@
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@@ -0,0 +1,305 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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@ -181,19 +181,19 @@
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+#define PCI_CR_FCI_ADDR_MAP6 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8))
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+#define PCI_CR_FCI_ADDR_MAP7 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC))
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+#define PCI_CR_CLK_CTRL ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000))
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+#define PCI_CR_PCI_IRM ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0028))
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+#define PCI_CR_PCI_MOD ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030))
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+#define PCI_CR_PC_ARB ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080))
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+#define PCI_CR_FCI_ADDR_MAP11hg ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4))
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+#define PCI_CR_BAR11MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044))
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+#define PCI_CR_BAR12MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048))
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+#define PCI_CR_BAR13MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C))
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+#define PCI_CS_BASE_ADDR1 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
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+#define PCI_CR_PCI_ADDR_MAP11 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064))
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+#define PCI_CR_FCI_BURST_LENGTH ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8))
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+#define PCI_CR_PCI_EOI ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C))
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+
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+
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+#define PCI_CS_STS_CMD ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004))
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+#define PCI_CS_BASE_ADDR1 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
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+
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+#define PCI_MASTER0_REQ_MASK_2BITS 8
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+#define PCI_MASTER1_REQ_MASK_2BITS 10
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@ -210,10 +210,14 @@
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+
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+u32 lq_pci_mapped_cfg;
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+
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+int (*lqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
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+
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+/* Since the PCI REQ pins can be reused for other functionality, make it possible
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+ to exclude those from interpretation by the PCI controller */
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+static int lq_pci_req_mask = 0xf;
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+
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+static int *lq_pci_irq_map;
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+
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+struct pci_ops lq_pci_ops =
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+{
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+ .read = lq_pci_read_config_dword,
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@ -248,26 +252,9 @@
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+int
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+pcibios_plat_dev_init(struct pci_dev *dev)
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+{
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+ u8 pin;
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+ if (lqpci_plat_dev_init)
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+ return lqpci_plat_dev_init(dev);
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+
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+ pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
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+ switch(pin)
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+ {
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+ case 0:
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+ break;
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+ case 1:
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+ //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
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+ lq_w32(lq_r32(LQ_EBU_PCC_CON) | 0xc, LQ_EBU_PCC_CON);
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+ lq_w32(lq_r32(LQ_EBU_PCC_IEN) | 0x10, LQ_EBU_PCC_IEN);
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+ break;
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+ case 2:
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+ case 3:
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+ case 4:
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+ printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
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+ default:
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+ printk ("WARNING: invalid interrupt pin %d\n", pin);
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+ return 1;
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+ }
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+ return 0;
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+}
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+
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@ -283,13 +270,63 @@
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+ return bar11mask;
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+}
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+
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+struct ltq_pci_gpio_map {
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+ int pin;
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+ int alt0;
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+ int alt1;
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+ int dir;
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+ char *name;
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+};
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+
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+static struct ltq_pci_gpio_map gmap[] = {
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+ { 0, 1, 0, 0, "pci-exin0" },
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+ { 1, 1, 0, 0, "pci-exin1" },
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+ { 2, 1, 0, 0, "pci-exin2" },
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+ { 30, 1, 0, 1, "pci-gnt1" },
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+ { 23, 1, 0, 1, "pci-gnt2" },
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+ { 19, 1, 0, 1, "pci-gnt3" },
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+ { 29, 1, 0, 0, "pci-req1" },
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+ { 31, 1, 0, 0, "pci-req2" },
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+ { 3, 1, 0, 0, "pci-req3" },
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+};
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+
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+static void
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+lq_pci_setup_clk(int external_clock)
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+lq_pci_setup_gpio(int gpio)
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+{
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+ int i;
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+ for (i = 0; i < ARRAY_SIZE(gmap); i++)
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+ {
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+ if(gpio & (1 << i))
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+ {
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+ lq_gpio_request(gmap[i].pin, gmap[i].alt0,
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+ gmap[i].alt1, gmap[i].dir, gmap[i].name);
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+ }
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+ }
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+ lq_w32(lq_r32((u32*)0xBF101000) | 0x60, (u32*)0xBF101000);
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+ lq_w32(lq_r32((u32*)0xBF101004) & ~2, (u32*)0xBF101004);
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+ lq_w32(lq_r32((u32*)0xBF10100C) | 2, (u32*)0xBF10100C);
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+ for(i = 0; i < 3; i++)
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+ {
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+ if(gpio & (1 << i))
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+ {
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+ lq_w32(lq_r32((u32*)0xBF101000) | (0x6 << (i * 4)), (u32*)0xBF101000);
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+ lq_w32(lq_r32((u32*)0xBF101004) & ~(1 << i), (u32*)0xBF101004);
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+ lq_w32(lq_r32((u32*)0xBF10100C) | (1 << i), (u32*)0xBF10100C);
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+ }
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+ }
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+ lq_gpio_request(21, 0, 0, 1, "pci-reset");
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+ lq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & 0x7;
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+}
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+
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+static int __init
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+lq_pci_startup(struct lq_pci_data *conf)
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+{
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+ u32 temp_buffer;
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+
|
||||
+ /* set clock to 33Mhz */
|
||||
+ lq_w32(lq_r32(LQ_CGU_IFCCR) & ~0xf00000, LQ_CGU_IFCCR);
|
||||
+ lq_w32(lq_r32(LQ_CGU_IFCCR) | 0x800000, LQ_CGU_IFCCR);
|
||||
+ if (external_clock)
|
||||
+ if (conf->clock == PCI_CLOCK_EXT)
|
||||
+ {
|
||||
+ lq_w32(lq_r32(LQ_CGU_IFCCR) & ~(1 << 16), LQ_CGU_IFCCR);
|
||||
+ lq_w32((1 << 30), LQ_CGU_PCICR);
|
||||
@ -297,28 +334,9 @@
|
||||
+ lq_w32(lq_r32(LQ_CGU_IFCCR) | (1 << 16), LQ_CGU_IFCCR);
|
||||
+ lq_w32((1 << 31) | (1 << 30), LQ_CGU_PCICR);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+lq_pci_setup_gpio(void)
|
||||
+{
|
||||
+ /* PCI reset line is gpio driven */
|
||||
+ lq_gpio_request(21, 0, 0, 1, "pci-reset");
|
||||
+
|
||||
+ /* PCI_REQ line */
|
||||
+ lq_gpio_request(29, 1, 0, 0, "pci-req");
|
||||
+
|
||||
+ /* PCI_GNT line */
|
||||
+ lq_gpio_request(30, 1, 0, 1, "pci-gnt");
|
||||
+}
|
||||
+
|
||||
+static int __init
|
||||
+lq_pci_startup(void)
|
||||
+{
|
||||
+ u32 temp_buffer;
|
||||
+
|
||||
+ /* setup pci clock and gpis used by pci */
|
||||
+ lq_pci_setup_gpio();
|
||||
+ lq_pci_setup_gpio(conf->gpio);
|
||||
+
|
||||
+ /* enable auto-switching between PCI and EBU */
|
||||
+ lq_w32(0xa, PCI_CR_CLK_CTRL);
|
||||
@ -331,7 +349,8 @@
|
||||
+
|
||||
+ /* enable external 2 PCI masters */
|
||||
+ temp_buffer = lq_r32(PCI_CR_PC_ARB);
|
||||
+ temp_buffer &= (~(lq_pci_req_mask << 16));
|
||||
+ temp_buffer &= (~((lq_pci_req_mask & 0xf) << 16));
|
||||
+
|
||||
+ /* enable internal arbiter */
|
||||
+ temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
|
||||
+ /* enable internal PCI master reqest */
|
||||
@ -355,22 +374,28 @@
|
||||
+ lq_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
|
||||
+ lq_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
|
||||
+ lq_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
|
||||
+
|
||||
+ lq_w32(lq_calc_bar11mask(), PCI_CR_BAR11MASK);
|
||||
+ lq_w32(0, PCI_CR_PCI_ADDR_MAP11);
|
||||
+ lq_w32(0, PCI_CS_BASE_ADDR1);
|
||||
+#ifdef CONFIG_SWAP_IO_SPACE
|
||||
+
|
||||
+ /* both TX and RX endian swap are enabled */
|
||||
+ lq_w32(lq_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
|
||||
+ wmb ();
|
||||
+#endif
|
||||
+
|
||||
+ /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
|
||||
+ lq_w32(lq_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
|
||||
+ lq_w32(lq_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
|
||||
+ /*use 8 dw burst length */
|
||||
+
|
||||
+ /* use 8 dw burst length */
|
||||
+ lq_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
|
||||
+ lq_w32(lq_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
|
||||
+ wmb();
|
||||
+
|
||||
+ /* setup irq line */
|
||||
+ lq_w32(lq_r32(LQ_EBU_PCC_CON) | 0xc, LQ_EBU_PCC_CON);
|
||||
+ lq_w32(lq_r32(LQ_EBU_PCC_IEN) | 0x10, LQ_EBU_PCC_IEN);
|
||||
+
|
||||
+ /* toggle reset pin */
|
||||
+ __gpio_set_value(21, 0);
|
||||
+ wmb();
|
||||
@ -381,18 +406,10 @@
|
||||
+
|
||||
+int __init
|
||||
+pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
|
||||
+ switch(slot)
|
||||
+ {
|
||||
+ case 13:
|
||||
+ /* IDSEL = AD29 --> USB Host Controller */
|
||||
+ return (INT_NUM_IM1_IRL0 + 17);
|
||||
+ case 14:
|
||||
+ /* IDSEL = AD30 --> mini PCI connector */
|
||||
+ return (INT_NUM_IM0_IRL0 + 22);
|
||||
+ default:
|
||||
+ printk("lq_pci: no IRQ found for slot %d, pin %d\n", slot, pin);
|
||||
+ return 0;
|
||||
+ }
|
||||
+ if(lq_pci_irq_map[slot])
|
||||
+ return lq_pci_irq_map[slot];
|
||||
+ printk("lq_pci: trying to map irq for unknown slot %d\n", slot);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
@ -400,17 +417,12 @@
|
||||
+{
|
||||
+ struct lq_pci_data *lq_pci_data = (struct lq_pci_data*) pdev->dev.platform_data;
|
||||
+ extern int pci_probe_only;
|
||||
+
|
||||
+ pci_probe_only = 0;
|
||||
+ lq_pci_req_mask = lq_pci_data->req_mask;
|
||||
+ lq_pci_setup_clk(lq_pci_data->clock);
|
||||
+
|
||||
+ lq_pci_startup();
|
||||
+ lq_pci_mapped_cfg =
|
||||
+ (u32)ioremap_nocache(LQ_PCI_CFG_BASE, LQ_PCI_CFG_BASE);
|
||||
+ lq_pci_controller.io_map_base =
|
||||
+ (unsigned long)ioremap(LQ_PCI_IO_BASE, LQ_PCI_IO_SIZE - 1);
|
||||
+
|
||||
+ lq_pci_irq_map = lq_pci_data->irq;
|
||||
+ lq_pci_startup(lq_pci_data);
|
||||
+ lq_pci_mapped_cfg =
|
||||
+ (u32)ioremap_nocache(LQ_PCI_CFG_BASE, LQ_PCI_CFG_SIZE);
|
||||
+ lq_pci_controller.io_map_base = mips_io_port_base + LQ_PCI_IO_BASE;
|
||||
+ register_pci_controller(&lq_pci_controller);
|
||||
+ return 0;
|
||||
+}
|
||||
|
||||
@ -1,12 +1,13 @@
|
||||
--- a/arch/mips/include/asm/mach-lantiq/machine.h
|
||||
+++ b/arch/mips/include/asm/mach-lantiq/machine.h
|
||||
@@ -11,4 +11,7 @@
|
||||
@@ -11,4 +11,8 @@
|
||||
LANTIQ_MACH_EASY4010, /* Twinpass evalkit */
|
||||
LANTIQ_MACH_EASY50712, /* Danube evalkit */
|
||||
LANTIQ_MACH_EASY50812, /* AR9 eval board */
|
||||
+ LANTIQ_MACH_ARV4518, /* Airties WAV-221, SMC-7908A-ISP */
|
||||
+ LANTIQ_MACH_ARV452, /* Airties WAV-281, Arcor EasyboxA800 */
|
||||
+ LANTIQ_MACH_ARV4525, /* Speedport W502V */
|
||||
+ LANTIQ_MACH_ARV752DPW22, /* Arcor easybox a803 */
|
||||
};
|
||||
--- a/arch/mips/lantiq/xway/Kconfig
|
||||
+++ b/arch/mips/lantiq/xway/Kconfig
|
||||
@ -30,7 +31,7 @@
|
||||
+obj-$(CONFIG_LANTIQ_MACH_ARV45XX) += mach-arv45xx.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/lantiq/xway/mach-arv45xx.c
|
||||
@@ -0,0 +1,178 @@
|
||||
@@ -0,0 +1,268 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
@ -58,6 +59,7 @@
|
||||
+#include "devices.h"
|
||||
+
|
||||
+#define ARV452_LATCH_SWITCH (1 << 10)
|
||||
+#define ARV752DPW22_LATCH_DEFAULT (2)
|
||||
+
|
||||
+#ifdef CONFIG_MTD_PARTITIONS
|
||||
+static struct mtd_partition arv45xx_partitions[] =
|
||||
@ -92,9 +94,43 @@
|
||||
+#endif
|
||||
+};
|
||||
+
|
||||
+static struct mtd_partition arv75xx_partitions[] =
|
||||
+{
|
||||
+ {
|
||||
+ .name = "uboot",
|
||||
+ .offset = 0x0,
|
||||
+ .size = 0x40000,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "uboot_env",
|
||||
+ .offset = 0x40000,
|
||||
+ .size = 0x10000,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "linux",
|
||||
+ .offset = 0x50000,
|
||||
+ .size = 0x7a0000,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "board_config",
|
||||
+ .offset = 0x7f0000,
|
||||
+ .size = 0x10000,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct physmap_flash_data arv75xx_flash_data = {
|
||||
+#ifdef CONFIG_MTD_PARTITIONS
|
||||
+ .nr_parts = ARRAY_SIZE(arv75xx_partitions),
|
||||
+ .parts = arv75xx_partitions,
|
||||
+#endif
|
||||
+};
|
||||
+
|
||||
+static struct lq_pci_data lq_pci_data = {
|
||||
+ .clock = PCI_CLOCK_EXT,
|
||||
+ .req_mask = 0xf,
|
||||
+ .gpio = PCI_GNT1 | PCI_REQ1,
|
||||
+ .irq = {
|
||||
+ [14] = INT_NUM_IM0_IRL0 + 22,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct lq_eth_data lq_eth_data = {
|
||||
@ -144,6 +180,25 @@
|
||||
+ { .name = "soc:green:online", .gpio = 9, .active_low = 1, },
|
||||
+};
|
||||
+
|
||||
+static struct gpio_led
|
||||
+arv752dpw22_leds_gpio[] __initdata = {
|
||||
+ { .name = "soc:blue:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:red:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:red:power", .gpio = 6, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:red:wps", .gpio = 8, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:red:fxo", .gpio = 35, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:red:voice", .gpio = 36, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:green:usb", .gpio = 37, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:green:wlan", .gpio = 38, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:green:wlan1", .gpio = 39, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:blue:wlan", .gpio = 40, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:blue:wlan1", .gpio = 41, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:green:eth1", .gpio = 43, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:green:eth2", .gpio = 44, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:green:eth3", .gpio = 45, .active_low = 1, .default_trigger = "default-on" },
|
||||
+ { .name = "soc:green:eth4", .gpio = 46, .active_low = 1, .default_trigger = "default-on", },
|
||||
+};
|
||||
+
|
||||
+static void
|
||||
+arv45xx_register_ethernet(void)
|
||||
+{
|
||||
@ -153,6 +208,15 @@
|
||||
+ lq_register_ethernet(&lq_eth_data);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+arv75xx_register_ethernet(void)
|
||||
+{
|
||||
+#define ARV75XX_BRN_MAC 0x7f0016
|
||||
+ memcpy_fromio(lq_eth_data.mac,
|
||||
+ (void *)KSEG1ADDR(LQ_FLASH_START + ARV75XX_BRN_MAC), 6);
|
||||
+ lq_register_ethernet(&lq_eth_data);
|
||||
+}
|
||||
+
|
||||
+static void __init
|
||||
+arv4518_init(void)
|
||||
+{
|
||||
@ -209,3 +273,30 @@
|
||||
+ "ARV4525",
|
||||
+ "ARV4525 - Speedport W502V",
|
||||
+ arv4525_init);
|
||||
+
|
||||
+static void __init
|
||||
+arv752dpw22_init(void)
|
||||
+{
|
||||
+ lq_register_gpio();
|
||||
+ lq_register_gpio_ebu(ARV752DPW22_LATCH_DEFAULT);
|
||||
+ lq_register_asc(0);
|
||||
+ lq_register_asc(1);
|
||||
+ lq_register_gpio_leds(arv752dpw22_leds_gpio, ARRAY_SIZE(arv752dpw22_leds_gpio));
|
||||
+ lq_register_nor(&arv75xx_flash_data);
|
||||
+ lq_pci_data.irq[15] = (INT_NUM_IM2_IRL0 + 31);
|
||||
+ lq_pci_data.gpio |= PCI_EXIN1 | PCI_REQ2;
|
||||
+ lq_register_pci(&lq_pci_data);
|
||||
+ lq_register_wdt();
|
||||
+ arv75xx_register_ethernet();
|
||||
+ gpio_request(32, "usb-power");
|
||||
+ gpio_direction_output(32, 0);
|
||||
+ mdelay(1);
|
||||
+ __gpio_set_value(32, 1);
|
||||
+ gpio_request(33, "relay");
|
||||
+ gpio_direction_output(33, 1);
|
||||
+}
|
||||
+
|
||||
+MIPS_MACHINE(LANTIQ_MACH_ARV752DPW22,
|
||||
+ "ARV752DPW22",
|
||||
+ "ARV752DPW22 - Arcor A803",
|
||||
+ arv752dpw22_init);
|
||||
|
||||
@ -15580,7 +15580,7 @@
|
||||
+xway_register_dwc(int pin)
|
||||
+{
|
||||
+ lq_enable_irq(resources[1].start);
|
||||
+ platform_dev.dev.platform_data = pin;
|
||||
+ platform_dev.dev.platform_data = (void*) pin;
|
||||
+ return platform_device_register(&platform_dev);
|
||||
+}
|
||||
--- /dev/null
|
||||
@ -15612,8 +15612,8 @@
|
||||
+#include "dev-dwc_otg.h"
|
||||
|
||||
#define ARV452_LATCH_SWITCH (1 << 10)
|
||||
|
||||
@@ -132,6 +133,7 @@
|
||||
#define ARV752DPW22_LATCH_DEFAULT (2)
|
||||
@@ -195,6 +196,7 @@
|
||||
lq_register_pci(&lq_pci_data);
|
||||
lq_register_wdt();
|
||||
arv45xx_register_ethernet();
|
||||
@ -15621,7 +15621,7 @@
|
||||
}
|
||||
|
||||
MIPS_MACHINE(LANTIQ_MACH_ARV4518,
|
||||
@@ -151,6 +153,7 @@
|
||||
@@ -214,6 +216,7 @@
|
||||
lq_register_pci(&lq_pci_data);
|
||||
lq_register_wdt();
|
||||
arv45xx_register_ethernet();
|
||||
|
||||
@ -1,40 +0,0 @@
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-lantiq/pci.h
|
||||
@@ -0,0 +1,14 @@
|
||||
+/*
|
||||
+ * lantiq SoCs specific PCI definitions
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#ifndef __ASM_MACH_LANTIQ_PCI_H
|
||||
+#define __ASM_MACH_LANTIQ_PCI_H
|
||||
+
|
||||
+extern int (*ifxmips_pci_plat_dev_init)(struct pci_dev *dev);
|
||||
+
|
||||
+#endif
|
||||
--- a/arch/mips/pci/pci-lantiq.c
|
||||
+++ b/arch/mips/pci/pci-lantiq.c
|
||||
@@ -68,6 +68,8 @@
|
||||
|
||||
u32 lq_pci_mapped_cfg;
|
||||
|
||||
+int (*lqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
|
||||
+
|
||||
/* Since the PCI REQ pins can be reused for other functionality, make it possible
|
||||
to exclude those from interpretation by the PCI controller */
|
||||
static int lq_pci_req_mask = 0xf;
|
||||
@@ -126,6 +128,10 @@
|
||||
printk ("WARNING: invalid interrupt pin %d\n", pin);
|
||||
return 1;
|
||||
}
|
||||
+
|
||||
+ if (lqpci_plat_dev_init)
|
||||
+ return lqpci_plat_dev_init(dev);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -1,8 +1,10 @@
|
||||
CONFIG_AR8216_PHY=y
|
||||
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
CONFIG_HW_HAS_PCI=y
|
||||
CONFIG_IMAGE_CMDLINE_HACK=y
|
||||
# CONFIG_ISDN is not set
|
||||
CONFIG_LANTIQ_ETOP=y
|
||||
CONFIG_LANTIQ_MACH_ARV45XX=y
|
||||
CONFIG_LANTIQ_MACH_EASY4010=y
|
||||
@ -15,6 +17,7 @@ CONFIG_LEDS_GPIO=y
|
||||
# CONFIG_LOONGSON_MC146818 is not set
|
||||
CONFIG_LOONGSON_UART_BASE=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_RTL8306_PHY=y
|
||||
CONFIG_SCSI_MOD=y
|
||||
CONFIG_SOC_LANTIQ=y
|
||||
CONFIG_SOC_LANTIQ_XWAY=y
|
||||
|
||||
Loading…
Reference in New Issue
Block a user