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Code

[U_BOOT]add-2GB-nand-support.patch

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Signed-off-by: Xiangfu Liu <xiangfu.z@gmail.com>
This commit is contained in:
Xiangfu Liu 2009-07-25 11:55:48 +08:00 committed by Xiangfu Liu
parent 6633201340
commit 6be1b61490
2 changed files with 237 additions and 2 deletions
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5
target/linux/xburst/image/u-boot/Makefile
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@ -1,7 +1,8 @@
#
# Copyright (C) 2009 Qi hardware inc.,
# Copyright (C) 2009 Qi Hardware, Inc.
#
# This is free software, licensed under the GNU General Public License v3.
# This is free software, licensed under the GNU General Public License v3
# or any later.
# See /LICENSE for more information.
#

234
target/linux/xburst/image/u-boot/patches/0002-add-2GB-nand-support.patch Normal file
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@ -0,0 +1,234 @@
diff --git a/board/qi_lb60/qi_lb60.c b/board/qi_lb60/qi_lb60.c
index c23534d..572d22b 100644
--- a/board/qi_lb60/qi_lb60.c
+++ b/board/qi_lb60/qi_lb60.c
@@ -45,47 +45,44 @@ static void gpio_init(void)
__gpio_as_i2c();
/*
- * Initialize Other pins
+ * Initialize MSC pins
*/
-/* unsigned int i;
- __gpio_as_output( GPIO_AUDIO_POP );
- __gpio_set_pin( GPIO_AUDIO_POP );
-
+ __gpio_as_msc();
- for (i = 0; i < 8; i++){
- __gpio_as_output( GPIO_KEYOUT_BASE + i );
- __gpio_set_pin( GPIO_KEYOUT_BASE + i );
+ /*
+ * Initialize Other pins
+ */
+ unsigned int i;
+ for (i = 0; i < 8; i++) {
+ __gpio_as_output(GPIO_KEYOUT_BASE + i);
+ __gpio_set_pin(GPIO_KEYOUT_BASE + i);
}
for (i = 0; i < 7; i++){
- __gpio_as_input( GPIO_KEYIN_BASE + i );
- __gpio_enable_pull( GPIO_KEYIN_BASE + i );
+ __gpio_as_input(GPIO_KEYIN_BASE + i);
+ __gpio_enable_pull(GPIO_KEYIN_BASE + i);
}
+ /* __gpio_as_input( GPIO_KEYIN_8 ); */
+ /* __gpio_enable_pull( GPIO_KEYIN_8 ); */
- __gpio_as_input( GPIO_KEYIN_8 );
- __gpio_enable_pull( GPIO_KEYIN_8 );
-
-*/
- __gpio_as_output( GPIO_LCD_CS );
- __gpio_clear_pin( GPIO_LCD_CS );
+ __gpio_as_output(GPIO_AUDIO_POP);
+ __gpio_set_pin(GPIO_AUDIO_POP);
- __gpio_as_output( GPIO_AMP_EN );
- __gpio_clear_pin( GPIO_AMP_EN );
+ __gpio_as_output(GPIO_LCD_CS);
+ __gpio_clear_pin(GPIO_LCD_CS);
- __gpio_as_output( GPIO_SDPW_EN );
- __gpio_set_pin( GPIO_SDPW_EN );
+ __gpio_as_output(GPIO_AMP_EN);
+ __gpio_clear_pin(GPIO_AMP_EN);
- __gpio_as_input( GPIO_SD_DETECT );
- __gpio_enable_pull( GPIO_SD_DETECT );
+ __gpio_as_output(GPIO_SDPW_EN);
+ __gpio_disable_pull(GPIO_SDPW_EN);
+ __gpio_clear_pin(GPIO_SDPW_EN);
- __gpio_as_input( GPIO_USB_DETECT );
- __gpio_enable_pull( GPIO_USB_DETECT );
+ __gpio_as_input(GPIO_SD_DETECT);
+ __gpio_disable_pull(GPIO_SD_DETECT);
- /*
- * Initialize MSC pins
- */
- __gpio_as_msc();
- __gpio_set_pin(2 + 3 * 32);
+ __gpio_as_input(GPIO_USB_DETECT);
+ __gpio_enable_pull(GPIO_USB_DETECT);
}
void board_early_init(void)
diff --git a/cpu/mips/jz_mmc.c b/cpu/mips/jz_mmc.c
index 8a7c310..ec0a518 100644
--- a/cpu/mips/jz_mmc.c
+++ b/cpu/mips/jz_mmc.c
@@ -61,7 +61,7 @@ do { \
({ \
int detected = 1; \
__gpio_as_input(GPIO_SD_CD_N); \
- if (__gpio_get_pin(GPIO_SD_CD_N)) \
+ if (!__gpio_get_pin(GPIO_SD_CD_N)) \
detected = 0; \
detected; \
})
diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
index 68a2e87..1e13653 100644
--- a/include/configs/qi_lb60.h
+++ b/include/configs/qi_lb60.h
@@ -13,7 +13,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define DEBUG
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_JzRISC 1 /* JzRISC core */
#define CONFIG_JZSOC 1 /* Jz SoC */
@@ -23,16 +22,16 @@
#define CONFIG_DOS_PARTITION 1
#define CONFIG_PCMCIA_SLOT_A 1
-#define CONFIG_LCD 1 /* LCD support */
+#define CONFIG_LCD 1 /* LCD support */
#define LCD_BPP LCD_COLOR32/*5:18,24,32 bits per pixel */
#define CONFIG_JZLCD_FOXCONN_PT035TN01
/* NAND Boot config code */
#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
-#define CONFIG_CPU_SPEED 252000000 /* CPU clock: 252 MHz */
+#define CONFIG_CPU_SPEED 366000000 /* CPU clock: 366 MHz */
#define CONFIG_EXTAL 12000000 /* EXTAL freq: 12 MHz */
-#define CONFIG_SYS_HZ (CONFIG_EXTAL / 256) /* incrementer freq */
+#define CONFIG_SYS_HZ (CONFIG_EXTAL / 256) /* incrementer freq */
#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_CPU_SPEED
#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
@@ -46,16 +45,15 @@
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTFILE "uImage" /* file to load */
-#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw"
-#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
-#define CONFIG_AUTOLOAD "n" /* No autoload */
-
-#define CONFIG_DRIVER_CS8900 1
-#define CS8900_BASE (0xa8000000)
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage" /* file to load */
+#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw nohz=off"
+#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x300000;bootm"
+
+#define CONFIG_DRIVER_CS8900 1
+#define CS8900_BASE (0xa8000000)
#define CS8900_BUS16
-#define CONFIG_ETHADDR 00:2a:cc:2a:af:fe /* Ethernet address */
+#define CONFIG_ETHADDR 00:2a:cc:2a:af:fe /* Ethernet address */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@@ -92,10 +90,10 @@
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x80100000
-#define CONFIG_SYS_MEMTEST_END 0x80800000
+#define CONFIG_SYS_MEMTEST_END 0x80800000
#define CONFIG_RX_ETH_BUFFER 16 /* use 16 rx buffers on jz47xx eth */
@@ -107,17 +105,22 @@
/*
* NAND FLASH configuration
*/
-#define CONFIG_NAND_PAGE_SIZE 2048
-#define CONFIG_NAND_BLOCK_SIZE (256 << 10) /* NAND chip block size */
-#define CONFIG_NAND_BADBLOCK_PAGE 127
-/* NAND bad block was marked at this page in a block, starting from 0 */
-#define CONFIG_NAND_ECC_POS 6
-/* Ecc offset position in oob area, default value is 6 if it isn't defined. */
-
+#define QI_LB60_NAND_SIZE 2 /* if board nand flash is 1GB, set to 1
+ * if board nand flash is 2GB, set to 2
+ * this is for change the PAGE_SIZE and BLOCK_SIZE
+ * will delete when there is no 1GB flash in board
+ */
+
+#define CONFIG_NAND_PAGE_SIZE 2048 * QI_LB60_NAND_SIZE
+#define CONFIG_NAND_BLOCK_SIZE (256 * QI_LB60_NAND_SIZE << 10) /* nand chip block size */
+#define CONFIG_NAND_BADBLOCK_PAGE 127 /* nand bad block was marked at this page in a block,
+ * starting from 0 */
+#define CONFIG_NAND_ECC_POS 6 /* ECC offset position in oob area,
+ * default value is 6 if it isn't defined */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xB8000000
-#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips*/
+#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
/*
@@ -150,25 +153,8 @@
/* environment starts here */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-/*
- * NOR FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (128)/* max number of sectors on one chip */
-
-#define PHYS_FLASH_1 0xa8000000 /* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-/* in pi/config.mk TEXT_BAS=0x88000000 */
+/* in qi_lb60.h/config.mk TEXT_BAS = 0x88000000 */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-/* Reserve 256 kB for Monitor*/
-#define CONFIG_MONITOR_LEN (256*1024)
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/* timeout values are in ticks */
-#define CONFIG_FLASH_ERASE_TOUT (2 * CONFIG_HZ) /* Timeout for Flash Erase */
-#define CONFIG_FLASH_WRITE_TOUT (2 * CONFIG_HZ) /* Timeout for Flash Write */
/*
* SDRAM Info.
diff --git a/lib_mips/board.c b/lib_mips/board.c
index 539f78f..6a0e060 100644
--- a/lib_mips/board.c
+++ b/lib_mips/board.c
@@ -389,9 +389,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
size = flash_init();
display_flash_config (size);
bd->bi_flashsize = size;
+ bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
#endif
- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */
#else