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synced 2024-08-21 21:03:42 +03:00
[ar71xx] ag71xx: introduce SoC specific fuctions for DDR flush and PLL setup
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13369 3c298f89-4303-0410-b956-a3cf2f4a3e73
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7188638a39
@ -172,6 +172,79 @@ void __init ar71xx_add_device_mdio(u32 phy_mask)
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platform_device_register(&ar71xx_mdio_device);
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}
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static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
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{
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void __iomem *base;
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u32 t;
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base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
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t = __raw_readl(base + cfg_reg);
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t &= ~(3 << shift);
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t |= (2 << shift);
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__raw_writel(t, base + cfg_reg);
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udelay(100);
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__raw_writel(pll_val, base + pll_reg);
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t |= (3 << shift);
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__raw_writel(t, base + cfg_reg);
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udelay(100);
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t &= ~(3 << shift);
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__raw_writel(t, base + cfg_reg);
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udelay(100);
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printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
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(unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
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iounmap(base);
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}
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static void ar71xx_set_pll_ge0(u32 val)
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{
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
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val, AR71XX_ETH0_PLL_SHIFT);
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}
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static void ar71xx_set_pll_ge1(u32 val)
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{
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
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val, AR71XX_ETH1_PLL_SHIFT);
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}
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static void ar91xx_set_pll_ge0(u32 val)
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{
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ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
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val, AR91XX_ETH0_PLL_SHIFT);
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}
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static void ar91xx_set_pll_ge1(u32 val)
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{
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ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
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val, AR91XX_ETH1_PLL_SHIFT);
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}
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static void ar71xx_ddr_flush_ge0(void)
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{
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ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
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}
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static void ar71xx_ddr_flush_ge1(void)
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{
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ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
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}
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static void ar91xx_ddr_flush_ge0(void)
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{
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ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
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}
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static void ar91xx_ddr_flush_ge1(void)
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{
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ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
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}
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static struct resource ar71xx_eth0_resources[] = {
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{
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.name = "mac_base",
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@ -198,7 +271,6 @@ static struct resource ar71xx_eth0_resources[] = {
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struct ag71xx_platform_data ar71xx_eth0_data = {
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.reset_bit = RESET_MODULE_GE0_MAC,
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.flush_reg = AR71XX_DDR_REG_FLUSH_GE0,
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};
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static struct platform_device ar71xx_eth0_device = {
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@ -237,7 +309,6 @@ static struct resource ar71xx_eth1_resources[] = {
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struct ag71xx_platform_data ar71xx_eth1_data = {
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.reset_bit = RESET_MODULE_GE1_MAC,
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.flush_reg = AR71XX_DDR_REG_FLUSH_GE1,
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};
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static struct platform_device ar71xx_eth1_device = {
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@ -301,14 +372,35 @@ void __init ar71xx_add_device_eth(unsigned int id)
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pdata = pdev->dev.platform_data;
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
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: ar71xx_ddr_flush_ge0;
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pdata->set_pll = id ? ar71xx_set_pll_ge1
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: ar71xx_set_pll_ge0;
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break;
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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case AR71XX_SOC_AR9132:
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pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
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: ar71xx_ddr_flush_ge0;
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pdata->set_pll = id ? ar71xx_set_pll_ge1
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: ar71xx_set_pll_ge0;
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pdata->has_gbit = 1;
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break;
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR9130:
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pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
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: ar91xx_ddr_flush_ge0;
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pdata->set_pll = id ? ar91xx_set_pll_ge1
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: ar91xx_set_pll_ge0;
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break;
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case AR71XX_SOC_AR9132:
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pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
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: ar91xx_ddr_flush_ge0;
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pdata->set_pll = id ? ar91xx_set_pll_ge1
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: ar91xx_set_pll_ge0;
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pdata->has_gbit = 1;
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break;
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default:
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@ -319,7 +411,7 @@ void __init ar71xx_add_device_eth(unsigned int id)
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case PHY_INTERFACE_MODE_GMII:
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case PHY_INTERFACE_MODE_RGMII:
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if (!pdata->has_gbit) {
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printk(KERN_ERR "ar71xx: no gigabit available on eth%d\n",
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printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
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id);
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return;
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}
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@ -149,7 +149,7 @@ static void __init ar91xx_detect_sys_frequency(void)
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u32 freq;
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u32 div;
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pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
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pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
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freq = div * AR91XX_BASE_FREQ;
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@ -169,7 +169,7 @@ static void __init ar71xx_detect_sys_frequency(void)
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u32 freq;
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u32 div;
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pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
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pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
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freq = div * AR71XX_BASE_FREQ;
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@ -37,7 +37,7 @@
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#define ETH_FCS_LEN 4
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#define AG71XX_DRV_NAME "ag71xx"
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#define AG71XX_DRV_VERSION "0.4.4"
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#define AG71XX_DRV_VERSION "0.5.0"
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#define AG71XX_NAPI_TX 1
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@ -331,6 +331,8 @@ static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
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reg -= AG71XX_REG_MAC_IFCTL;
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ret = __raw_readl(ag->mac_base2 + reg);
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break;
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default:
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BUG();
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}
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return ret;
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@ -384,7 +384,7 @@ static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
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desc = &ring->descs[i];
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spin_lock_irqsave(&ag->lock, flags);
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ar71xx_ddr_flush(pdata->flush_reg);
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pdata->ddr_flush();
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spin_unlock_irqrestore(&ag->lock, flags);
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if (!ag71xx_desc_empty(desc))
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@ -480,7 +480,7 @@ static void ag71xx_tx_packets(struct ag71xx *ag)
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DBG("%s: processing TX ring\n", ag->dev->name);
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#ifdef AG71XX_NAPI_TX
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ar71xx_ddr_flush(pdata->flush_reg);
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pdata->ddr_flush();
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#endif
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sent = 0;
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@ -523,7 +523,7 @@ static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
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#ifndef AG71XX_NAPI_TX
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spin_lock_irqsave(&ag->lock, flags);
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ar71xx_ddr_flush(pdata->flush_reg);
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pdata->ddr_flush();
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spin_unlock_irqrestore(&ag->lock, flags);
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#endif
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@ -592,7 +592,7 @@ static int ag71xx_poll(struct napi_struct *napi, int limit)
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int done;
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#ifdef AG71XX_NAPI_TX
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ar71xx_ddr_flush(pdata->flush_reg);
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pdata->ddr_flush();
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ag71xx_tx_packets(ag);
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#endif
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@ -13,46 +13,6 @@
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#include "ag71xx.h"
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#define PLL_SEC_CONFIG 0x18050004
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#define PLL_ETH0_INT_CLOCK 0x18050010
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#define PLL_ETH1_INT_CLOCK 0x18050014
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#define PLL_ETH_EXT_CLOCK 0x18050018
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#define ag71xx_pll_shift(_ag) (((_ag)->pdev->id) ? 19 : 17)
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#define ag71xx_pll_offset(_ag) (((_ag)->pdev->id) ? PLL_ETH1_INT_CLOCK \
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: PLL_ETH0_INT_CLOCK)
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static void ag71xx_set_pll(struct ag71xx *ag, u32 pll_val)
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{
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void __iomem *pll_reg = ioremap_nocache(ag71xx_pll_offset(ag), 4);
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void __iomem *pll_cfg = ioremap_nocache(PLL_SEC_CONFIG, 4);
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u32 s;
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u32 t;
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s = ag71xx_pll_shift(ag);
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t = __raw_readl(pll_cfg);
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t &= ~(3 << s);
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t |= (2 << s);
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__raw_writel(t, pll_cfg);
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udelay(100);
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__raw_writel(pll_val, pll_reg);
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t |= (3 << s);
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__raw_writel(t, pll_cfg);
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udelay(100);
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t &= ~(3 << s);
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__raw_writel(t, pll_cfg);
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udelay(100);
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DBG("%s: pll_reg %#x: %#x\n", ag->dev->name,
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(unsigned int)pll_reg, __raw_readl(pll_reg));
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iounmap(pll_cfg);
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iounmap(pll_reg);
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}
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static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
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{
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switch (ag->speed) {
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@ -79,6 +39,7 @@ static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
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static void ag71xx_phy_link_update(struct ag71xx *ag)
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{
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
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u32 cfg2;
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u32 ifctl;
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u32 pll;
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@ -126,7 +87,7 @@ static void ag71xx_phy_link_update(struct ag71xx *ag)
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}
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
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ag71xx_set_pll(ag, pll);
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pdata->set_pll(pll);
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ag71xx_mii_ctrl_set_speed(ag, mii_speed);
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ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
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@ -106,13 +106,10 @@ extern enum ar71xx_soc_type ar71xx_soc;
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/*
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* PLL block
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*/
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#define PLL_REG_CPU_PLL_CFG 0x00
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#define PLL_REG_SEC_PLL_CFG 0x04
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#define PLL_REG_CPU_CLK_CTRL 0x08
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#define PLL_REG_ETH_INT0_CLK 0x10
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#define PLL_REG_ETH_INT1_CLK 0x14
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#define PLL_REG_ETH_EXT_CLK 0x18
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#define PLL_REG_PCI_CLK 0x1c
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#define AR71XX_PLL_REG_CPU_CONFIG 0x00
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#define AR71XX_PLL_REG_SEC_CONFIG 0x04
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#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
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#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
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#define AR71XX_PLL_DIV_SHIFT 3
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#define AR71XX_PLL_DIV_MASK 0x1f
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@ -123,6 +120,14 @@ extern enum ar71xx_soc_type ar71xx_soc;
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#define AR71XX_AHB_DIV_SHIFT 20
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#define AR71XX_AHB_DIV_MASK 0x7
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#define AR71XX_ETH0_PLL_SHIFT 17
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#define AR71XX_ETH1_PLL_SHIFT 19
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#define AR91XX_PLL_REG_CPU_CONFIG 0x00
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#define AR91XX_PLL_REG_ETH_CONFIG 0x04
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#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
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#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
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#define AR91XX_PLL_DIV_SHIFT 0
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#define AR91XX_PLL_DIV_MASK 0x3ff
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#define AR91XX_DDR_DIV_SHIFT 22
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@ -130,6 +135,9 @@ extern enum ar71xx_soc_type ar71xx_soc;
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#define AR91XX_AHB_DIV_SHIFT 19
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#define AR91XX_AHB_DIV_MASK 0x1
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#define AR91XX_ETH0_PLL_SHIFT 20
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#define AR91XX_ETH1_PLL_SHIFT 22
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extern void __iomem *ar71xx_pll_base;
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static inline void ar71xx_pll_wr(unsigned reg, u32 val)
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@ -25,11 +25,13 @@ struct ag71xx_platform_data {
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int speed;
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int duplex;
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u32 reset_bit;
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u32 flush_reg;
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u32 mii_if;
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u8 mac_addr[ETH_ALEN];
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u8 has_gbit:1;
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void (* ddr_flush)(void);
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void (* set_pll)(u32 pll);
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};
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struct ag71xx_mdio_platform_data {
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