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[ar71xx] ag71xx: introduce SoC specific fuctions for DDR flush and PLL setup

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13369 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
2008-11-26 20:00:41 +00:00
parent aedeeb1874
commit 7188638a39
7 changed files with 126 additions and 61 deletions
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22
target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
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@@ -106,13 +106,10 @@ extern enum ar71xx_soc_type ar71xx_soc;
/*
* PLL block
*/
#define PLL_REG_CPU_PLL_CFG 0x00
#define PLL_REG_SEC_PLL_CFG 0x04
#define PLL_REG_CPU_CLK_CTRL 0x08
#define PLL_REG_ETH_INT0_CLK 0x10
#define PLL_REG_ETH_INT1_CLK 0x14
#define PLL_REG_ETH_EXT_CLK 0x18
#define PLL_REG_PCI_CLK 0x1c
#define AR71XX_PLL_REG_CPU_CONFIG 0x00
#define AR71XX_PLL_REG_SEC_CONFIG 0x04
#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
#define AR71XX_PLL_DIV_SHIFT 3
#define AR71XX_PLL_DIV_MASK 0x1f
@@ -123,6 +120,14 @@ extern enum ar71xx_soc_type ar71xx_soc;
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
#define AR71XX_ETH0_PLL_SHIFT 17
#define AR71XX_ETH1_PLL_SHIFT 19
#define AR91XX_PLL_REG_CPU_CONFIG 0x00
#define AR91XX_PLL_REG_ETH_CONFIG 0x04
#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
#define AR91XX_PLL_DIV_SHIFT 0
#define AR91XX_PLL_DIV_MASK 0x3ff
#define AR91XX_DDR_DIV_SHIFT 22
@@ -130,6 +135,9 @@ extern enum ar71xx_soc_type ar71xx_soc;
#define AR91XX_AHB_DIV_SHIFT 19
#define AR91XX_AHB_DIV_MASK 0x1
#define AR91XX_ETH0_PLL_SHIFT 20
#define AR91XX_ETH1_PLL_SHIFT 22
extern void __iomem *ar71xx_pll_base;
static inline void ar71xx_pll_wr(unsigned reg, u32 val)

4
target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/platform.h
View File

@@ -25,11 +25,13 @@ struct ag71xx_platform_data {
int speed;
int duplex;
u32 reset_bit;
u32 flush_reg;
u32 mii_if;
u8 mac_addr[ETH_ALEN];
u8 has_gbit:1;
void (* ddr_flush)(void);
void (* set_pll)(u32 pll);
};
struct ag71xx_mdio_platform_data {