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[backfire] ar71xx: backport pci/dma fix from r21143
git-svn-id: svn://svn.openwrt.org/openwrt/branches/backfire@21207 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -21,6 +21,8 @@
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#include <asm/mach-ar71xx/ar71xx.h>
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static int ip2_flush_reg;
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static void ar71xx_gpio_irq_dispatch(void)
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{
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void __iomem *base = ar71xx_gpio_base;
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@ -239,8 +241,17 @@ asmlinkage void plat_irq_dispatch(void)
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if (pending & STATUSF_IP7)
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do_IRQ(AR71XX_CPU_IRQ_TIMER);
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else if (pending & STATUSF_IP2)
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else if (pending & STATUSF_IP2) {
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/*
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* This IRQ is meant for a PCI device. Drivers for PCI devices
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* typically allocate coherent DMA memory for the descriptor
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* ring, however the DMA controller may still have some
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* unsynchronized data in the FIFO.
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* Issue a flush here to ensure that the driver sees the update.
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*/
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ar71xx_ddr_flush(ip2_flush_reg);
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do_IRQ(AR71XX_CPU_IRQ_IP2);
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}
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else if (pending & STATUSF_IP4)
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do_IRQ(AR71XX_CPU_IRQ_GE0);
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@ -260,6 +271,20 @@ asmlinkage void plat_irq_dispatch(void)
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void __init arch_init_irq(void)
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{
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switch(ar71xx_soc) {
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case AR71XX_SOC_AR7240:
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC;
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break;
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default:
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ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
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break;
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}
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mips_cpu_irq_init();
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ar71xx_misc_irq_init();
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