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Code

added CONFIG_DANUBE_PCI_HW_SWAP

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9705 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic 2007-12-10 20:26:15 +00:00
parent 80484c3972
commit 77ce46e9f8
1 changed files with 17 additions and 2 deletions
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19
target/linux/danube/files/arch/mips/danube/pci.c
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@ -77,15 +77,25 @@ danube_pci_config_access(unsigned char access_type,
/* Perform access */ /* Perform access */
if (access_type == PCI_ACCESS_WRITE) if (access_type == PCI_ACCESS_WRITE)
{ {
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
writel(swab32(*data), ((u32*)cfg_base));
#else
writel(*data, ((u32*)cfg_base)); writel(*data, ((u32*)cfg_base));
#endif
} else { } else {
*data = readl(((u32*)(cfg_base))); *data = readl(((u32*)(cfg_base)));
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
*data = swab32(*data);
#endif
} }
wmb(); wmb();
/* clean possible Master abort */ /* clean possible Master abort */
cfg_base = (danube_pci_mapped_cfg | (0x0 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4; cfg_base = (danube_pci_mapped_cfg | (0x0 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
temp = readl(((u32*)(cfg_base))); temp = readl(((u32*)(cfg_base)));
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
temp = swab32 (temp);
#endif
cfg_base = (danube_pci_mapped_cfg | (0x68 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4; cfg_base = (danube_pci_mapped_cfg | (0x68 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
writel(temp, ((u32*)cfg_base)); writel(temp, ((u32*)cfg_base));
@ -250,9 +260,14 @@ static void __init danube_pci_startup (void){
writel(0x0e000008, PCI_CR_BAR11MASK); writel(0x0e000008, PCI_CR_BAR11MASK);
writel(0, PCI_CR_PCI_ADDR_MAP11); writel(0, PCI_CR_PCI_ADDR_MAP11);
writel(0, PCI_CS_BASE_ADDR1); writel(0, PCI_CS_BASE_ADDR1);
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
/* both TX and RX endian swap are enabled */
DANUBE_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
wmb ();
#endif
/*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */ /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
// writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK); writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
// writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK); writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
/*use 8 dw burse length */ /*use 8 dw burse length */
writel(0x303, PCI_CR_FCI_BURST_LENGTH); writel(0x303, PCI_CR_FCI_BURST_LENGTH);