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Prepare bcm63xx for SPI master support
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13547 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -81,6 +81,7 @@ enum bcm63xx_regs_set {
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#define RSET_ENET_SIZE 2048
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#define RSET_ENETDMA_SIZE 2048
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#define RSET_UART_SIZE 24
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#define RSET_SPI_SIZE 2048
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#define RSET_UDC_SIZE 256
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#define RSET_OHCI_SIZE 256
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#define RSET_EHCI_SIZE 256
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@ -249,6 +250,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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enum bcm63xx_irq {
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IRQ_TIMER = 0,
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IRQ_UART0,
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IRQ_SPI,
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IRQ_DSL,
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IRQ_ENET0,
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IRQ_ENET1,
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@ -268,6 +270,7 @@ enum bcm63xx_irq {
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* 6348 irqs
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*/
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#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
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#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
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#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
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#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
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#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
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@ -285,6 +288,7 @@ enum bcm63xx_irq {
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* 6358 irqs
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*/
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#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
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#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
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#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
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#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
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@ -724,5 +724,69 @@
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#define DMIPSPLLCFG_N2_SHIFT 29
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#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
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#endif /* BCM63XX_REGS_H_ */
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/*************************************************************************
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* _REG relative to RSET_SPI
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*************************************************************************/
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#define SPI_MSG_CTL 0x00
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#define SPI_FD_RW 0
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#define SPI_HD_W 1
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#define SPI_HD_R 2
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#define SPI_MSG_TYPE_SHIFT 14
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#define SPI_BYTE_CNT_SHIFT 0
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#define SPI_MSG_DATA 0x02
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#define SPI_MSG_DATA_SIZE 0x21e
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#define SPI_RX_FIFO 0x400
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#define SPI_RX_FIFO_SIZE 0x220
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#define SPI_CMD 0x700
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#define SPI_CMD_NOOP 0
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#define SPI_CMD_SOFT_RESET 1
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#define SPI_CMD_HARD_RESET 2
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#define SPI_CMD_START_IMMEDIATE 3
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#define SPI_CMD_COMMAND_SHIFT 0
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#define SPI_CMD_COMMAND_MASK 0x000f
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#define SPI_CMD_DEVICE_ID_SHIFT 4
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#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
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#define SPI_CMD_ONE_BYTE_SHIFT 11
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#define SPI_CMD_ONE_WIRE_SHIFT 12
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#define SPI_DEV_ID_0 0
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#define SPI_DEV_ID_1 1
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#define SPI_DEV_ID_2 2
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#define SPI_DEV_ID_3 3
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#define SPI_INT_STATUS 0x702
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#define SPI_MASK_INT_STATUS 0x703
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#define SPI_INT_MASK 0x704
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#define SPI_INTR_CMD_DONE 0x01
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#define SPI_INTR_RX_OVERFLOW 0x02
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#define SPI_INTR_INTR_TX_UNDERFLOW 0x04
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#define SPI_INTR_TX_OVERFLOW 0x08
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#define SPI_INTR_RX_UNDERFLOW 0x10
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#define SPI_INTR_CLEAR_ALL 0x1f
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#define SPI_STATUS 0x705
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#define SPI_RX_EMPTY 0x02
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#define SPI_CMD_BUSY 0x04
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#define SPI_SERIAL_BUSY 0x08
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#define SPI_CLK_CFG 0x706
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#define SPI_CLK_0_391MHZ 1
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#define SPI_CLK_0_781MHZ 2 /* default */
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#define SPI_CLK_1_563MHZ 3
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#define SPI_CLK_3_125MHZ 4
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#define SPI_CLK_6_250MHZ 5
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#define SPI_CLK_12_50MHZ 6
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#define SPI_CLK_MASK 0x07
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#define SPI_SSOFFTIME_MASK 0x38
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#define SPI_SSOFFTIME_SHIFT 3
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#define SPI_BYTE_SWAP 0x80
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#define SPI_FILL_BYTE 0x707
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#define SPI_MSG_TAIL 0x709
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#define SPI_RX_TAIL 0x70B
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#endif /* BCM63XX_REGS_H_ */
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