mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
initial merge of danube, pci is still broken and the new dma code still needs to be tested, before the merge
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9704 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
288
target/linux/danube/files/include/asm-mips/danube/danube.h
Normal file
288
target/linux/danube/files/include/asm-mips/danube/danube.h
Normal file
@@ -0,0 +1,288 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2005 infineon
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||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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*/
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#ifndef _DANUBE_H__
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#define _DANUBE_H__
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/*------------ GENERAL */
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#define BOARD_SYSTEM_TYPE "DANUBE"
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#define IOPORT_RESOURCE_START 0x10000000
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#define IOPORT_RESOURCE_END 0xffffffff
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#define IOMEM_RESOURCE_START 0x10000000
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#define IOMEM_RESOURCE_END 0xffffffff
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/*------------ ASC1 */
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#define DANUBE_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
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/* FIFO status register */
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#define DANUBE_ASC1_FSTAT ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0048))
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#define ASCFSTAT_TXFFLMASK 0x3F00
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#define ASCFSTAT_TXFFLOFF 8
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/* ASC1 transmit buffer */
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#define DANUBE_ASC1_TBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0020))
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/* channel operating modes */
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#define ASCOPT_CSIZE 0x3
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#define ASCOPT_CS7 0x1
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#define ASCOPT_CS8 0x2
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#define ASCOPT_PARENB 0x4
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#define ASCOPT_STOPB 0x8
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#define ASCOPT_PARODD 0x0
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#define ASCOPT_CREAD 0x20
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/* hardware modified control register */
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#define DANUBE_ASC1_WHBSTATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0018))
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/* receive buffer register */
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#define DANUBE_ASC1_RBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0024))
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/* status register */
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#define DANUBE_ASC1_STATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0014))
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/* interrupt control */
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#define DANUBE_ASC1_IRNCR ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F8))
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#define ASC_IRNCR_TIR 0x4
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#define ASC_IRNCR_RIR 0x2
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#define ASC_IRNCR_EIR 0x4
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/* clock control */
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#define DANUBE_ASC1_CLC ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0000))
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#define DANUBE_ASC1_CLC_DISS 0x2
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/* port input select register */
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#define DANUBE_ASC1_PISEL ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0004))
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/* tx fifo */
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#define DANUBE_ASC1_TXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0044))
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/* rx fifo */
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#define DANUBE_ASC1_RXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0040))
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/* control */
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#define DANUBE_ASC1_CON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0010))
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/* timer reload */
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#define DANUBE_ASC1_BG ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0050))
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/* int enable */
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#define DANUBE_ASC1_IRNREN ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F4))
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#define ASC_IRNREN_RX_BUF 0x8
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#define ASC_IRNREN_TX_BUF 0x4
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#define ASC_IRNREN_ERR 0x2
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#define ASC_IRNREN_TX 0x1
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/*------------ RCU */
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#define DANUBE_RCU_BASE_ADDR 0xBF203000
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/* reset request */
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#define DANUBE_RCU_REQ ((u32*)(DANUBE_RCU_BASE_ADDR + 0x0010))
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#define DANUBE_RST_ALL 0x40000000
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/*------------ MCD */
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#define DANUBE_MCD_BASE_ADDR (KSEG1 + 0x1F106000)
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/* chip id */
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#define DANUBE_MCD_CHIPID ((u32*)(DANUBE_MCD_BASE_ADDR + 0x0028))
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/*------------ GPTU */
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#define DANUBE_GPTU_BASE_ADDR 0xB8000300
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/* clock control register */
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#define DANUBE_GPTU_GPT_CLC ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0000))
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/* captur reload register */
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#define DANUBE_GPTU_GPT_CAPREL ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0030))
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/* timer 6 control register */
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#define DANUBE_GPTU_GPT_T6CON ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0020))
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/*------------ EBU */
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#define DANUBE_EBU_BASE_ADDR 0xBE105300
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/* bus configuration register */
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#define DANUBE_EBU_BUSCON0 ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0060))
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#define DANUBE_EBU_PCC_CON ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0090))
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#define DANUBE_EBU_PCC_IEN ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A4))
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#define DANUBE_EBU_PCC_ISTAT ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A0))
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/*------------ CGU */
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#define DANUBE_CGU_BASE_ADDR 0xBF103000
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/* clock mux */
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#define DANUBE_CGU_SYS ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0010))
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#define DANUBE_CGU_IFCCR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0018))
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#define DANUBE_CGU_PCICR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0034))
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#define CLOCK_60M 60000000
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#define CLOCK_83M 83333333
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#define CLOCK_111M 111111111
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#define CLOCK_133M 133333333
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#define CLOCK_167M 166666667
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#define CLOCK_333M 333333333
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/*------------ CGU */
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#define DANUBE_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
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/* power down control */
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#define DANUBE_PMU_PWDCR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C))
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#define DANUBE_PMU_PWDCR_DMA 0x20
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#define DANUBE_PMU_PWDCR_GPT 0x1000
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#define DANUBE_PMU_PWDCR_PPE 0x2000
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#define DANUBE_PMU_PWDCR_FPI 0x4000
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/*------------ ICU */
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#define DANUBE_ICU_BASE_ADDR 0xBF880200
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#define DANUBE_ICU_IM0_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0000))
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#define DANUBE_ICU_IM0_IER ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0008))
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#define DANUBE_ICU_IM0_IOSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0010))
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#define DANUBE_ICU_IM0_IRSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0018))
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#define DANUBE_ICU_IM0_IMR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0020))
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#define DANUBE_ICU_IM1_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0028))
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#define DANUBE_ICU_OFFSET (DANUBE_ICU_IM1_ISR - DANUBE_ICU_IM0_ISR)
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/*------------ ETOP */
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#define DANUBE_PPE32_BASE_ADDR 0xBE180000
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#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
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#define DANUBE_PPE32_MEM_MAP (DANUBE_PPE32_BASE_ADDR + 0x10000 )
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#define MII_MODE 1
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#define REV_MII_MODE 2
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/* mdio access */
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#define DANUBE_PPE32_MDIO_ACC ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1804))
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#define MDIO_ACC_REQUEST 0x80000000
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#define MDIO_ACC_READ 0x40000000
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#define MDIO_ACC_ADDR_MASK 0x1f
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#define MDIO_ACC_ADDR_OFFSET 0x15
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#define MDIO_ACC_REG_MASK 0xff
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#define MDIO_ACC_REG_OFFSET 0x10
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#define MDIO_ACC_VAL_MASK 0xffff
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/* configuration */
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#define DANUBE_PPE32_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1808))
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#define PPE32_MII_MASK 0xfffffffc
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#define PPE32_MII_NORMAL 0x8
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#define PPE32_MII_REVERSE 0xe
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/* packet length */
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#define DANUBE_PPE32_IG_PLEN_CTRL ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1820))
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#define PPE32_PLEN_OVER 0x5ee
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#define PPE32_PLEN_UNDER 0x400000
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/* enet */
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#define DANUBE_PPE32_ENET_MAC_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1840))
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#define PPE32_CGEN 0x800
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/*------------ DMA */
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#define DANUBE_DMA_BASE_ADDR 0xBE104100
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#define DANUBE_DMA_CS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x18))
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#define DANUBE_DMA_CIE ((u32*)(DANUBE_DMA_BASE_ADDR + 0x2C))
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#define DANUBE_DMA_IRNEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0xf4))
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#define DANUBE_DMA_CCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x1C))
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#define DANUBE_DMA_CIS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x28))
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#define DANUBE_DMA_CDLEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0x24))
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#define DANUBE_DMA_PS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x40))
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#define DANUBE_DMA_PCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x44))
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#define DANUBE_DMA_CTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x10))
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#define DANUBE_DMA_CPOLL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x14))
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#define DANUBE_DMA_CDBA ((u32*)(DANUBE_DMA_BASE_ADDR + 0x20))
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|
||||
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/*------------ PCI */
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#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
|
||||
|
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#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0))
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#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4))
|
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#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8))
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#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC))
|
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#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0))
|
||||
#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4))
|
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#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8))
|
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#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC))
|
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#define PCI_CR_CLK_CTRL ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000))
|
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#define PCI_CR_PCI_MOD ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030))
|
||||
#define PCI_CR_PC_ARB ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080))
|
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#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4))
|
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#define PCI_CR_BAR11MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044))
|
||||
#define PCI_CR_BAR12MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048))
|
||||
#define PCI_CR_BAR13MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C))
|
||||
#define PCI_CS_BASE_ADDR1 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010))
|
||||
#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064))
|
||||
#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8))
|
||||
#define PCI_CR_PCI_EOI ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C))
|
||||
|
||||
#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
|
||||
|
||||
#define PCI_CS_STS_CMD ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0004))
|
||||
|
||||
#define PCI_MASTER0_REQ_MASK_2BITS 8
|
||||
#define PCI_MASTER1_REQ_MASK_2BITS 10
|
||||
#define PCI_MASTER2_REQ_MASK_2BITS 12
|
||||
#define INTERNAL_ARB_ENABLE_BIT 0
|
||||
|
||||
|
||||
/*------------ GPIO */
|
||||
#define DANUBE_GPIO_BASE_ADDR 0xBE100B00
|
||||
|
||||
#define DANUBE_GPIO_P1_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040))
|
||||
#define DANUBE_GPIO_P1_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054))
|
||||
#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C))
|
||||
#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020))
|
||||
#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050))
|
||||
#define DANUBE_GPIO_P1_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048))
|
||||
|
||||
#endif
|
||||
202
target/linux/danube/files/include/asm-mips/danube/danube_dma.h
Normal file
202
target/linux/danube/files/include/asm-mips/danube/danube_dma.h
Normal file
@@ -0,0 +1,202 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2005 infineon
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
#ifndef _DANUBE_DMA_H__
|
||||
#define _DANUBE_DMA_H__
|
||||
|
||||
#define RCV_INT 1
|
||||
#define TX_BUF_FULL_INT 2
|
||||
#define TRANSMIT_CPT_INT 4
|
||||
#define DANUBE_DMA_CH_ON 1
|
||||
#define DANUBE_DMA_CH_OFF 0
|
||||
#define DANUBE_DMA_CH_DEFAULT_WEIGHT 100
|
||||
|
||||
enum attr_t{
|
||||
TX = 0,
|
||||
RX = 1,
|
||||
RESERVED = 2,
|
||||
DEFAULT = 3,
|
||||
};
|
||||
|
||||
#define DMA_OWN 1
|
||||
#define CPU_OWN 0
|
||||
#define DMA_MAJOR 250
|
||||
|
||||
#define DMA_DESC_OWN_CPU 0x0
|
||||
#define DMA_DESC_OWN_DMA 0x80000000
|
||||
#define DMA_DESC_CPT_SET 0x40000000
|
||||
#define DMA_DESC_SOP_SET 0x20000000
|
||||
#define DMA_DESC_EOP_SET 0x10000000
|
||||
|
||||
#define MISCFG_MASK 0x40
|
||||
#define RDERR_MASK 0x20
|
||||
#define CHOFF_MASK 0x10
|
||||
#define DESCPT_MASK 0x8
|
||||
#define DUR_MASK 0x4
|
||||
#define EOP_MASK 0x2
|
||||
|
||||
#define DMA_DROP_MASK (1<<31)
|
||||
|
||||
#define DANUBE_DMA_RX -1
|
||||
#define DANUBE_DMA_TX 1
|
||||
|
||||
typedef struct dma_chan_map {
|
||||
char dev_name[15];
|
||||
enum attr_t dir;
|
||||
int pri;
|
||||
int irq;
|
||||
int rel_chan_no;
|
||||
} _dma_chan_map;
|
||||
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
typedef struct rx_desc{
|
||||
u32 data_length:16;
|
||||
volatile u32 reserved:7;
|
||||
volatile u32 byte_offset:2;
|
||||
volatile u32 Burst_length_offset:3;
|
||||
volatile u32 EoP:1;
|
||||
volatile u32 Res:1;
|
||||
volatile u32 C:1;
|
||||
volatile u32 OWN:1;
|
||||
volatile u32 Data_Pointer;
|
||||
/*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/
|
||||
}_rx_desc;
|
||||
|
||||
typedef struct tx_desc{
|
||||
volatile u32 data_length:16;
|
||||
volatile u32 reserved1:7;
|
||||
volatile u32 byte_offset:5;
|
||||
volatile u32 EoP:1;
|
||||
volatile u32 SoP:1;
|
||||
volatile u32 C:1;
|
||||
volatile u32 OWN:1;
|
||||
volatile u32 Data_Pointer;//fix me:should be 28 bits here
|
||||
}_tx_desc;
|
||||
#else //BIG
|
||||
typedef struct rx_desc{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
volatile u32 OWN:1;
|
||||
volatile u32 C:1;
|
||||
volatile u32 SoP:1;
|
||||
volatile u32 EoP:1;
|
||||
volatile u32 Burst_length_offset:3;
|
||||
volatile u32 byte_offset:2;
|
||||
volatile u32 reserve:7;
|
||||
volatile u32 data_length:16;
|
||||
}field;
|
||||
volatile u32 word;
|
||||
}status;
|
||||
volatile u32 Data_Pointer;
|
||||
}_rx_desc;
|
||||
|
||||
typedef struct tx_desc{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
volatile u32 OWN:1;
|
||||
volatile u32 C:1;
|
||||
volatile u32 SoP:1;
|
||||
volatile u32 EoP:1;
|
||||
volatile u32 byte_offset:5;
|
||||
volatile u32 reserved:7;
|
||||
volatile u32 data_length:16;
|
||||
}field;
|
||||
volatile u32 word;
|
||||
}status;
|
||||
volatile u32 Data_Pointer;
|
||||
}_tx_desc;
|
||||
#endif //ENDIAN
|
||||
|
||||
typedef struct dma_channel_info{
|
||||
/*relative channel number*/
|
||||
int rel_chan_no;
|
||||
/*class for this channel for QoS*/
|
||||
int pri;
|
||||
/*specify byte_offset*/
|
||||
int byte_offset;
|
||||
/*direction*/
|
||||
int dir;
|
||||
/*irq number*/
|
||||
int irq;
|
||||
/*descriptor parameter*/
|
||||
int desc_base;
|
||||
int desc_len;
|
||||
int curr_desc;
|
||||
int prev_desc;/*only used if it is a tx channel*/
|
||||
/*weight setting for WFQ algorithm*/
|
||||
int weight;
|
||||
int default_weight;
|
||||
int packet_size;
|
||||
int burst_len;
|
||||
/*on or off of this channel*/
|
||||
int control;
|
||||
/**optional information for the upper layer devices*/
|
||||
#if defined(CONFIG_DANUBE_ETHERNET_D2) || defined(CONFIG_DANUBE_PPA)
|
||||
void* opt[64];
|
||||
#else
|
||||
void* opt[25];
|
||||
#endif
|
||||
/*Pointer to the peripheral device who is using this channel*/
|
||||
void* dma_dev;
|
||||
/*channel operations*/
|
||||
void (*open)(struct dma_channel_info* pCh);
|
||||
void (*close)(struct dma_channel_info* pCh);
|
||||
void (*reset)(struct dma_channel_info* pCh);
|
||||
void (*enable_irq)(struct dma_channel_info* pCh);
|
||||
void (*disable_irq)(struct dma_channel_info* pCh);
|
||||
}_dma_channel_info;
|
||||
|
||||
typedef struct dma_device_info{
|
||||
/*device name of this peripheral*/
|
||||
char device_name[15];
|
||||
int reserved;
|
||||
int tx_burst_len;
|
||||
int rx_burst_len;
|
||||
int default_weight;
|
||||
int current_tx_chan;
|
||||
int current_rx_chan;
|
||||
int num_tx_chan;
|
||||
int num_rx_chan;
|
||||
int max_rx_chan_num;
|
||||
int max_tx_chan_num;
|
||||
_dma_channel_info* tx_chan[20];
|
||||
_dma_channel_info* rx_chan[20];
|
||||
/*functions, optional*/
|
||||
u8* (*buffer_alloc)(int len,int* offset, void** opt);
|
||||
void (*buffer_free)(u8* dataptr, void* opt);
|
||||
int (*intr_handler)(struct dma_device_info* info, int status);
|
||||
void * priv; /* used by peripheral driver only */
|
||||
}_dma_device_info;
|
||||
|
||||
_dma_device_info* dma_device_reserve(char* dev_name);
|
||||
|
||||
void dma_device_release(_dma_device_info* dev);
|
||||
|
||||
void dma_device_register(_dma_device_info* info);
|
||||
|
||||
void dma_device_unregister(_dma_device_info* info);
|
||||
|
||||
int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt);
|
||||
|
||||
int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt);
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2005 infineon
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
#ifndef _DANUBE_IRQ__
|
||||
#define _DANUBE_IRQ__
|
||||
|
||||
#define INT_NUM_IRQ0 8
|
||||
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
|
||||
#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
|
||||
#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
|
||||
#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
|
||||
#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
|
||||
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
|
||||
|
||||
#define DANUBEASC1_TIR (INT_NUM_IM3_IRL0 + 7)
|
||||
#define DANUBEASC1_RIR (INT_NUM_IM3_IRL0 + 9)
|
||||
#define DANUBEASC1_EIR (INT_NUM_IM3_IRL0 + 10)
|
||||
|
||||
#define DANUBE_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
|
||||
|
||||
#define MIPS_CPU_TIMER_IRQ 7
|
||||
|
||||
#define DANUBE_DMA_CH0_INT (INT_NUM_IM2_IRL0)
|
||||
#define DANUBE_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
|
||||
#define DANUBE_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
|
||||
#define DANUBE_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
|
||||
#define DANUBE_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
|
||||
#define DANUBE_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
|
||||
#define DANUBE_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
|
||||
#define DANUBE_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
|
||||
#define DANUBE_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
|
||||
#define DANUBE_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
|
||||
#define DANUBE_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
|
||||
#define DANUBE_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
|
||||
#define DANUBE_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
|
||||
#define DANUBE_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
|
||||
#define DANUBE_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
|
||||
#define DANUBE_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
|
||||
#define DANUBE_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
|
||||
#define DANUBE_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
|
||||
#define DANUBE_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
|
||||
#define DANUBE_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
|
||||
|
||||
extern void mask_and_ack_danube_irq (unsigned int irq_nr);
|
||||
|
||||
#endif
|
||||
254
target/linux/danube/files/include/asm-mips/danube/danube_mii0.h
Normal file
254
target/linux/danube/files/include/asm-mips/danube/danube_mii0.h
Normal file
@@ -0,0 +1,254 @@
|
||||
#ifndef DANUBE_SW_H
|
||||
#define DANUBE_SW_H
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : danube_sw.h
|
||||
** PROJECT : Danube
|
||||
** MODULES : ETH Interface (MII0)
|
||||
**
|
||||
** DATE : 11 AUG 2005
|
||||
** AUTHOR : Wu Qi Ming
|
||||
** DESCRIPTION : ETH Interface (MII0) Driver Header File
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 11 AUG 2005 Wu Qi Ming Initiate Version
|
||||
** 23 OCT 2006 Xu Liang Add GPL header.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE
|
||||
#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1
|
||||
#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2
|
||||
#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3
|
||||
#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4
|
||||
#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5
|
||||
#define SET_ETH_REG SIOCDEVPRIVATE+6
|
||||
#define VLAN_TOOLS SIOCDEVPRIVATE+7
|
||||
#define MAC_TABLE_TOOLS SIOCDEVPRIVATE+8
|
||||
#define SET_VLAN_COS SIOCDEVPRIVATE+9
|
||||
#define SET_DSCP_COS SIOCDEVPRIVATE+10
|
||||
#define ENABLE_VLAN_CLASSIFICATION SIOCDEVPRIVATE+11
|
||||
#define DISABLE_VLAN_CLASSIFICATION SIOCDEVPRIVATE+12
|
||||
#define VLAN_CLASS_FIRST SIOCDEVPRIVATE+13
|
||||
#define VLAN_CLASS_SECOND SIOCDEVPRIVATE+14
|
||||
#define ENABLE_DSCP_CLASSIFICATION SIOCDEVPRIVATE+15
|
||||
#define DISABLE_DSCP_CLASSIFICATION SIOCDEVPRIVATE+16
|
||||
#define PASS_UNICAST_PACKETS SIOCDEVPRIVATE+17
|
||||
#define FILTER_UNICAST_PACKETS SIOCDEVPRIVATE+18
|
||||
#define KEEP_BROADCAST_PACKETS SIOCDEVPRIVATE+19
|
||||
#define DROP_BROADCAST_PACKETS SIOCDEVPRIVATE+20
|
||||
#define KEEP_MULTICAST_PACKETS SIOCDEVPRIVATE+21
|
||||
#define DROP_MULTICAST_PACKETS SIOCDEVPRIVATE+22
|
||||
|
||||
|
||||
/*===mac table commands==*/
|
||||
#define RESET_MAC_TABLE 0
|
||||
#define READ_MAC_ENTRY 1
|
||||
#define WRITE_MAC_ENTRY 2
|
||||
#define ADD_MAC_ENTRY 3
|
||||
|
||||
/*====vlan commands===*/
|
||||
|
||||
#define CHANGE_VLAN_CTRL 0
|
||||
#define READ_VLAN_ENTRY 1
|
||||
#define UPDATE_VLAN_ENTRY 2
|
||||
#define CLEAR_VLAN_ENTRY 3
|
||||
#define RESET_VLAN_TABLE 4
|
||||
#define ADD_VLAN_ENTRY 5
|
||||
|
||||
/*
|
||||
** MDIO constants.
|
||||
*/
|
||||
|
||||
#define MDIO_BASE_STATUS_REG 0x1
|
||||
#define MDIO_BASE_CONTROL_REG 0x0
|
||||
#define MDIO_PHY_ID_HIGH_REG 0x2
|
||||
#define MDIO_PHY_ID_LOW_REG 0x3
|
||||
#define MDIO_BC_NEGOTIATE 0x0200
|
||||
#define MDIO_BC_FULL_DUPLEX_MASK 0x0100
|
||||
#define MDIO_BC_AUTO_NEG_MASK 0x1000
|
||||
#define MDIO_BC_SPEED_SELECT_MASK 0x2000
|
||||
#define MDIO_STATUS_100_FD 0x4000
|
||||
#define MDIO_STATUS_100_HD 0x2000
|
||||
#define MDIO_STATUS_10_FD 0x1000
|
||||
#define MDIO_STATUS_10_HD 0x0800
|
||||
#define MDIO_STATUS_SPEED_DUPLEX_MASK 0x7800
|
||||
#define MDIO_ADVERTISMENT_REG 0x4
|
||||
#define MDIO_ADVERT_100_FD 0x100
|
||||
#define MDIO_ADVERT_100_HD 0x080
|
||||
#define MDIO_ADVERT_10_FD 0x040
|
||||
#define MDIO_ADVERT_10_HD 0x020
|
||||
#define MDIO_LINK_UP_MASK 0x4
|
||||
#define MDIO_START 0x1
|
||||
#define MDIO_READ 0x2
|
||||
#define MDIO_WRITE 0x1
|
||||
#define MDIO_PREAMBLE 0xfffffffful
|
||||
|
||||
#define PHY_RESET 0x8000
|
||||
#define AUTO_NEGOTIATION_ENABLE 0X1000
|
||||
#define AUTO_NEGOTIATION_COMPLETE 0x20
|
||||
#define RESTART_AUTO_NEGOTIATION 0X200
|
||||
|
||||
|
||||
/*ETOP_MDIO_CFG MASKS*/
|
||||
#define SMRST_MASK 0X2000
|
||||
#define PHYA1_MASK 0X1F00
|
||||
#define PHYA0_MASK 0XF8
|
||||
#define UMM1_MASK 0X4
|
||||
#define UMM0_MASK 0X2
|
||||
|
||||
/*ETOP_MDIO_ACCESS MASKS*/
|
||||
#define MDIO_RA_MASK 0X80000000
|
||||
#define MDIO_RW_MASK 0X40000000
|
||||
|
||||
|
||||
/*ENET_MAC_CFG MASKS*/
|
||||
#define BP_MASK 1<<12
|
||||
#define CGEN_MASK 1<<11
|
||||
#define IFG_MASK 0x3F<<5
|
||||
#define IPAUS_MASK 1<<4
|
||||
#define EPAUS_MASK 1<<3
|
||||
#define DUPLEX_MASK 1<<2
|
||||
#define SPEED_MASK 0x2
|
||||
#define LINK_MASK 1
|
||||
|
||||
/*ENETS_CoS_CFG MASKS*/
|
||||
#define VLAN_MASK 2
|
||||
#define DSCP_MASK 1
|
||||
|
||||
/*ENET_CFG MASKS*/
|
||||
#define VL2_MASK 1<<29
|
||||
#define FTUC_MASK 1<<25
|
||||
#define DPBC_MASK 1<<24
|
||||
#define DPMC_MASK 1<<23
|
||||
|
||||
#define PHY0_ADDR 0
|
||||
#define PHY1_ADDR 1
|
||||
#define P1M 0
|
||||
|
||||
#define DANUBE_SW_REG32(reg_num) *((volatile u32*)(reg_num))
|
||||
|
||||
#define OK 0;
|
||||
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
typedef struct mac_table_entry{
|
||||
u64 mac_address:48;
|
||||
u64 p0:1;
|
||||
u64 p1:1;
|
||||
u64 p2:1;
|
||||
u64 cr:1;
|
||||
u64 ma_st:3;
|
||||
u64 res:9;
|
||||
}_mac_table_entry;
|
||||
|
||||
typedef struct IFX_Switch_VLanTableEntry{
|
||||
u32 vlan_id:12;
|
||||
u32 mp0:1;
|
||||
u32 mp1:1;
|
||||
u32 mp2:1;
|
||||
u32 v:1;
|
||||
u32 res:16;
|
||||
}_IFX_Switch_VLanTableEntry;
|
||||
|
||||
typedef struct mac_table_req{
|
||||
int cmd;
|
||||
int index;
|
||||
u32 data;
|
||||
u64 entry_value;
|
||||
}_mac_table_req;
|
||||
|
||||
#else //not CONFIG_CPU_LITTLE_ENDIAN
|
||||
typedef struct mac_table_entry{
|
||||
u64 mac_address:48;
|
||||
u64 p0:1;
|
||||
u64 p1:1;
|
||||
u64 p2:1;
|
||||
u64 cr:1;
|
||||
u64 ma_st:3;
|
||||
u64 res:9;
|
||||
}_mac_table_entry;
|
||||
|
||||
typedef struct IFX_Switch_VLanTableEntry{
|
||||
u32 vlan_id:12;
|
||||
u32 mp0:1;
|
||||
u32 mp1:1;
|
||||
u32 mp2:1;
|
||||
u32 v:1;
|
||||
u32 res:16;
|
||||
}_IFX_Switch_VLanTableEntry;
|
||||
|
||||
|
||||
typedef struct mac_table_req{
|
||||
int cmd;
|
||||
int index;
|
||||
u32 data;
|
||||
u64 entry_value;
|
||||
}_mac_table_req;
|
||||
|
||||
#endif //CONFIG_CPU_LITTLE_ENDIAN
|
||||
|
||||
typedef struct vlan_cos_req{
|
||||
int pri;
|
||||
int cos_value;
|
||||
}_vlan_cos_req;
|
||||
|
||||
typedef struct dscp_cos_req{
|
||||
int dscp;
|
||||
int cos_value;
|
||||
}_dscp_cos_req;
|
||||
|
||||
|
||||
typedef struct vlan_req{
|
||||
int cmd;
|
||||
int index;
|
||||
u32 data;
|
||||
u32 entry_value;
|
||||
}_vlan_req;
|
||||
|
||||
typedef struct data_req{
|
||||
int index;
|
||||
u32 value;
|
||||
}_data_req;
|
||||
|
||||
enum duplex
|
||||
{
|
||||
half,
|
||||
full,
|
||||
autoneg
|
||||
};
|
||||
|
||||
struct switch_priv {
|
||||
struct net_device_stats stats;
|
||||
int rx_packetlen;
|
||||
u8 *rx_packetdata;
|
||||
int rx_status;
|
||||
int tx_packetlen;
|
||||
#ifdef CONFIG_NET_HW_FLOWCONTROL
|
||||
int fc_bit;
|
||||
#endif //CONFIG_NET_HW_FLOWCONTROL
|
||||
u8 *tx_packetdata;
|
||||
int tx_status;
|
||||
struct dma_device_info *dma_device;
|
||||
struct sk_buff *skb;
|
||||
spinlock_t lock;
|
||||
int mdio_phy_addr;
|
||||
int current_speed;
|
||||
int current_speed_selection;
|
||||
int rx_queue_len;
|
||||
int full_duplex;
|
||||
enum duplex current_duplex;
|
||||
};
|
||||
|
||||
#endif //DANUBE_SW_H
|
||||
2021
target/linux/danube/files/include/asm-mips/danube/danube_orig.h
Normal file
2021
target/linux/danube/files/include/asm-mips/danube/danube_orig.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,194 @@
|
||||
/* incaAscSio.h - (DANUBE) ASC UART tty driver header */
|
||||
|
||||
#ifndef __DANUBE_ASC_H
|
||||
#define __DANUBE_ASC_H
|
||||
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : serial.c
|
||||
** PROJECT : Danube
|
||||
** MODULES : ASC/UART
|
||||
**
|
||||
** DATE : 27 MAR 2006
|
||||
** AUTHOR : Liu Peng
|
||||
** DESCRIPTION : Asynchronous Serial Channel (ASC/UART) Driver Header File
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 27 MAR 2006 Liu Peng Initiate Version (rev 1.7)
|
||||
** 23 OCT 2006 Xu Liang Add GPL header.
|
||||
*******************************************************************************/
|
||||
|
||||
/* channel operating modes */
|
||||
/*#define ASCOPT_CSIZE 0x00000003
|
||||
#define ASCOPT_CS7 0x00000001
|
||||
#define ASCOPT_CS8 0x00000002
|
||||
#define ASCOPT_PARENB 0x00000004
|
||||
#define ASCOPT_STOPB 0x00000008
|
||||
#define ASCOPT_PARODD 0x00000010
|
||||
#define ASCOPT_CREAD 0x00000020
|
||||
*/
|
||||
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
|
||||
|
||||
/* ASC input select (0 or 1) */
|
||||
#define CONSOLE_TTY 0
|
||||
|
||||
#define DANUBEASC_TXFIFO_FL 1
|
||||
#define DANUBEASC_RXFIFO_FL 1
|
||||
#define DANUBEASC_TXFIFO_FULL 16
|
||||
|
||||
/* interrupt lines masks for the ASC device interrupts*/
|
||||
/* change these macroses if it's necessary */
|
||||
#define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
|
||||
|
||||
#define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
|
||||
#define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
|
||||
#define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
|
||||
#define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
|
||||
#define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
|
||||
#define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
|
||||
#define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
|
||||
|
||||
/* interrupt controller access macros */
|
||||
#define ASC_INTERRUPTS_ENABLE(X) \
|
||||
*((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X;
|
||||
#define ASC_INTERRUPTS_DISABLE(X) \
|
||||
*((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X;
|
||||
#define ASC_INTERRUPTS_CLEAR(X) \
|
||||
*((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X;
|
||||
|
||||
/* CLC register's bits and bitfields */
|
||||
#define ASCCLC_DISR 0x00000001
|
||||
#define ASCCLC_DISS 0x00000002
|
||||
#define ASCCLC_RMCMASK 0x0000FF00
|
||||
#define ASCCLC_RMCOFFSET 8
|
||||
|
||||
/* CON register's bits and bitfields */
|
||||
#define ASCCON_MODEMASK 0x0000000f
|
||||
#define ASCCON_M_8ASYNC 0x0
|
||||
#define ASCCON_M_8IRDA 0x1
|
||||
#define ASCCON_M_7ASYNC 0x2
|
||||
#define ASCCON_M_7IRDA 0x3
|
||||
#define ASCCON_WLSMASK 0x0000000c
|
||||
#define ASCCON_WLSOFFSET 2
|
||||
#define ASCCON_WLS_8BIT 0x0
|
||||
#define ASCCON_WLS_7BIT 0x1
|
||||
#define ASCCON_PEN 0x00000010
|
||||
#define ASCCON_ODD 0x00000020
|
||||
#define ASCCON_SP 0x00000040
|
||||
#define ASCCON_STP 0x00000080
|
||||
#define ASCCON_BRS 0x00000100
|
||||
#define ASCCON_FDE 0x00000200
|
||||
#define ASCCON_ERRCLK 0x00000400
|
||||
#define ASCCON_EMMASK 0x00001800
|
||||
#define ASCCON_EMOFFSET 11
|
||||
#define ASCCON_EM_ECHO_OFF 0x0
|
||||
#define ASCCON_EM_ECHO_AB 0x1
|
||||
#define ASCCON_EM_ECHO_ON 0x2
|
||||
#define ASCCON_LB 0x00002000
|
||||
#define ASCCON_ACO 0x00004000
|
||||
#define ASCCON_R 0x00008000
|
||||
#define ASCCON_PAL 0x00010000
|
||||
#define ASCCON_FEN 0x00020000
|
||||
#define ASCCON_RUEN 0x00040000
|
||||
#define ASCCON_ROEN 0x00080000
|
||||
#define ASCCON_TOEN 0x00100000
|
||||
#define ASCCON_BEN 0x00200000
|
||||
#define ASCCON_TXINV 0x01000000
|
||||
#define ASCCON_RXINV 0x02000000
|
||||
#define ASCCON_TXMSB 0x04000000
|
||||
#define ASCCON_RXMSB 0x08000000
|
||||
|
||||
/* STATE register's bits and bitfields */
|
||||
#define ASCSTATE_REN 0x00000001
|
||||
#define ASCSTATE_PE 0x00010000
|
||||
#define ASCSTATE_FE 0x00020000
|
||||
#define ASCSTATE_RUE 0x00040000
|
||||
#define ASCSTATE_ROE 0x00080000
|
||||
#define ASCSTATE_TOE 0x00100000
|
||||
#define ASCSTATE_BE 0x00200000
|
||||
#define ASCSTATE_TXBVMASK 0x07000000
|
||||
#define ASCSTATE_TXBVOFFSET 24
|
||||
#define ASCSTATE_TXEOM 0x08000000
|
||||
#define ASCSTATE_RXBVMASK 0x70000000
|
||||
#define ASCSTATE_RXBVOFFSET 28
|
||||
#define ASCSTATE_RXEOM 0x80000000
|
||||
#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
|
||||
|
||||
/* WHBSTATE register's bits and bitfields */
|
||||
#define ASCWHBSTATE_CLRREN 0x00000001
|
||||
#define ASCWHBSTATE_SETREN 0x00000002
|
||||
#define ASCWHBSTATE_CLRPE 0x00000004
|
||||
#define ASCWHBSTATE_CLRFE 0x00000008
|
||||
#define ASCWHBSTATE_CLRRUE 0x00000010
|
||||
#define ASCWHBSTATE_CLRROE 0x00000020
|
||||
#define ASCWHBSTATE_CLRTOE 0x00000040
|
||||
#define ASCWHBSTATE_CLRBE 0x00000080
|
||||
#define ASCWHBSTATE_SETPE 0x00000100
|
||||
#define ASCWHBSTATE_SETFE 0x00000200
|
||||
#define ASCWHBSTATE_SETRUE 0x00000400
|
||||
#define ASCWHBSTATE_SETROE 0x00000800
|
||||
#define ASCWHBSTATE_SETTOE 0x00001000
|
||||
#define ASCWHBSTATE_SETBE 0x00002000
|
||||
|
||||
/* ABCON register's bits and bitfields */
|
||||
#define ASCABCON_ABEN 0x0001
|
||||
#define ASCABCON_AUREN 0x0002
|
||||
#define ASCABCON_ABSTEN 0x0004
|
||||
#define ASCABCON_ABDETEN 0x0008
|
||||
#define ASCABCON_FCDETEN 0x0010
|
||||
|
||||
/* FDV register mask, offset and bitfields*/
|
||||
#define ASCFDV_VALUE_MASK 0x000001FF
|
||||
|
||||
/* WHBABCON register's bits and bitfields */
|
||||
#define ASCWHBABCON_CLRABEN 0x0001
|
||||
#define ASCWHBABCON_SETABEN 0x0002
|
||||
|
||||
/* ABSTAT register's bits and bitfields */
|
||||
#define ASCABSTAT_FCSDET 0x0001
|
||||
#define ASCABSTAT_FCCDET 0x0002
|
||||
#define ASCABSTAT_SCSDET 0x0004
|
||||
#define ASCABSTAT_SCCDET 0x0008
|
||||
#define ASCABSTAT_DETWAIT 0x0010
|
||||
|
||||
/* WHBABSTAT register's bits and bitfields */
|
||||
#define ASCWHBABSTAT_CLRFCSDET 0x0001
|
||||
#define ASCWHBABSTAT_SETFCSDET 0x0002
|
||||
#define ASCWHBABSTAT_CLRFCCDET 0x0004
|
||||
#define ASCWHBABSTAT_SETFCCDET 0x0008
|
||||
#define ASCWHBABSTAT_CLRSCSDET 0x0010
|
||||
#define ASCWHBABSTAT_SETSCSDET 0x0020
|
||||
#define ASCWHBABSTAT_CLRSCCDET 0x0040
|
||||
#define ASCWHBABSTAT_SETSCCDET 0x0080
|
||||
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
|
||||
#define ASCWHBABSTAT_SETDETWAIT 0x0200
|
||||
|
||||
/* TXFCON register's bits and bitfields */
|
||||
#define ASCTXFCON_TXFIFO1 0x00000400
|
||||
#define ASCTXFCON_TXFEN 0x0001
|
||||
#define ASCTXFCON_TXFFLU 0x0002
|
||||
#define ASCTXFCON_TXFITLMASK 0x3F00
|
||||
#define ASCTXFCON_TXFITLOFF 8
|
||||
|
||||
/* RXFCON register's bits and bitfields */
|
||||
#define ASCRXFCON_RXFIFO1 0x00000400
|
||||
#define ASCRXFCON_RXFEN 0x0001
|
||||
#define ASCRXFCON_RXFFLU 0x0002
|
||||
#define ASCRXFCON_RXFITLMASK 0x3F00
|
||||
#define ASCRXFCON_RXFITLOFF 8
|
||||
|
||||
/* FSTAT register's bits and bitfields */
|
||||
#define ASCFSTAT_RXFFLMASK 0x003F
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
|
||||
#endif /* __DANUBE_ASC_H */
|
||||
@@ -0,0 +1,8 @@
|
||||
#ifndef __DANUBE_IRQ_H
|
||||
#define __DANUBE_IRQ_H
|
||||
|
||||
#define NR_IRQS 256
|
||||
#include_next <irq.h>
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user