brcm47xx: add initial support for kernel 2.6.38

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@26524 3c298f89-4303-0410-b956-a3cf2f4a3e73
2024-12-24 18:50:49 +02:00 · 2011-04-07 21:38:41 +00:00 · 2011-04-07 21:38:41 +00:00 · 82b04bebc1
commit 82b04bebc1
parent b1f3482e70
33 changed files with 3076 additions and 0 deletions
--- a/target/linux/brcm47xx/config-2.6.38
+++ b/target/linux/brcm47xx/config-2.6.38
@ -0,0 +1,129 @@
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ARPD is not set
+# CONFIG_ATH79 is not set
+# CONFIG_AUTO_IRQ_AFFINITY is not set
+CONFIG_B44=y
+CONFIG_B44_PCI=y
+CONFIG_B44_PCICORE_AUTOSELECT=y
+CONFIG_B44_PCI_AUTOSELECT=y
+CONFIG_BCM47XX=y
+CONFIG_BCM47XX_WDT=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_BUG is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CFE=y
+CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_CSRC_R4K_LIB=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_EXPERT=y
+# CONFIG_FSNOTIFY is not set
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED is not set
+# CONFIG_GENERIC_PENDING_IRQ is not set
+# CONFIG_HARDIRQS_SW_RESEND is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+# CONFIG_HAVE_SPARSE_IRQ is not set
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IRQ_CPU=y
+# CONFIG_IRQ_PER_CPU is not set
+CONFIG_KALLSYMS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_MACH_NO_WESTBRIDGE=y
+CONFIG_MIPS=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_MT_DISABLED=y
+CONFIG_MTD_BCM47XX=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NO_HZ=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_RSA is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SSB=y
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_DEBUG=y
+CONFIG_SSB_DRIVER_EXTIF=y
+CONFIG_SSB_DRIVER_GIGE=y
+CONFIG_SSB_DRIVER_MIPS=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_EMBEDDED=y
+CONFIG_SSB_PCICORE_HOSTMODE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_SERIAL=y
+CONFIG_SSB_SPROM=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_XZ_DEC=y
+CONFIG_ZONE_DMA_FLAG=0
--- a/target/linux/brcm47xx/patches-2.6.38/014-MIPS-BCM47xx-Setup-and-register-serial-early.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/014-MIPS-BCM47xx-Setup-and-register-serial-early.patch
@ -0,0 +1,69 @@
+From 9be402f069cc259ad5795b77567d66c4e7f6bef6 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Sun, 18 Jul 2010 14:59:24 +0200
+Subject: [PATCH 4/6] MIPS: BCM47xx: Setup and register serial early
+
+Swap the first and second serial if console=ttyS1 was set.
+Set it up and register it for early serial support.
+
+This patch has been in OpenWRT for a long time.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ arch/mips/bcm47xx/setup.c |   39 ++++++++++++++++++++++++++++++++++++++-
+ 1 files changed, 38 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
+@@ -28,6 +28,8 @@
+ #include <linux/types.h>
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+ #include <asm/bootinfo.h>
+ #include <asm/reboot.h>
+ #include <asm/time.h>
+@@ -166,6 +168,31 @@ static int bcm47xx_get_invariants(struct
+ 	return 0;
+ }
+ 
+#ifdef CONFIG_SERIAL_8250
+static void __init bcm47xx_early_serial_setup(struct ssb_mipscore *mcore)
+{
+	int i;
+
+	for (i = 0; i < mcore->nr_serial_ports; i++) {
+		struct ssb_serial_port *port = &(mcore->serial_ports[i]);
+		struct uart_port s;
+
+		memset(&s, 0, sizeof(s));
+		s.line = i;
+		s.mapbase = (unsigned int) port->regs;
+		s.membase = port->regs;
+		s.irq = port->irq + 2;
+		s.uartclk = port->baud_base;
+		s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+		s.iotype = SERIAL_IO_MEM;
+		s.regshift = port->reg_shift;
+
+		early_serial_setup(&s);
+	}
+	printk(KERN_DEBUG "Serial init done.\n");
+}
+#endif
+
+ void __init plat_mem_setup(void)
+ {
+ 	int err;
+@@ -191,6 +218,10 @@ void __init plat_mem_setup(void)
+ 		}
+ 	}
+ 
+#ifdef CONFIG_SERIAL_8250
+	bcm47xx_early_serial_setup(mcore);
+#endif
+
+ 	_machine_restart = bcm47xx_machine_restart;
+ 	_machine_halt = bcm47xx_machine_halt;
+ 	pm_power_off = bcm47xx_machine_halt;
--- a/target/linux/brcm47xx/patches-2.6.38/016-MIPS-BCM47xx-Remove-CFE-console.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/016-MIPS-BCM47xx-Remove-CFE-console.patch
@ -0,0 +1,141 @@
+From 5219981646071abb6731634bf47781a53e248764 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Sun, 18 Jul 2010 15:11:26 +0200
+Subject: [PATCH 6/6] MIPS: BCM47xx: Remove CFE console
+
+Do not use the CFE console. It causes hangs on some devices like the
+Buffalo WHR-HP-G54.
+This was reported in https://dev.openwrt.org/ticket/4061 and
+https://forum.openwrt.org/viewtopic.php?id=17063
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ arch/mips/Kconfig        |    1 -
+ arch/mips/bcm47xx/prom.c |   82 +++------------------------------------------
+ 2 files changed, 6 insertions(+), 77 deletions(-)
+
+--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
+@@ -100,7 +100,6 @@ config BCM47XX
+ 	select SSB_B43_PCI_BRIDGE if PCI
+ 	select SSB_PCICORE_HOSTMODE if PCI
+ 	select GENERIC_GPIO
+-	select SYS_HAS_EARLY_PRINTK
+ 	select CFE
+ 	help
+ 	 Support for BCM47XX based boards
+--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
+@@ -31,96 +31,28 @@
+ #include <asm/fw/cfe/cfe_api.h>
+ #include <asm/fw/cfe/cfe_error.h>
+ 
+-static int cfe_cons_handle;
+-
+ const char *get_system_type(void)
+ {
+ 	return "Broadcom BCM47XX";
+ }
+ 
+-void prom_putchar(char c)
+-{
+-	while (cfe_write(cfe_cons_handle, &c, 1) == 0)
+-		;
+-}
+-
+-static __init void prom_init_cfe(void)
+static __init int prom_init_cfe(void)
+ {
+ 	uint32_t cfe_ept;
+ 	uint32_t cfe_handle;
+ 	uint32_t cfe_eptseal;
+-	int argc = fw_arg0;
+-	char **envp = (char **) fw_arg2;
+-	int *prom_vec = (int *) fw_arg3;
+-
+-	/*
+-	 * Check if a loader was used; if NOT, the 4 arguments are
+-	 * what CFE gives us (handle, 0, EPT and EPTSEAL)
+-	 */
+-	if (argc < 0) {
+-		cfe_handle = (uint32_t)argc;
+-		cfe_ept = (uint32_t)envp;
+-		cfe_eptseal = (uint32_t)prom_vec;
+-	} else {
+-		if ((int)prom_vec < 0) {
+-			/*
+-			 * Old loader; all it gives us is the handle,
+-			 * so use the "known" entrypoint and assume
+-			 * the seal.
+-			 */
+-			cfe_handle = (uint32_t)prom_vec;
+-			cfe_ept = 0xBFC00500;
+-			cfe_eptseal = CFE_EPTSEAL;
+-		} else {
+-			/*
+-			 * Newer loaders bundle the handle/ept/eptseal
+-			 * Note: prom_vec is in the loader's useg
+-			 * which is still alive in the TLB.
+-			 */
+-			cfe_handle = prom_vec[0];
+-			cfe_ept = prom_vec[2];
+-			cfe_eptseal = prom_vec[3];
+-		}
+-	}
+
+	cfe_eptseal = (uint32_t) fw_arg3;
+	cfe_handle = (uint32_t) fw_arg0;
+	cfe_ept = (uint32_t) fw_arg2;
+ 
+ 	if (cfe_eptseal != CFE_EPTSEAL) {
+-		/* too early for panic to do any good */
+ 		printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
+-		while (1) ;
+		return -1;
+ 	}
+ 
+ 	cfe_init(cfe_handle, cfe_ept);
+-}
+-
+-static __init void prom_init_console(void)
+-{
+-	/* Initialize CFE console */
+-	cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
+-}
+-
+-static __init void prom_init_cmdline(void)
+-{
+-	static char buf[COMMAND_LINE_SIZE] __initdata;
+-
+-	/* Get the kernel command line from CFE */
+-	if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
+-		buf[COMMAND_LINE_SIZE - 1] = 0;
+-		strcpy(arcs_cmdline, buf);
+-	}
+-
+-	/* Force a console handover by adding a console= argument if needed,
+-	 * as CFE is not available anymore later in the boot process. */
+-	if ((strstr(arcs_cmdline, "console=")) == NULL) {
+-		/* Try to read the default serial port used by CFE */
+-		if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
+-		    || (strncmp("uart", buf, 4)))
+-			/* Default to uart0 */
+-			strcpy(buf, "uart0");
+-
+-		/* Compute the new command line */
+-		snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
+-			 arcs_cmdline, buf[4]);
+-	}
+	return 0;
+ }
+ 
+ static __init void prom_init_mem(void)
+@@ -161,8 +93,6 @@ static __init void prom_init_mem(void)
+ void __init prom_init(void)
+ {
+ 	prom_init_cfe();
+-	prom_init_console();
+-	prom_init_cmdline();
+ 	prom_init_mem();
+ }
+ 
--- a/target/linux/brcm47xx/patches-2.6.38/018-wgt634u_mac_address_parser_fix.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/018-wgt634u_mac_address_parser_fix.patch
@ -0,0 +1,20 @@
+--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h
+@@ -39,8 +39,15 @@ extern int nvram_getenv(char *name, char
+ 
+ static inline void nvram_parse_macaddr(char *buf, u8 *macaddr)
+ {
+-	sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1],
+-	       &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]);
+	if (strchr(buf, ':')) {
+		sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1],
+			&macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]);
+	} else if (strchr(buf, '-')) {
+		sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0], &macaddr[1],
+			&macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]);
+	} else {
+		printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
+	}
+ }
+ 
+ #endif
--- a/target/linux/brcm47xx/patches-2.6.38/019-fix-boot.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/019-fix-boot.patch
@ -0,0 +1,42 @@
+--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
+@@ -121,14 +121,6 @@
+ #endif
+ 	.endm
+ 
+-#ifndef CONFIG_NO_EXCEPT_FILL
+-	/*
+-	 * Reserved space for exception handlers.
+-	 * Necessary for machines which link their kernels at KSEG0.
+-	 */
+-	.fill	0x400
+-#endif
+-
+ EXPORT(_stext)
+ 
+ #ifdef CONFIG_BOOT_RAW
+@@ -141,6 +133,14 @@ FEXPORT(__kernel_entry)
+ 	j	kernel_entry
+ #endif
+ 
+#ifndef CONFIG_NO_EXCEPT_FILL
+	/*
+	 * Reserved space for exception handlers.
+	 * Necessary for machines which link their kernels at KSEG0.
+	 */
+	.fill	0x400
+#endif
+
+ #ifdef CONFIG_IMAGE_CMDLINE_HACK
+ 	.ascii	"CMDLINE:"
+ EXPORT(__image_cmdline)
+--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
+@@ -85,6 +85,7 @@ config ATH79
+ 
+ config BCM47XX
+ 	bool "Broadcom BCM47XX based boards"
+	select BOOT_RAW
+ 	select CEVT_R4K
+ 	select CSRC_R4K
+ 	select DMA_NONCOHERENT
--- a/target/linux/brcm47xx/patches-2.6.38/022-USB-Add-ehci-ssb-driver.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/022-USB-Add-ehci-ssb-driver.patch
@ -0,0 +1,345 @@
+From ad224c0d5fa0fc05f8aaef3c19fc9b4eb275a5d2 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Sun, 18 Jul 2010 21:29:40 +0200
+Subject: [PATCH 2/2] USB: Add ehci ssb driver
+
+Support for the Sonics Silicon Backplane (SSB) attached Broadcom USB EHCI core.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ drivers/usb/host/Kconfig    |   13 ++
+ drivers/usb/host/ehci-hcd.c |   22 ++++-
+ drivers/usb/host/ehci-ssb.c |  255 +++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 288 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/usb/host/ehci-ssb.c
+
+--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
+@@ -189,6 +189,19 @@ config USB_OXU210HP_HCD
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called oxu210hp-hcd.
+ 
+config USB_EHCI_HCD_SSB
+	bool "EHCI support for Broadcom SSB EHCI core"
+	depends on USB_EHCI_HCD && (SSB = y || SSB = USB_EHCI_HCD) && EXPERIMENTAL
+	default n
+	---help---
+	  Support for the Sonics Silicon Backplane (SSB) attached
+	  Broadcom USB EHCI core.
+
+	  This device is present in some embedded devices with
+	  Broadcom based SSB bus.
+
+	  If unsure, say N.
+
+ config USB_ISP116X_HCD
+ 	tristate "ISP116X HCD support"
+ 	depends on USB
+--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
+@@ -1254,9 +1254,14 @@ MODULE_LICENSE ("GPL");
+ #define PLATFORM_DRIVER		ehci_msm_driver
+ #endif
+ 
+#ifdef CONFIG_USB_EHCI_HCD_SSB
+#include "ehci-ssb.c"
+#define SSB_EHCI_DRIVER		ssb_ehci_driver
+#endif
+
+ #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
+     !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
+-    !defined(XILINX_OF_PLATFORM_DRIVER)
+    !defined(XILINX_OF_PLATFORM_DRIVER) && !defined(SSB_EHCI_DRIVER)
+ #error "missing bus glue for ehci-hcd"
+ #endif
+ 
+@@ -1316,10 +1321,20 @@ static int __init ehci_hcd_init(void)
+ 	if (retval < 0)
+ 		goto clean4;
+ #endif
+
+#ifdef SSB_EHCI_DRIVER
+	retval = ssb_driver_register(&SSB_EHCI_DRIVER);
+	if (retval < 0)
+		goto clean5;
+#endif
+ 	return retval;
+ 
+#ifdef SSB_EHCI_DRIVER
+	/* ssb_driver_unregister(&SSB_EHCI_DRIVER); */
+clean5:
+#endif
+ #ifdef XILINX_OF_PLATFORM_DRIVER
+-	/* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */
+	of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
+ clean4:
+ #endif
+ #ifdef OF_PLATFORM_DRIVER
+@@ -1350,6 +1365,9 @@ module_init(ehci_hcd_init);
+ 
+ static void __exit ehci_hcd_cleanup(void)
+ {
+#ifdef SSB_EHCI_DRIVER
+	ssb_driver_unregister(&SSB_EHCI_DRIVER);
+#endif
+ #ifdef XILINX_OF_PLATFORM_DRIVER
+ 	of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
+ #endif
+--- /dev/null
+++ b/drivers/usb/host/ehci-ssb.c
+@@ -0,0 +1,255 @@
+/*
+ * Sonics Silicon Backplane
+ * Broadcom USB-core EHCI driver (SSB bus glue)
+ *
+ * Copyright 2007 Steven Brown <sbrown@cortland.com>
+ * Copyright 2010 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Derived from the OHCI-SSB driver
+ * Copyright 2007 Michael Buesch <mb@bu3sch.de>
+ *
+ * Derived from the EHCI-PCI driver
+ * Copyright (c) 2000-2004 by David Brownell
+ *
+ * Derived from the OHCI-PCI driver
+ * Copyright 1999 Roman Weissgaerber
+ * Copyright 2000-2002 David Brownell
+ * Copyright 1999 Linus Torvalds
+ * Copyright 1999 Gregory P. Smith
+ *
+ * Derived from the USBcore related parts of Broadcom-SB
+ * Copyright 2005 Broadcom Corporation
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+#include <linux/ssb/ssb.h>
+
+
+struct ssb_ehci_device {
+	struct ehci_hcd ehci; /* _must_ be at the beginning. */
+};
+
+static inline
+struct ssb_ehci_device *hcd_to_ssb_ehci(struct usb_hcd *hcd)
+{
+	return (struct ssb_ehci_device *)(hcd->hcd_priv);
+}
+
+static int ssb_ehci_reset(struct usb_hcd *hcd)
+{
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	int err;
+
+	ehci->caps = hcd->regs;
+	ehci->regs = hcd->regs +
+		HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+
+	dbg_hcs_params(ehci, "reset");
+	dbg_hcc_params(ehci, "reset");
+
+	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+
+	err = ehci_halt(ehci);
+
+	if (err)
+		return err;
+
+	err = ehci_init(hcd);
+
+	if (err)
+		return err;
+
+	ehci_reset(ehci);
+
+	return err;
+}
+
+static const struct hc_driver ssb_ehci_hc_driver = {
+	.description		= "ssb-usb-ehci",
+	.product_desc		= "SSB EHCI Controller",
+	.hcd_priv_size		= sizeof(struct ssb_ehci_device),
+
+	.irq			= ehci_irq,
+	.flags			= HCD_MEMORY | HCD_USB2,
+
+	.reset			= ssb_ehci_reset,
+	.start			= ehci_run,
+	.stop			= ehci_stop,
+	.shutdown		= ehci_shutdown,
+
+	.urb_enqueue		= ehci_urb_enqueue,
+	.urb_dequeue		= ehci_urb_dequeue,
+	.endpoint_disable	= ehci_endpoint_disable,
+	.endpoint_reset		= ehci_endpoint_reset,
+
+	.get_frame_number	= ehci_get_frame,
+
+	.hub_status_data	= ehci_hub_status_data,
+	.hub_control		= ehci_hub_control,
+#if defined(CONFIG_PM)
+	.bus_suspend		= ehci_bus_suspend,
+	.bus_resume		= ehci_bus_resume,
+#endif
+	.relinquish_port	= ehci_relinquish_port,
+	.port_handed_over	= ehci_port_handed_over,
+
+	.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
+};
+
+static void ssb_ehci_detach(struct ssb_device *dev)
+{
+	struct usb_hcd *hcd = ssb_get_drvdata(dev);
+
+	if (hcd->driver->shutdown)
+		hcd->driver->shutdown(hcd);
+	usb_remove_hcd(hcd);
+	iounmap(hcd->regs);
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	usb_put_hcd(hcd);
+	ssb_device_disable(dev, 0);
+}
+
+static int ssb_ehci_attach(struct ssb_device *dev)
+{
+	struct ssb_ehci_device *ehcidev;
+	struct usb_hcd *hcd;
+	int err = -ENOMEM;
+	u32 tmp;
+
+	if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) ||
+	    dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32)))
+		return -EOPNOTSUPP;
+
+	/*
+	 * USB 2.0 special considerations:
+	 *
+	 * In addition to the standard SSB reset sequence, the Host Control
+	 * Register must be programmed to bring the USB core and various phy
+	 * components out of reset.
+	 */
+	ssb_device_enable(dev, 0);
+	ssb_write32(dev, 0x200, 0x7ff);
+
+	/* Change Flush control reg */
+	tmp = ssb_read32(dev, 0x400);
+	tmp &= ~8;
+	ssb_write32(dev, 0x400, tmp);
+	tmp = ssb_read32(dev, 0x400);
+
+	/* Change Shim control reg */
+	tmp = ssb_read32(dev, 0x304);
+	tmp &= ~0x100;
+	ssb_write32(dev, 0x304, tmp);
+	tmp = ssb_read32(dev, 0x304);
+
+	udelay(1);
+
+	/* Work around for 5354 failures */
+	if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) {
+		/* Change syn01 reg */
+		tmp = 0x00fe00fe;
+		ssb_write32(dev, 0x894, tmp);
+
+		/* Change syn03 reg */
+		tmp = ssb_read32(dev, 0x89c);
+		tmp |= 0x1;
+		ssb_write32(dev, 0x89c, tmp);
+	}
+
+	hcd = usb_create_hcd(&ssb_ehci_hc_driver, dev->dev,
+			     dev_name(dev->dev));
+	if (!hcd)
+		goto err_dev_disable;
+
+	ehcidev = hcd_to_ssb_ehci(hcd);
+	tmp = ssb_read32(dev, SSB_ADMATCH0);
+	hcd->rsrc_start = ssb_admatch_base(tmp) + 0x800; /* ehci core offset */
+	hcd->rsrc_len = 0x100; /* ehci reg block size */
+	/*
+	 * start & size modified per sbutils.c
+	 */
+	hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len);
+	if (!hcd->regs)
+		goto err_put_hcd;
+	err = usb_add_hcd(hcd, dev->irq, IRQF_DISABLED | IRQF_SHARED);
+	if (err)
+		goto err_iounmap;
+
+	ssb_set_drvdata(dev, hcd);
+
+	return err;
+
+err_iounmap:
+	iounmap(hcd->regs);
+err_put_hcd:
+	usb_put_hcd(hcd);
+err_dev_disable:
+	ssb_device_disable(dev, 0);
+	return err;
+}
+
+static int ssb_ehci_probe(struct ssb_device *dev,
+		const struct ssb_device_id *id)
+{
+	int err;
+	u16 chipid_top;
+
+	/* USBcores are only connected on embedded devices. */
+	chipid_top = (dev->bus->chip_id & 0xFF00);
+	if (chipid_top != 0x4700 && chipid_top != 0x5300)
+		return -ENODEV;
+
+	/* TODO: Probably need checks here; is the core connected? */
+
+	if (usb_disabled())
+		return -ENODEV;
+
+	err = ssb_ehci_attach(dev);
+
+	return err;
+}
+
+static void ssb_ehci_remove(struct ssb_device *dev)
+{
+	ssb_ehci_detach(dev);
+}
+
+#ifdef CONFIG_PM
+
+static int ssb_ehci_suspend(struct ssb_device *dev, pm_message_t state)
+{
+	ssb_device_disable(dev, 0);
+
+	return 0;
+}
+
+static int ssb_ehci_resume(struct ssb_device *dev)
+{
+	struct usb_hcd *hcd = ssb_get_drvdata(dev);
+	struct ssb_ehci_device *ehcidev = hcd_to_ssb_ehci(hcd);
+
+	ssb_device_enable(dev, 0);
+
+	ehci_finish_controller_resume(hcd);
+	return 0;
+}
+
+#else /* !CONFIG_PM */
+#define ssb_ehci_suspend	NULL
+#define ssb_ehci_resume	NULL
+#endif /* CONFIG_PM */
+
+static const struct ssb_device_id ssb_ehci_table[] = {
+	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
+	SSB_DEVTABLE_END
+};
+MODULE_DEVICE_TABLE(ssb, ssb_ehci_table);
+
+static struct ssb_driver ssb_ehci_driver = {
+	.name		= KBUILD_MODNAME,
+	.id_table	= ssb_ehci_table,
+	.probe		= ssb_ehci_probe,
+	.remove		= ssb_ehci_remove,
+	.suspend	= ssb_ehci_suspend,
+	.resume		= ssb_ehci_resume,
+};
--- a/target/linux/brcm47xx/patches-2.6.38/023-usb_ehci_ohci.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/023-usb_ehci_ohci.patch
@ -0,0 +1,188 @@
+--- a/drivers/usb/host/ohci-ssb.c
+++ b/drivers/usb/host/ohci-ssb.c
+@@ -17,6 +17,8 @@
+  */
+ #include <linux/ssb/ssb.h>
+ 
+extern int ssb_ehci_attach(struct ssb_device *dev, struct usb_hcd **hcd);
+extern void ssb_ehci_detach(struct ssb_device *dev, struct usb_hcd *hcd);
+ 
+ #define SSB_OHCI_TMSLOW_HOSTMODE	(1 << 29)
+ 
+@@ -24,6 +26,9 @@ struct ssb_ohci_device {
+ 	struct ohci_hcd ohci; /* _must_ be at the beginning. */
+ 
+ 	u32 enable_flags;
+#ifdef CONFIG_USB_EHCI_HCD_SSB
+	struct usb_hcd *ehci_hcd;
+#endif
+ };
+ 
+ static inline
+@@ -92,6 +97,9 @@ static const struct hc_driver ssb_ohci_h
+ static void ssb_ohci_detach(struct ssb_device *dev)
+ {
+ 	struct usb_hcd *hcd = ssb_get_drvdata(dev);
+#ifdef CONFIG_USB_EHCI_HCD_SSB
+	struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
+#endif
+ 
+ 	if (hcd->driver->shutdown)
+ 		hcd->driver->shutdown(hcd);
+@@ -99,6 +107,14 @@ static void ssb_ohci_detach(struct ssb_d
+ 	iounmap(hcd->regs);
+ 	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ 	usb_put_hcd(hcd);
+
+#ifdef CONFIG_USB_EHCI_HCD_SSB
+	/*
+ 	 * Also detach ehci function
+	 */
+	if (dev->id.coreid == SSB_DEV_USB20_HOST)
+		ssb_ehci_detach(dev, ohcidev->ehci_hcd);
+#endif
+ 	ssb_device_disable(dev, 0);
+ }
+ 
+@@ -121,6 +137,9 @@ static int ssb_ohci_attach(struct ssb_de
+ 		/*
+ 		 * USB 2.0 special considerations:
+ 		 *
+		 * Since the core supports both OHCI and EHCI functions, 
+		 * it must only be reset once.
+		 *
+ 		 * In addition to the standard SSB reset sequence, the Host
+ 		 * Control Register must be programmed to bring the USB core
+ 		 * and various phy components out of reset.
+@@ -175,6 +194,14 @@ static int ssb_ohci_attach(struct ssb_de
+ 
+ 	ssb_set_drvdata(dev, hcd);
+ 
+#ifdef CONFIG_USB_EHCI_HCD_SSB
+	/*
+	 *  attach ehci function in this core
+	 */
+	if (dev->id.coreid == SSB_DEV_USB20_HOST)
+		err = ssb_ehci_attach(dev, &(ohcidev->ehci_hcd));
+#endif
+
+ 	return err;
+ 
+ err_iounmap:
+--- a/drivers/usb/host/ehci-ssb.c
+++ b/drivers/usb/host/ehci-ssb.c
+@@ -106,10 +106,18 @@ static void ssb_ehci_detach(struct ssb_d
+ 	iounmap(hcd->regs);
+ 	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ 	usb_put_hcd(hcd);
+#ifndef CONFIG_USB_OHCI_HCD_SSB
+	ssb_device_disable(dev, 0);
+#endif
+ 	ssb_device_disable(dev, 0);
+ }
+EXPORT_SYMBOL_GPL(ssb_ehci_detach);
+ 
+#ifndef CONFIG_USB_OHCI_HCD_SSB
+ static int ssb_ehci_attach(struct ssb_device *dev)
+#else
+static int ssb_ehci_attach(struct ssb_device *dev, struct usb_hcd **ehci_hcd)
+#endif
+ {
+ 	struct ssb_ehci_device *ehcidev;
+ 	struct usb_hcd *hcd;
+@@ -120,6 +128,7 @@ static int ssb_ehci_attach(struct ssb_de
+ 	    dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32)))
+ 		return -EOPNOTSUPP;
+ 
+#ifndef CONFIG_USB_OHCI_HCD_SSB
+ 	/*
+ 	 * USB 2.0 special considerations:
+ 	 *
+@@ -155,6 +164,7 @@ static int ssb_ehci_attach(struct ssb_de
+ 		tmp |= 0x1;
+ 		ssb_write32(dev, 0x89c, tmp);
+ 	}
+#endif
+ 
+ 	hcd = usb_create_hcd(&ssb_ehci_hc_driver, dev->dev,
+ 			     dev_name(dev->dev));
+@@ -175,7 +185,11 @@ static int ssb_ehci_attach(struct ssb_de
+ 	if (err)
+ 		goto err_iounmap;
+ 
+#ifndef CONFIG_USB_OHCI_HCD_SSB
+ 	ssb_set_drvdata(dev, hcd);
+#else
+	*ehci_hcd = hcd;
+#endif
+ 
+ 	return err;
+ 
+@@ -187,7 +201,9 @@ err_dev_disable:
+ 	ssb_device_disable(dev, 0);
+ 	return err;
+ }
+EXPORT_SYMBOL_GPL(ssb_ehci_attach);
+ 
+#ifndef CONFIG_USB_OHCI_HCD_SSB
+ static int ssb_ehci_probe(struct ssb_device *dev,
+ 		const struct ssb_device_id *id)
+ {
+@@ -238,6 +254,7 @@ static int ssb_ehci_resume(struct ssb_de
+ #define ssb_ehci_suspend	NULL
+ #define ssb_ehci_resume	NULL
+ #endif /* CONFIG_PM */
+#endif /* !CONFIG_USB_OHCI_HCD_SSB */
+ 
+ static const struct ssb_device_id ssb_ehci_table[] = {
+ 	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
+@@ -245,6 +262,8 @@ static const struct ssb_device_id ssb_eh
+ };
+ MODULE_DEVICE_TABLE(ssb, ssb_ehci_table);
+ 
+
+#ifndef CONFIG_USB_OHCI_HCD_SSB
+ static struct ssb_driver ssb_ehci_driver = {
+ 	.name		= KBUILD_MODNAME,
+ 	.id_table	= ssb_ehci_table,
+@@ -253,3 +272,4 @@ static struct ssb_driver ssb_ehci_driver
+ 	.suspend	= ssb_ehci_suspend,
+ 	.resume		= ssb_ehci_resume,
+ };
+#endif
+--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
+@@ -1322,17 +1322,21 @@ static int __init ehci_hcd_init(void)
+ 		goto clean4;
+ #endif
+ 
+#ifndef CONFIG_USB_OHCI_HCD_SSB
+ #ifdef SSB_EHCI_DRIVER
+ 	retval = ssb_driver_register(&SSB_EHCI_DRIVER);
+ 	if (retval < 0)
+ 		goto clean5;
+ #endif
+#endif /* !CONFIG_USB_OHCI_HCD_SSB */
+ 	return retval;
+ 
+#ifndef CONFIG_USB_OHCI_HCD_SSB
+ #ifdef SSB_EHCI_DRIVER
+ 	/* ssb_driver_unregister(&SSB_EHCI_DRIVER); */
+ clean5:
+ #endif
+#endif /* !CONFIG_USB_OHCI_HCD_SSB */
+ #ifdef XILINX_OF_PLATFORM_DRIVER
+ 	of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
+ clean4:
+@@ -1365,9 +1369,11 @@ module_init(ehci_hcd_init);
+ 
+ static void __exit ehci_hcd_cleanup(void)
+ {
+#ifndef CONFIG_USB_OHCI_HCD_SSB
+ #ifdef SSB_EHCI_DRIVER
+ 	ssb_driver_unregister(&SSB_EHCI_DRIVER);
+ #endif
+#endif /* !CONFIG_USB_OHCI_HCD_SSB */
+ #ifdef XILINX_OF_PLATFORM_DRIVER
+ 	of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
+ #endif
--- a/target/linux/brcm47xx/patches-2.6.38/040-bcm47xx-add-gpio_set_debounce.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/040-bcm47xx-add-gpio_set_debounce.patch
@ -0,0 +1,13 @@
+--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
+@@ -58,6 +58,10 @@ static inline int gpio_polarity(unsigned
+ 	return 0;
+ }
+ 
+static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
+{
+	return -ENOSYS;
+}
+ 
+ /* cansleep wrappers */
+ #include <asm-generic/gpio.h>
--- a/target/linux/brcm47xx/patches-2.6.38/110-flash_map.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/110-flash_map.patch
@ -0,0 +1,25 @@
+--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
+@@ -328,6 +328,12 @@ config MTD_CFI_FLAGADM
+ 	  Mapping for the Flaga digital module. If you don't have one, ignore
+ 	  this setting.
+ 
+config MTD_BCM47XX
+	tristate "BCM47xx flash device"
+	depends on MIPS && MTD_CFI && BCM47XX
+	help
+	  Support for the flash chips on the BCM947xx board.
+
+ config MTD_SOLUTIONENGINE
+ 	tristate "CFI Flash device mapped on Hitachi SolutionEngine"
+ 	depends on SUPERH && SOLUTION_ENGINE && MTD_CFI && MTD_REDBOOT_PARTS
+--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_MTD_PMC_MSP_EVM)   += pmcms
+ obj-$(CONFIG_MTD_PCMCIA)	+= pcmciamtd.o
+ obj-$(CONFIG_MTD_RPXLITE)	+= rpxlite.o
+ obj-$(CONFIG_MTD_TQM8XXL)	+= tqm8xxl.o
+obj-$(CONFIG_MTD_BCM47XX)	+= bcm47xx-flash.o
+ obj-$(CONFIG_MTD_SA1100)	+= sa1100-flash.o
+ obj-$(CONFIG_MTD_SBC_GXX)	+= sbc_gxx.o
+ obj-$(CONFIG_MTD_SC520CDP)	+= sc520cdp.o
--- a/target/linux/brcm47xx/patches-2.6.38/150-cpu_fixes.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/150-cpu_fixes.patch
@ -0,0 +1,367 @@
+--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
+@@ -17,6 +17,20 @@
+ #include <asm/cpu-features.h>
+ #include <asm/mipsmtregs.h>
+ 
+#ifdef CONFIG_BCM47XX
+#include <asm/paccess.h>
+#include <linux/ssb/ssb.h>
+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
+
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
+#else
+#define BCM4710_DUMMY_RREG()
+
+#define BCM4710_FILL_TLB(addr)
+#define BCM4710_PROTECTED_FILL_TLB(addr)
+#endif
+
+ /*
+  * This macro return a properly sign-extended address suitable as base address
+  * for indexed cache operations.  Two issues here:
+@@ -150,6 +164,7 @@ static inline void flush_icache_line_ind
+ static inline void flush_dcache_line_indexed(unsigned long addr)
+ {
+ 	__dflush_prologue
+	BCM4710_DUMMY_RREG();
+ 	cache_op(Index_Writeback_Inv_D, addr);
+ 	__dflush_epilogue
+ }
+@@ -169,6 +184,7 @@ static inline void flush_icache_line(uns
+ static inline void flush_dcache_line(unsigned long addr)
+ {
+ 	__dflush_prologue
+	BCM4710_DUMMY_RREG();
+ 	cache_op(Hit_Writeback_Inv_D, addr);
+ 	__dflush_epilogue
+ }
+@@ -176,6 +192,7 @@ static inline void flush_dcache_line(uns
+ static inline void invalidate_dcache_line(unsigned long addr)
+ {
+ 	__dflush_prologue
+	BCM4710_DUMMY_RREG();
+ 	cache_op(Hit_Invalidate_D, addr);
+ 	__dflush_epilogue
+ }
+@@ -208,6 +225,7 @@ static inline void flush_scache_line(uns
+  */
+ static inline void protected_flush_icache_line(unsigned long addr)
+ {
+	BCM4710_DUMMY_RREG();
+ 	protected_cache_op(Hit_Invalidate_I, addr);
+ }
+ 
+@@ -219,6 +237,7 @@ static inline void protected_flush_icach
+  */
+ static inline void protected_writeback_dcache_line(unsigned long addr)
+ {
+	BCM4710_DUMMY_RREG();
+ 	protected_cache_op(Hit_Writeback_Inv_D, addr);
+ }
+ 
+@@ -339,8 +358,52 @@ static inline void invalidate_tcache_pag
+ 		: "r" (base),						\
+ 		  "i" (op));
+ 
+static inline void blast_dcache(void)
+{
+	unsigned long start = KSEG0;
+	unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
+	unsigned long end = (start + dcache_size);
+
+	do {
+		BCM4710_DUMMY_RREG();
+		cache_op(Index_Writeback_Inv_D, start);
+		start += current_cpu_data.dcache.linesz;
+	} while(start < end);
+}
+
+static inline void blast_dcache_page(unsigned long page)
+{
+	unsigned long start = page;
+	unsigned long end = start + PAGE_SIZE;
+
+	BCM4710_FILL_TLB(start);
+	do {
+		BCM4710_DUMMY_RREG();
+		cache_op(Hit_Writeback_Inv_D, start);
+		start += current_cpu_data.dcache.linesz;
+	} while(start < end);
+}
+
+static inline void blast_dcache_page_indexed(unsigned long page)
+{
+	unsigned long start = page;
+	unsigned long end = start + PAGE_SIZE;
+	unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
+	unsigned long ws_end = current_cpu_data.dcache.ways <<
+	                       current_cpu_data.dcache.waybit;
+	unsigned long ws, addr;
+	for (ws = 0; ws < ws_end; ws += ws_inc) {
+		start = page + ws;
+		for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
+			BCM4710_DUMMY_RREG();
+			cache_op(Index_Writeback_Inv_D, addr);
+		}
+	}
+}
+
+
+ /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
+-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
+ static inline void blast_##pfx##cache##lsize(void)			\
+ {									\
+ 	unsigned long start = INDEX_BASE;				\
+@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##l
+ 									\
+ 	__##pfx##flush_prologue						\
+ 									\
+	war								\
+ 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
+ 		for (addr = start; addr < end; addr += lsize * 32)	\
+ 			cache##lsize##_unroll32(addr|ws, indexop);	\
+@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##l
+ 									\
+ 	__##pfx##flush_prologue						\
+ 									\
+	war								\
+ 	do {								\
+ 		cache##lsize##_unroll32(start, hitop);			\
+ 		start += lsize * 32;					\
+@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##l
+ 	                       current_cpu_data.desc.waybit;		\
+ 	unsigned long ws, addr;						\
+ 									\
+	war								\
+									\
+ 	__##pfx##flush_prologue						\
+ 									\
+ 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
+@@ -393,36 +460,38 @@ static inline void blast_##pfx##cache##l
+ 	__##pfx##flush_epilogue						\
+ }
+ 
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
+-
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
+
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
+ 
+ /* build blast_xxx_range, protected_blast_xxx_range */
+-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
+ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
+ 						    unsigned long end)	\
+ {									\
+ 	unsigned long lsize = cpu_##desc##_line_size();			\
+ 	unsigned long addr = start & ~(lsize - 1);			\
+ 	unsigned long aend = (end - 1) & ~(lsize - 1);			\
+	war								\
+ 									\
+ 	__##pfx##flush_prologue						\
+ 									\
+ 	while (1) {							\
+		war2						\
+ 		prot##cache_op(hitop, addr);				\
+ 		if (addr == aend)					\
+ 			break;						\
+@@ -432,13 +501,13 @@ static inline void prot##blast_##pfx##ca
+ 	__##pfx##flush_epilogue						\
+ }
+ 
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
+-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
+ /* blast_inv_dcache_range */
+-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
+-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
+ 
+ #endif /* _ASM_R4KCACHE_H */
+--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
+@@ -449,6 +449,10 @@
+ 		.macro	RESTORE_SP_AND_RET
+ 		LONG_L	sp, PT_R29(sp)
+ 		.set	mips3
+#ifdef CONFIG_BCM47XX
+		nop
+		nop
+#endif
+ 		eret
+ 		.set	mips0
+ 		.endm
+--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
+@@ -52,6 +52,10 @@ NESTED(except_vec1_generic, 0, sp)
+ NESTED(except_vec3_generic, 0, sp)
+ 	.set	push
+ 	.set	noat
+#ifdef CONFIG_BCM47XX
+	nop
+	nop
+#endif
+ #if R5432_CP0_INTERRUPT_WAR
+ 	mfc0	k0, CP0_INDEX
+ #endif
+--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
+@@ -35,6 +35,9 @@
+ #include <asm/cacheflush.h> /* for run_uncached() */
+ 
+ 
+/* For enabling BCM4710 cache workarounds */
+int bcm4710 = 0;
+
+ /*
+  * Special Variant of smp_call_function for use by cache functions:
+  *
+@@ -111,6 +114,9 @@ static void __cpuinit r4k_blast_dcache_p
+ {
+ 	unsigned long  dc_lsize = cpu_dcache_line_size();
+ 
+	if (bcm4710)
+		r4k_blast_dcache_page = blast_dcache_page;
+	else
+ 	if (dc_lsize == 0)
+ 		r4k_blast_dcache_page = (void *)cache_noop;
+ 	else if (dc_lsize == 16)
+@@ -127,6 +133,9 @@ static void __cpuinit r4k_blast_dcache_p
+ {
+ 	unsigned long dc_lsize = cpu_dcache_line_size();
+ 
+	if (bcm4710)
+		r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
+	else
+ 	if (dc_lsize == 0)
+ 		r4k_blast_dcache_page_indexed = (void *)cache_noop;
+ 	else if (dc_lsize == 16)
+@@ -143,6 +152,9 @@ static void __cpuinit r4k_blast_dcache_s
+ {
+ 	unsigned long dc_lsize = cpu_dcache_line_size();
+ 
+	if (bcm4710)
+		r4k_blast_dcache = blast_dcache;
+	else
+ 	if (dc_lsize == 0)
+ 		r4k_blast_dcache = (void *)cache_noop;
+ 	else if (dc_lsize == 16)
+@@ -679,6 +691,8 @@ static void local_r4k_flush_cache_sigtra
+ 	unsigned long addr = (unsigned long) arg;
+ 
+ 	R4600_HIT_CACHEOP_WAR_IMPL;
+	BCM4710_PROTECTED_FILL_TLB(addr);
+	BCM4710_PROTECTED_FILL_TLB(addr + 4);
+ 	if (dc_lsize)
+ 		protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
+ 	if (!cpu_icache_snoops_remote_store && scache_size)
+@@ -1310,6 +1324,17 @@ static void __cpuinit coherency_setup(vo
+ 	 * silly idea of putting something else there ...
+ 	 */
+ 	switch (current_cpu_type()) {
+	case CPU_BMIPS3300:
+		{
+			u32 cm;
+			cm = read_c0_diag();
+			/* Enable icache */
+			cm |= (1 << 31);
+			/* Enable dcache */
+			cm |= (1 << 30);
+			write_c0_diag(cm);
+		}
+		break;
+ 	case CPU_R4000PC:
+ 	case CPU_R4000SC:
+ 	case CPU_R4000MC:
+@@ -1366,6 +1391,15 @@ void __cpuinit r4k_cache_init(void)
+ 		break;
+ 	}
+ 
+	/* Check if special workarounds are required */
+#ifdef CONFIG_BCM47XX
+	if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
+		printk("Enabling BCM4710A0 cache workarounds.\n");
+		bcm4710 = 1;
+	} else
+#endif
+		bcm4710 = 0;
+
+ 	probe_pcache();
+ 	setup_scache();
+ 
+@@ -1424,5 +1458,13 @@ void __cpuinit r4k_cache_init(void)
+ #if !defined(CONFIG_MIPS_CMP)
+ 	local_r4k___flush_cache_all(NULL);
+ #endif
+#ifdef CONFIG_BCM47XX
+	{
+		static void (*_coherency_setup)(void);
+		_coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
+		_coherency_setup();
+	}
+#else
+ 	coherency_setup();
+#endif
+ }
+--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
+@@ -1187,6 +1187,9 @@ static void __cpuinit build_r4000_tlb_re
+ 			/* No need for uasm_i_nop */
+ 		}
+ 
+#ifdef CONFIG_BCM47XX
+		uasm_i_nop(&p);
+#endif
+ #ifdef CONFIG_64BIT
+ 		build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
+ #else
+@@ -1706,6 +1709,9 @@ build_r4000_tlbchange_handler_head(u32 *
+ 				   struct uasm_reloc **r, unsigned int pte,
+ 				   unsigned int ptr)
+ {
+#ifdef CONFIG_BCM47XX
+	uasm_i_nop(p);
+#endif
+ #ifdef CONFIG_64BIT
+ 	build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
+ #else
--- a/target/linux/brcm47xx/patches-2.6.38/160-kmap_coherent.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/160-kmap_coherent.patch
@ -0,0 +1,77 @@
+--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
+@@ -110,6 +110,9 @@
+ #ifndef cpu_has_pindexed_dcache
+ #define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+ #endif
+#ifndef cpu_use_kmap_coherent
+#define cpu_use_kmap_coherent 1
+#endif
+ 
+ /*
+  * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
+--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
+@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_use_kmap_coherent	0
+
+#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
+--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
+@@ -507,7 +507,7 @@ static inline void local_r4k_flush_cache
+ 		 */
+ 		map_coherent = (cpu_has_dc_aliases &&
+ 				page_mapped(page) && !Page_dcache_dirty(page));
+-		if (map_coherent)
+		if (map_coherent && cpu_use_kmap_coherent)
+ 			vaddr = kmap_coherent(page, addr);
+ 		else
+ 			vaddr = kmap_atomic(page, KM_USER0);
+@@ -530,7 +530,7 @@ static inline void local_r4k_flush_cache
+ 	}
+ 
+ 	if (vaddr) {
+-		if (map_coherent)
+		if (map_coherent && cpu_use_kmap_coherent)
+ 			kunmap_coherent();
+ 		else
+ 			kunmap_atomic(vaddr, KM_USER0);
+--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
+@@ -210,7 +210,7 @@ void copy_user_highpage(struct page *to,
+ 	void *vfrom, *vto;
+ 
+ 	vto = kmap_atomic(to, KM_USER1);
+-	if (cpu_has_dc_aliases &&
+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ 	    page_mapped(from) && !Page_dcache_dirty(from)) {
+ 		vfrom = kmap_coherent(from, vaddr);
+ 		copy_page(vto, vfrom);
+@@ -232,7 +232,7 @@ void copy_to_user_page(struct vm_area_st
+ 	struct page *page, unsigned long vaddr, void *dst, const void *src,
+ 	unsigned long len)
+ {
+-	if (cpu_has_dc_aliases &&
+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ 	    page_mapped(page) && !Page_dcache_dirty(page)) {
+ 		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ 		memcpy(vto, src, len);
+@@ -250,7 +250,7 @@ void copy_from_user_page(struct vm_area_
+ 	struct page *page, unsigned long vaddr, void *dst, const void *src,
+ 	unsigned long len)
+ {
+-	if (cpu_has_dc_aliases &&
+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ 	    page_mapped(page) && !Page_dcache_dirty(page)) {
+ 		void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ 		memcpy(dst, vfrom, len);
--- a/target/linux/brcm47xx/patches-2.6.38/210-b44_phy_fix.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/210-b44_phy_fix.patch
@ -0,0 +1,61 @@
+--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
+@@ -411,10 +411,41 @@ static void b44_wap54g10_workaround(stru
+ error:
+ 	pr_warning("PHY: cannot reset MII transceiver isolate bit\n");
+ }
+
+static inline int startswith (const char *source, const char *cmp) 
+{ 
+       return !strncmp(source,cmp,strlen(cmp)); 
+}
+
+static inline void b44_bcm47xx_workarounds(struct b44 *bp)
+{
+	char buf[20];
+	/* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */
+	if (nvram_getenv("boardnum", buf, sizeof(buf)) > 0)
+		return;
+	if (simple_strtoul(buf, NULL, 0) == 100) {
+		bp->phy_addr = B44_PHY_ADDR_NO_PHY;
+	} else {
+		/* WL-HDD */
+		struct ssb_device *sdev = bp->sdev;
+		if (nvram_getenv("hardware_version", buf, sizeof(buf)) > 0)
+			return;
+		if (startswith(buf, "WL300-")) {
+			if (sdev->bus->sprom.et0phyaddr == 0 &&
+			    sdev->bus->sprom.et1phyaddr == 1)
+				bp->phy_addr = B44_PHY_ADDR_NO_PHY;
+		}
+	}
+	return;
+}
+ #else
+ static inline void b44_wap54g10_workaround(struct b44 *bp)
+ {
+ }
+
+static inline void b44_bcm47xx_workarounds(struct b44 *bp)
+{
+}
+ #endif
+ 
+ static int b44_setup_phy(struct b44 *bp)
+@@ -423,6 +454,7 @@ static int b44_setup_phy(struct b44 *bp)
+ 	int err;
+ 
+ 	b44_wap54g10_workaround(bp);
+	b44_bcm47xx_workarounds(bp);
+ 
+ 	if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
+ 		return 0;
+@@ -2088,6 +2120,8 @@ static int __devinit b44_get_invariants(
+ 	 * valid PHY address. */
+ 	bp->phy_addr &= 0x1F;
+ 
+	b44_bcm47xx_workarounds(bp);
+
+ 	memcpy(bp->dev->dev_addr, addr, 6);
+ 
+ 	if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
--- a/target/linux/brcm47xx/patches-2.6.38/211-b44_timeout_spam.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/211-b44_timeout_spam.patch
@ -0,0 +1,15 @@
+--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
+@@ -188,10 +188,11 @@ static int b44_wait_bit(struct b44 *bp,
+ 		udelay(10);
+ 	}
+ 	if (i == timeout) {
+#if 0
+ 		if (net_ratelimit())
+ 			netdev_err(bp->dev, "BUG!  Timeout waiting for bit %08x of register %lx to %s\n",
+ 				   bit, reg, clear ? "clear" : "set");
+-
+#endif
+ 		return -ENODEV;
+ 	}
+ 	return 0;
--- a/target/linux/brcm47xx/patches-2.6.38/220-bcm5354.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/220-bcm5354.patch
@ -0,0 +1,42 @@
+--- a/drivers/ssb/driver_chipcommon.c
+++ b/drivers/ssb/driver_chipcommon.c
+@@ -285,6 +285,8 @@ void ssb_chipco_resume(struct ssb_chipco
+ void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
+                              u32 *plltype, u32 *n, u32 *m)
+ {
+	if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
+		return;
+ 	*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
+ 	*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
+ 	switch (*plltype) {
+@@ -308,6 +310,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
+ void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
+ 				 u32 *plltype, u32 *n, u32 *m)
+ {
+	if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
+		return;
+ 	*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
+ 	*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
+ 	switch (*plltype) {
+--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
+@@ -217,6 +217,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
+ 
+ 	if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
+ 		rate = 200000000;
+	} else if (bus->chip_id == 0x5354) {
+		rate = 240000000;
+ 	} else {
+ 		rate = ssb_calc_clock_rate(pll_type, n, m);
+ 	}
+--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
+@@ -1103,6 +1103,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
+ 
+ 	if (bus->chip_id == 0x5365) {
+ 		rate = 100000000;
+	} else if (bus->chip_id == 0x5354) {
+		rate = 120000000;
+ 	} else {
+ 		rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
+ 		if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
--- a/target/linux/brcm47xx/patches-2.6.38/280-activate_ssb_support_in_usb.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/280-activate_ssb_support_in_usb.patch
@ -0,0 +1,16 @@
+This prevents the options from being delete with make kernel_oldconfig.
+---
+ drivers/ssb/Kconfig |    2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/ssb/Kconfig
+++ b/drivers/ssb/Kconfig
+@@ -141,6 +141,8 @@ config SSB_DRIVER_MIPS
+ config SSB_EMBEDDED
+ 	bool
+ 	depends on SSB_DRIVER_MIPS
+	select USB_EHCI_HCD_SSB if USB_EHCI_HCD
+	select USB_OHCI_HCD_SSB if USB_OHCI_HCD
+ 	default y
+ 
+ config SSB_DRIVER_EXTIF
--- a/target/linux/brcm47xx/patches-2.6.38/300-fork_cacheflush.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/300-fork_cacheflush.patch
@ -0,0 +1,11 @@
+--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
+@@ -32,7 +32,7 @@
+ extern void (*flush_cache_all)(void);
+ extern void (*__flush_cache_all)(void);
+ extern void (*flush_cache_mm)(struct mm_struct *mm);
+-#define flush_cache_dup_mm(mm)	do { (void) (mm); } while (0)
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+ extern void (*flush_cache_range)(struct vm_area_struct *vma,
+ 	unsigned long start, unsigned long end);
+ extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
--- a/target/linux/brcm47xx/patches-2.6.38/301-kmod-fuse-dcache-bug-r4k.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/301-kmod-fuse-dcache-bug-r4k.patch
@ -0,0 +1,28 @@
+--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
+@@ -373,7 +373,7 @@ static inline void local_r4k___flush_cac
+ 	}
+ }
+ 
+-static void r4k___flush_cache_all(void)
+void r4k___flush_cache_all(void)
+ {
+ 	r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
+ }
+@@ -537,7 +537,7 @@ static inline void local_r4k_flush_cache
+ 	}
+ }
+ 
+-static void r4k_flush_cache_page(struct vm_area_struct *vma,
+void r4k_flush_cache_page(struct vm_area_struct *vma,
+ 	unsigned long addr, unsigned long pfn)
+ {
+ 	struct flush_cache_page_args args;
+@@ -1468,3 +1468,7 @@ void __cpuinit r4k_cache_init(void)
+ 	coherency_setup();
+ #endif
+ }
+
+/* fuse package DCACHE BUG patch exports */
+void (*fuse_flush_cache_all)(void) = r4k___flush_cache_all;
+EXPORT_SYMBOL(fuse_flush_cache_all);
--- a/target/linux/brcm47xx/patches-2.6.38/302-kmod-fuse-dcache-bug-fuse.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/302-kmod-fuse-dcache-bug-fuse.patch
@ -0,0 +1,46 @@
+--- a/fs/fuse/dev.c
+++ b/fs/fuse/dev.c
+@@ -647,11 +647,20 @@ static int fuse_copy_fill(struct fuse_co
+ 	return lock_request(cs->fc, cs->req);
+ }
+ 
+#ifdef DCACHE_BUG
+extern void (*fuse_flush_cache_all)(void);
+#endif
+
+ /* Do as much copy to/from userspace buffer as we can */
+ static int fuse_copy_do(struct fuse_copy_state *cs, void **val, unsigned *size)
+ {
+ 	unsigned ncpy = min(*size, cs->len);
+ 	if (val) {
+#ifdef DCACHE_BUG
+		// patch from mailing list, it is very important, otherwise,
+		// can't mount, or ls mount point will hang
+		fuse_flush_cache_all();
+#endif
+ 		if (cs->write)
+ 			memcpy(cs->buf, *val, ncpy);
+ 		else
+--- a/fs/fuse/fuse_i.h
+++ b/fs/fuse/fuse_i.h
+@@ -8,6 +8,7 @@
+ 
+ #ifndef _FS_FUSE_I_H
+ #define _FS_FUSE_I_H
+#define DCACHE_BUG
+ 
+ #include <linux/fuse.h>
+ #include <linux/fs.h>
+--- a/fs/fuse/inode.c
+++ b/fs/fuse/inode.c
+@@ -1199,6 +1199,10 @@ static int __init fuse_init(void)
+ 	printk(KERN_INFO "fuse init (API version %i.%i)\n",
+ 	       FUSE_KERNEL_VERSION, FUSE_KERNEL_MINOR_VERSION);
+ 
+#ifdef DCACHE_BUG
+	printk("fuse init DCACHE_BUG workaround enabled\n");
+#endif
+
+ 	INIT_LIST_HEAD(&fuse_conn_list);
+ 	res = fuse_fs_init();
+ 	if (res)
--- a/target/linux/brcm47xx/patches-2.6.38/310-no_highpage.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/310-no_highpage.patch
@ -0,0 +1,66 @@
+--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
+@@ -43,6 +43,7 @@
+ #ifndef __ASSEMBLY__
+ 
+ #include <linux/pfn.h>
+#include <asm/cpu-features.h>
+ #include <asm/io.h>
+ 
+ extern void build_clear_page(void);
+@@ -78,13 +79,16 @@ static inline void clear_user_page(void
+ 		flush_data_cache_page((unsigned long)addr);
+ }
+ 
+-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+-	struct page *to);
+-struct vm_area_struct;
+-extern void copy_user_highpage(struct page *to, struct page *from,
+-	unsigned long vaddr, struct vm_area_struct *vma);
+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+	struct page *to)
+{
+	extern void (*flush_data_cache_page)(unsigned long addr);
+ 
+-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
+	copy_page(vto, vfrom);
+	if (!cpu_has_ic_fills_f_dc ||
+	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+		flush_data_cache_page((unsigned long)vto);
+}
+ 
+ /*
+  * These are used to make use of C type-checking..
+--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
+@@ -204,30 +204,6 @@ void kunmap_coherent(void)
+ 	preempt_check_resched();
+ }
+ 
+-void copy_user_highpage(struct page *to, struct page *from,
+-	unsigned long vaddr, struct vm_area_struct *vma)
+-{
+-	void *vfrom, *vto;
+-
+-	vto = kmap_atomic(to, KM_USER1);
+-	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+-	    page_mapped(from) && !Page_dcache_dirty(from)) {
+-		vfrom = kmap_coherent(from, vaddr);
+-		copy_page(vto, vfrom);
+-		kunmap_coherent();
+-	} else {
+-		vfrom = kmap_atomic(from, KM_USER0);
+-		copy_page(vto, vfrom);
+-		kunmap_atomic(vfrom, KM_USER0);
+-	}
+-	if ((!cpu_has_ic_fills_f_dc) ||
+-	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+-		flush_data_cache_page((unsigned long)vto);
+-	kunmap_atomic(vto, KM_USER1);
+-	/* Make sure this page is cleared on other CPU's too before using it */
+-	smp_wmb();
+-}
+-
+ void copy_to_user_page(struct vm_area_struct *vma,
+ 	struct page *page, unsigned long vaddr, void *dst, const void *src,
+ 	unsigned long len)
--- a/target/linux/brcm47xx/patches-2.6.38/400-arch-bcm47xx.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/400-arch-bcm47xx.patch
@ -0,0 +1,56 @@
+--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
+@@ -92,3 +92,30 @@ int nvram_getenv(char *name, char *val,
+ 	return NVRAM_ERR_ENVNOTFOUND;
+ }
+ EXPORT_SYMBOL(nvram_getenv);
+
+char *nvram_get(const char *name)
+{
+	char *var, *value, *end, *eq;
+
+	if (!name)
+		return NULL;
+
+	if (!nvram_buf[0])
+		early_nvram_init();
+
+	/* Look for name=value and return value */
+	var = &nvram_buf[sizeof(struct nvram_header)];
+	end = nvram_buf + sizeof(nvram_buf) - 2;
+	end[0] = end[1] = '\0';
+	for (; *var; var = value + strlen(value) + 1) {
+		eq = strchr(var, '=');
+		if (!eq)
+			break;
+		value = eq + 1;
+		if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
+			return value;
+	}
+
+	return NULL;
+}
+EXPORT_SYMBOL(nvram_get);
+--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
+@@ -226,3 +226,20 @@ void __init plat_mem_setup(void)
+ 	_machine_halt = bcm47xx_machine_halt;
+ 	pm_power_off = bcm47xx_machine_halt;
+ }
+
+static int __init bcm47xx_register_gpiodev(void)
+{
+	static struct resource res = {
+		.start = 0xFFFFFFFF,
+	};
+	struct platform_device *pdev;
+
+	pdev = platform_device_register_simple("GPIODEV", 0, &res, 1);
+	if (!pdev) {
+		printk(KERN_ERR "bcm47xx: GPIODEV init failed\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+device_initcall(bcm47xx_register_gpiodev);
--- a/target/linux/brcm47xx/patches-2.6.38/601-mips-remove-pci-collision-check.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/601-mips-remove-pci-collision-check.patch
@ -0,0 +1,18 @@
+--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
+@@ -185,12 +185,10 @@ static int pcibios_enable_resources(stru
+ 		if ((idx == PCI_ROM_RESOURCE) &&
+ 				(!(r->flags & IORESOURCE_ROM_ENABLE)))
+ 			continue;
+-		if (!r->start && r->end) {
+-			printk(KERN_ERR "PCI: Device %s not available "
+-			       "because of resource collisions\n",
+		if (!r->start && r->end)
+			printk(KERN_WARNING "PCI: Device %s resource"
+			       "collisions detected. Ignoring...\n",
+ 			       pci_name(dev));
+-			return -EINVAL;
+-		}
+ 		if (r->flags & IORESOURCE_IO)
+ 			cmd |= PCI_COMMAND_IO;
+ 		if (r->flags & IORESOURCE_MEM)
--- a/target/linux/brcm47xx/patches-2.6.38/610-pci_ide_fix.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/610-pci_ide_fix.patch
@ -0,0 +1,14 @@
+--- a/include/linux/ide.h
+++ b/include/linux/ide.h
+@@ -195,7 +195,11 @@ static inline void ide_std_init_ports(st
+ 	hw->io_ports.ctl_addr = ctl_addr;
+ }
+ 
+#if defined CONFIG_BCM47XX
+# define MAX_HWIFS	2
+#else
+ #define MAX_HWIFS	10
+#endif
+ 
+ /*
+  * Now for the data we need to maintain per-drive:  ide_drive_t
--- a/target/linux/brcm47xx/patches-2.6.38/700-ssb-gigabit-ethernet-driver.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/700-ssb-gigabit-ethernet-driver.patch
@ -0,0 +1,328 @@
+--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
+@@ -43,6 +43,7 @@
+ #include <linux/prefetch.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/firmware.h>
+#include <linux/ssb/ssb_driver_gige.h>
+ 
+ #include <net/checksum.h>
+ #include <net/ip.h>
+@@ -488,8 +489,9 @@ static void _tw32_flush(struct tg3 *tp,
+ static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
+ {
+ 	tp->write32_mbox(tp, off, val);
+-	if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
+-	    !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
+	if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
+	    (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
+	     !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
+ 		tp->read32_mbox(tp, off);
+ }
+ 
+@@ -499,7 +501,7 @@ static void tg3_write32_tx_mbox(struct t
+ 	writel(val, mbox);
+ 	if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
+ 		writel(val, mbox);
+-	if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
+	if ((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES))
+ 		readl(mbox);
+ }
+ 
+@@ -782,7 +784,7 @@ static void tg3_switch_clocks(struct tg3
+ 
+ #define PHY_BUSY_LOOPS	5000
+ 
+-static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
+static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
+ {
+ 	u32 frame_val;
+ 	unsigned int loops;
+@@ -796,7 +798,7 @@ static int tg3_readphy(struct tg3 *tp, i
+ 
+ 	*val = 0x0;
+ 
+-	frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
+	frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
+ 		      MI_COM_PHY_ADDR_MASK);
+ 	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
+ 		      MI_COM_REG_ADDR_MASK);
+@@ -831,7 +833,12 @@ static int tg3_readphy(struct tg3 *tp, i
+ 	return ret;
+ }
+ 
+-static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
+static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
+{
+	return __tg3_readphy(tp, tp->phy_addr, reg, val);
+}
+
+static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
+ {
+ 	u32 frame_val;
+ 	unsigned int loops;
+@@ -847,7 +854,7 @@ static int tg3_writephy(struct tg3 *tp,
+ 		udelay(80);
+ 	}
+ 
+-	frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
+	frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
+ 		      MI_COM_PHY_ADDR_MASK);
+ 	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
+ 		      MI_COM_REG_ADDR_MASK);
+@@ -880,6 +887,11 @@ static int tg3_writephy(struct tg3 *tp,
+ 	return ret;
+ }
+ 
+static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
+{
+	return __tg3_writephy(tp, tp->phy_addr, reg, val);
+}
+
+ static int tg3_bmcr_reset(struct tg3 *tp)
+ {
+ 	u32 phy_control;
+@@ -2467,6 +2479,9 @@ static int tg3_nvram_read(struct tg3 *tp
+ {
+ 	int ret;
+ 
+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
+		return -ENODEV;
+
+ 	if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
+ 		return tg3_nvram_read_using_eeprom(tp, offset, val);
+ 
+@@ -2791,8 +2806,10 @@ static int tg3_power_down_prepare(struct
+ 	tg3_frob_aux_power(tp);
+ 
+ 	/* Workaround for unstable PLL clock */
+-	if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
+-	    (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
+	if ((tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_2 &&
+				/* !!! FIXME !!! */
+	    ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
+	    (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
+ 		u32 val = tr32(0x7d00);
+ 
+ 		val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
+@@ -3311,6 +3328,14 @@ relink:
+ 	if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
+ 		tg3_phy_copper_begin(tp);
+ 
+		if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
+			current_link_up = 1;
+			current_speed = SPEED_1000; /* FIXME */
+			current_duplex = DUPLEX_FULL;
+			tp->link_config.active_speed = current_speed;
+			tp->link_config.active_duplex = current_duplex;
+		}
+
+ 		tg3_readphy(tp, MII_BMSR, &bmsr);
+ 		if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
+ 		    (bmsr & BMSR_LSTATUS))
+@@ -6887,6 +6912,11 @@ static int tg3_poll_fw(struct tg3 *tp)
+ 	int i;
+ 	u32 val;
+ 
+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
+		/* We don't use firmware. */
+		return 0;
+	}
+
+ 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+ 		/* Wait up to 20ms for init done. */
+ 		for (i = 0; i < 200; i++) {
+@@ -7177,6 +7207,14 @@ static int tg3_chip_reset(struct tg3 *tp
+ 		tw32(0x5000, 0x400);
+ 	}
+ 
+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
+		/* BCM4785: In order to avoid repercussions from using potentially
+		 * defective internal ROM, stop the Rx RISC CPU, which is not
+		 * required. */
+		tg3_stop_fw(tp);
+		tg3_halt_cpu(tp, RX_CPU_BASE);
+	}
+
+ 	tw32(GRC_MODE, tp->grc_mode);
+ 
+ 	if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
+@@ -7331,9 +7369,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
+ 		return -ENODEV;
+ 	}
+ 
+-	/* Clear firmware's nvram arbitration. */
+-	if (tp->tg3_flags & TG3_FLAG_NVRAM)
+-		tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
+	if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
+		/* Clear firmware's nvram arbitration. */
+		if (tp->tg3_flags & TG3_FLAG_NVRAM)
+			tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
+	}
+
+ 	return 0;
+ }
+ 
+@@ -7396,6 +7437,11 @@ static int tg3_load_5701_a0_firmware_fix
+ 	const __be32 *fw_data;
+ 	int err, i;
+ 
+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
+		/* We don't use firmware. */
+		return 0;
+	}
+
+ 	fw_data = (void *)tp->fw->data;
+ 
+ 	/* Firmware blob starts with version numbers, followed by
+@@ -7454,6 +7500,11 @@ static int tg3_load_tso_firmware(struct
+ 	unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
+ 	int err, i;
+ 
+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
+		/* We don't use firmware. */
+		return 0;
+	}
+
+ 	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
+ 		return 0;
+ 
+@@ -8671,6 +8722,11 @@ static void tg3_timer(unsigned long __op
+ 
+ 	spin_lock(&tp->lock);
+ 
+	if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
+		/* BCM4785: Flush posted writes from GbE to host memory. */
+		tr32(HOSTCC_MODE);
+	}
+
+ 	if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
+ 		/* All of this garbage is because when using non-tagged
+ 		 * IRQ status the mailbox/status_block protocol the chip
+@@ -10341,6 +10397,11 @@ static int tg3_test_nvram(struct tg3 *tp
+ 	if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
+ 		return 0;
+ 
+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
+		/* We don't have NVRAM. */
+		return 0;
+	}
+
+ 	if (tg3_nvram_read(tp, 0, &magic) != 0)
+ 		return -EIO;
+ 
+@@ -11164,7 +11225,7 @@ static int tg3_ioctl(struct net_device *
+ 			return -EAGAIN;
+ 
+ 		spin_lock_bh(&tp->lock);
+-		err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
+		err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
+ 		spin_unlock_bh(&tp->lock);
+ 
+ 		data->val_out = mii_regval;
+@@ -11182,7 +11243,7 @@ static int tg3_ioctl(struct net_device *
+ 			return -EAGAIN;
+ 
+ 		spin_lock_bh(&tp->lock);
+-		err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
+		err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
+ 		spin_unlock_bh(&tp->lock);
+ 
+ 		return err;
+@@ -11802,6 +11863,12 @@ static void __devinit tg3_get_5717_nvram
+ /* Chips other than 5700/5701 use the NVRAM for fetching info. */
+ static void __devinit tg3_nvram_init(struct tg3 *tp)
+ {
+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
+		/* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
+		tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
+		return;
+	}
+
+ 	tw32_f(GRC_EEPROM_ADDR,
+ 	     (EEPROM_ADDR_FSM_RESET |
+ 	      (EEPROM_DEFAULT_CLOCK_PERIOD <<
+@@ -12065,6 +12132,9 @@ static int tg3_nvram_write_block(struct
+ {
+ 	int ret;
+ 
+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
+		return -ENODEV;
+
+ 	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
+ 		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
+ 		       ~GRC_LCLCTRL_GPIO_OUTPUT1);
+@@ -13527,6 +13597,11 @@ static int __devinit tg3_get_invariants(
+ 	      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
+ 		tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
+ 
+	if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
+		tp->write32_tx_mbox = tg3_write_flush_reg32;
+		tp->write32_rx_mbox = tg3_write_flush_reg32;
+	}
+
+ 	/* Get eeprom hw config before calling tg3_set_power_state().
+ 	 * In particular, the TG3_FLG2_IS_NIC flag must be
+ 	 * determined before calling tg3_set_power_state() so that
+@@ -13924,6 +13999,10 @@ static int __devinit tg3_get_device_addr
+ 	}
+ 
+ 	if (!is_valid_ether_addr(&dev->dev_addr[0])) {
+		if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
+			ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
+	}
+	if (!is_valid_ether_addr(&dev->dev_addr[0])) {
+ #ifdef CONFIG_SPARC
+ 		if (!tg3_get_default_macaddr_sparc(tp))
+ 			return 0;
+@@ -14441,6 +14520,7 @@ static char * __devinit tg3_phy_string(s
+ 	case TG3_PHY_ID_BCM5704:	return "5704";
+ 	case TG3_PHY_ID_BCM5705:	return "5705";
+ 	case TG3_PHY_ID_BCM5750:	return "5750";
+	case TG3_PHY_ID_BCM5750_2:	return "5750-2";
+ 	case TG3_PHY_ID_BCM5752:	return "5752";
+ 	case TG3_PHY_ID_BCM5714:	return "5714";
+ 	case TG3_PHY_ID_BCM5780:	return "5780";
+@@ -14644,6 +14724,13 @@ static int __devinit tg3_init_one(struct
+ 		tp->msg_enable = tg3_debug;
+ 	else
+ 		tp->msg_enable = TG3_DEF_MSG_ENABLE;
+	if (pdev_is_ssb_gige_core(pdev)) {
+		tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
+		if (ssb_gige_must_flush_posted_writes(pdev))
+			tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
+		if (ssb_gige_have_roboswitch(pdev))
+			tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
+	}
+ 
+ 	/* The word/byte swap controls here control register access byte
+ 	 * swapping.  DMA data byte swapping is controlled in the GRC_MODE
+--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
+@@ -2060,6 +2060,9 @@
+ #define  NIC_SRAM_RGMII_INBAND_DISABLE	 0x00000004
+ #define  NIC_SRAM_RGMII_EXT_IBND_RX_EN	 0x00000008
+ #define  NIC_SRAM_RGMII_EXT_IBND_TX_EN	 0x00000010
+#define TG3_FLG3_IS_SSB_CORE		0x00000800
+#define TG3_FLG3_FLUSH_POSTED_WRITES	0x00001000
+#define TG3_FLG3_ROBOSWITCH		0x00002000
+ 
+ #define NIC_SRAM_RX_MINI_BUFFER_DESC	0x00001000
+ 
+@@ -2962,6 +2965,7 @@ struct tg3 {
+ #define TG3_PHY_ID_BCM5704		0x60008190
+ #define TG3_PHY_ID_BCM5705		0x600081a0
+ #define TG3_PHY_ID_BCM5750		0x60008180
+#define TG3_PHY_ID_BCM5750_2		0xbc050cd0
+ #define TG3_PHY_ID_BCM5752		0x60008100
+ #define TG3_PHY_ID_BCM5714		0x60008340
+ #define TG3_PHY_ID_BCM5780		0x60008350
+@@ -2998,7 +3002,7 @@ struct tg3 {
+ 	 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
+ 	 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
+ 	 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
+-	 (X) == TG3_PHY_ID_BCM8002)
+	 (X) == TG3_PHY_ID_BCM8002 || (X) == TG3_PHY_ID_BCM5750_2)
+ 
+ 	u32				phy_flags;
+ #define TG3_PHYFLG_IS_LOW_POWER		0x00000001
--- a/target/linux/brcm47xx/patches-2.6.38/812-disable_wgt634u_crap.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/812-disable_wgt634u_crap.patch
@ -0,0 +1,177 @@
+--- a/arch/mips/bcm47xx/Makefile
+++ b/arch/mips/bcm47xx/Makefile
+@@ -3,4 +3,4 @@
+ # under Linux.
+ #
+ 
+-obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
+obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o
+--- a/arch/mips/bcm47xx/wgt634u.c
+++ /dev/null
+@@ -1,166 +0,0 @@
+-/*
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License.  See the file "COPYING" in the main directory of this archive
+- * for more details.
+- *
+- * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
+- */
+-
+-#include <linux/platform_device.h>
+-#include <linux/module.h>
+-#include <linux/leds.h>
+-#include <linux/mtd/physmap.h>
+-#include <linux/ssb/ssb.h>
+-#include <linux/interrupt.h>
+-#include <linux/reboot.h>
+-#include <linux/gpio.h>
+-#include <asm/mach-bcm47xx/bcm47xx.h>
+-
+-/* GPIO definitions for the WGT634U */
+-#define WGT634U_GPIO_LED	3
+-#define WGT634U_GPIO_RESET	2
+-#define WGT634U_GPIO_TP1	7
+-#define WGT634U_GPIO_TP2	6
+-#define WGT634U_GPIO_TP3	5
+-#define WGT634U_GPIO_TP4	4
+-#define WGT634U_GPIO_TP5	1
+-
+-static struct gpio_led wgt634u_leds[] = {
+-	{
+-		.name = "power",
+-		.gpio = WGT634U_GPIO_LED,
+-		.active_low = 1,
+-		.default_trigger = "heartbeat",
+-	},
+-};
+-
+-static struct gpio_led_platform_data wgt634u_led_data = {
+-	.num_leds =     ARRAY_SIZE(wgt634u_leds),
+-	.leds =         wgt634u_leds,
+-};
+-
+-static struct platform_device wgt634u_gpio_leds = {
+-	.name =         "leds-gpio",
+-	.id =           -1,
+-	.dev = {
+-		.platform_data = &wgt634u_led_data,
+-	}
+-};
+-
+-
+-/* 8MiB flash. The struct mtd_partition matches original Netgear WGT634U
+-   firmware. */
+-static struct mtd_partition wgt634u_partitions[] = {
+-	{
+-		.name       = "cfe",
+-		.offset     = 0,
+-		.size       = 0x60000,		/* 384k */
+-		.mask_flags = MTD_WRITEABLE 	/* force read-only */
+-	},
+-	{
+-		.name   = "config",
+-		.offset = 0x60000,
+-		.size   = 0x20000		/* 128k */
+-	},
+-	{
+-		.name   = "linux",
+-		.offset = 0x80000,
+-		.size   = 0x140000 		/* 1280k */
+-	},
+-	{
+-		.name   = "jffs",
+-		.offset = 0x1c0000,
+-		.size   = 0x620000 		/* 6272k */
+-	},
+-	{
+-		.name   = "nvram",
+-		.offset = 0x7e0000,
+-		.size   = 0x20000		/* 128k */
+-	},
+-};
+-
+-static struct physmap_flash_data wgt634u_flash_data = {
+-	.parts    = wgt634u_partitions,
+-	.nr_parts = ARRAY_SIZE(wgt634u_partitions)
+-};
+-
+-static struct resource wgt634u_flash_resource = {
+-	.flags = IORESOURCE_MEM,
+-};
+-
+-static struct platform_device wgt634u_flash = {
+-	.name          = "physmap-flash",
+-	.id            = 0,
+-	.dev           = { .platform_data = &wgt634u_flash_data, },
+-	.resource      = &wgt634u_flash_resource,
+-	.num_resources = 1,
+-};
+-
+-/* Platform devices */
+-static struct platform_device *wgt634u_devices[] __initdata = {
+-	&wgt634u_flash,
+-	&wgt634u_gpio_leds,
+-};
+-
+-static irqreturn_t gpio_interrupt(int irq, void *ignored)
+-{
+-	int state;
+-
+-	/* Interrupts are shared, check if the current one is
+-	   a GPIO interrupt. */
+-	if (!ssb_chipco_irq_status(&ssb_bcm47xx.chipco,
+-				   SSB_CHIPCO_IRQ_GPIO))
+-		return IRQ_NONE;
+-
+-	state = gpio_get_value(WGT634U_GPIO_RESET);
+-
+-	/* Interrupt are level triggered, revert the interrupt polarity
+-	   to clear the interrupt. */
+-	gpio_polarity(WGT634U_GPIO_RESET, state);
+-
+-	if (!state) {
+-		printk(KERN_INFO "Reset button pressed");
+-		ctrl_alt_del();
+-	}
+-
+-	return IRQ_HANDLED;
+-}
+-
+-static int __init wgt634u_init(void)
+-{
+-	/* There is no easy way to detect that we are running on a WGT634U
+-	 * machine. Use the MAC address as an heuristic. Netgear Inc. has
+-	 * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx.
+-	 */
+-
+-	u8 *et0mac = ssb_bcm47xx.sprom.et0mac;
+-
+-	if (et0mac[0] == 0x00 &&
+-	    ((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
+-	     (et0mac[1] == 0x0f && et0mac[2] == 0xb5))) {
+-		struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
+-
+-		printk(KERN_INFO "WGT634U machine detected.\n");
+-
+-		if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET),
+-				 gpio_interrupt, IRQF_SHARED,
+-				 "WGT634U GPIO", &ssb_bcm47xx.chipco)) {
+-			gpio_direction_input(WGT634U_GPIO_RESET);
+-			gpio_intmask(WGT634U_GPIO_RESET, 1);
+-			ssb_chipco_irq_mask(&ssb_bcm47xx.chipco,
+-					    SSB_CHIPCO_IRQ_GPIO,
+-					    SSB_CHIPCO_IRQ_GPIO);
+-		}
+-
+-		wgt634u_flash_data.width = mcore->flash_buswidth;
+-		wgt634u_flash_resource.start = mcore->flash_window;
+-		wgt634u_flash_resource.end = mcore->flash_window
+-					   + mcore->flash_window_size
+-					   - 1;
+-		return platform_add_devices(wgt634u_devices,
+-					    ARRAY_SIZE(wgt634u_devices));
+-	} else
+-		return -ENODEV;
+-}
+-
+-module_init(wgt634u_init);
--- a/target/linux/brcm47xx/patches-2.6.38/820-wgt634u-nvram-fix.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/820-wgt634u-nvram-fix.patch
@ -0,0 +1,305 @@
+The Netgear wgt634u uses a different format for storing the 
+configuration. This patch is needed to read out the correct 
+configuration. The cfe_env.c file uses a different method way to read 
+out the configuration than the in kernel cfe config reader.
+
+--- a/arch/mips/bcm47xx/Makefile
+++ b/arch/mips/bcm47xx/Makefile
+@@ -3,4 +3,4 @@
+ # under Linux.
+ #
+ 
+-obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o
+obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o cfe_env.o
+--- /dev/null
+++ b/arch/mips/bcm47xx/cfe_env.c
+@@ -0,0 +1,229 @@
+/*
+ * CFE environment variable access
+ *
+ * Copyright 2001-2003, Broadcom Corporation
+ * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
+ * 
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+
+#define NVRAM_SIZE       (0x1ff0)
+static char _nvdata[NVRAM_SIZE];
+static char _valuestr[256];
+
+/*
+ * TLV types.  These codes are used in the "type-length-value"
+ * encoding of the items stored in the NVRAM device (flash or EEPROM)
+ *
+ * The layout of the flash/nvram is as follows:
+ *
+ * <type> <length> <data ...> <type> <length> <data ...> <type_end>
+ *
+ * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
+ * The "length" field marks the length of the data section, not
+ * including the type and length fields.
+ *
+ * Environment variables are stored as follows:
+ *
+ * <type_env> <length> <flags> <name> = <value>
+ *
+ * If bit 0 (low bit) is set, the length is an 8-bit value.
+ * If bit 0 (low bit) is clear, the length is a 16-bit value
+ * 
+ * Bit 7 set indicates "user" TLVs.  In this case, bit 0 still
+ * indicates the size of the length field.  
+ *
+ * Flags are from the constants below:
+ *
+ */
+#define ENV_LENGTH_16BITS	0x00	/* for low bit */
+#define ENV_LENGTH_8BITS	0x01
+
+#define ENV_TYPE_USER		0x80
+
+#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
+#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
+
+/*
+ * The actual TLV types we support
+ */
+
+#define ENV_TLV_TYPE_END	0x00	
+#define ENV_TLV_TYPE_ENV	ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
+
+/*
+ * Environment variable flags 
+ */
+
+#define ENV_FLG_NORMAL		0x00	/* normal read/write */
+#define ENV_FLG_BUILTIN		0x01	/* builtin - not stored in flash */
+#define ENV_FLG_READONLY	0x02	/* read-only - cannot be changed */
+
+#define ENV_FLG_MASK		0xFF	/* mask of attributes we keep */
+#define ENV_FLG_ADMIN		0x100	/* lets us internally override permissions */
+
+
+/*  *********************************************************************
+    *  _nvram_read(buffer,offset,length)
+    *  
+    *  Read data from the NVRAM device
+    *  
+    *  Input parameters: 
+    *  	   buffer - destination buffer
+    *  	   offset - offset of data to read
+    *  	   length - number of bytes to read
+    *  	   
+    *  Return value:
+    *  	   number of bytes read, or <0 if error occured
+    ********************************************************************* */
+static int
+_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
+{
+    int i;
+    if (offset > NVRAM_SIZE)
+	return -1; 
+
+    for ( i = 0; i < length; i++) {
+	buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
+    }
+    return length;
+}
+
+
+static char*
+_strnchr(const char *dest,int c,size_t cnt)
+{
+	while (*dest && (cnt > 0)) {
+	if (*dest == c) return (char *) dest;
+	dest++;
+	cnt--;
+	}
+	return NULL;
+}
+
+
+
+/*
+ * Core support API: Externally visible.
+ */
+
+/*
+ * Get the value of an NVRAM variable
+ * @param	name	name of variable to get
+ * @return	value of variable or NULL if undefined
+ */
+
+char* 
+cfe_env_get(unsigned char *nv_buf, char* name)
+{
+    int size;
+    unsigned char *buffer;
+    unsigned char *ptr;
+    unsigned char *envval;
+    unsigned int reclen;
+    unsigned int rectype;
+    int offset;
+    int flg;
+    
+	if (!strcmp(name, "nvram_type"))
+		return "cfe";
+	
+    size = NVRAM_SIZE;
+    buffer = &_nvdata[0];
+
+    ptr = buffer;
+    offset = 0;
+
+    /* Read the record type and length */
+    if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
+	goto error;
+    }
+    
+    while ((*ptr != ENV_TLV_TYPE_END)  && (size > 1)) {
+
+	/* Adjust pointer for TLV type */
+	rectype = *(ptr);
+	offset++;
+	size--;
+
+	/* 
+	 * Read the length.  It can be either 1 or 2 bytes
+	 * depending on the code 
+	 */
+	if (rectype & ENV_LENGTH_8BITS) {
+	    /* Read the record type and length - 8 bits */
+	    if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
+		goto error;
+	    }
+	    reclen = *(ptr);
+	    size--;
+	    offset++;
+	}
+	else {
+	    /* Read the record type and length - 16 bits, MSB first */
+	    if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
+		goto error;
+	    }
+	    reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
+	    size -= 2;
+	    offset += 2;
+	}
+
+	if (reclen > size)
+	    break;	/* should not happen, bad NVRAM */
+
+	switch (rectype) {
+	    case ENV_TLV_TYPE_ENV:
+		/* Read the TLV data */
+		if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
+		    goto error;
+		flg = *ptr++;
+		envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
+		if (envval) {
+		    *envval++ = '\0';
+		    memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
+		    _valuestr[(reclen-1)-(envval-ptr)] = '\0';
+#if 0			
+		    printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
+#endif
+		    if(!strcmp(ptr, name)){
+			return _valuestr;
+		    }
+		    if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
+			return _valuestr;
+		}
+		break;
+		
+	    default: 
+		/* Unknown TLV type, skip it. */
+		break;
+	    }
+
+	/*
+	 * Advance to next TLV 
+	 */
+		
+	size -= (int)reclen;
+	offset += reclen;
+
+	/* Read the next record type */
+	ptr = buffer;
+	if (_nvram_read(nv_buf, ptr,offset,1) != 1)
+	    goto error;
+	}
+
+error:
+    return NULL;
+
+}
+
+--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
+@@ -21,6 +21,8 @@
+ #include <asm/mach-bcm47xx/bcm47xx.h>
+ 
+ static char nvram_buf[NVRAM_SPACE];
+static int cfe_env;
+extern char *cfe_env_get(char *nv_buf, const char *name);
+ 
+ /* Probe for NVRAM header */
+ static void __init early_nvram_init(void)
+@@ -33,6 +35,25 @@ static void __init early_nvram_init(void
+ 
+ 	base = mcore->flash_window;
+ 	lim = mcore->flash_window_size;
+	cfe_env = 0;
+
+	/* XXX: hack for supporting the CFE environment stuff on WGT634U */
+	if (lim >= 8 * 1024 * 1024) {
+		src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
+		dst = (u32 *) nvram_buf;
+
+		if ((*src & 0xff00ff) == 0x000001) {
+			printk("early_nvram_init: WGT634U NVRAM found.\n");
+
+			for (i = 0; i < 0x1ff0; i++) {
+				if (*src == 0xFFFFFFFF)
+					break;
+				*dst++ = *src++;
+			}
+			cfe_env = 1;
+			return;
+		}
+	}
+ 
+ 	off = FLASH_MIN;
+ 	while (off <= lim) {
+@@ -74,6 +95,12 @@ int nvram_getenv(char *name, char *val,
+ 	if (!nvram_buf[0])
+ 		early_nvram_init();
+ 
+	if (cfe_env) {
+		value = cfe_env_get(nvram_buf, name);
+		snprintf(val, val_len, "%s", value);
+		return 0;
+	}
+
+ 	/* Look for name=value and return value */
+ 	var = &nvram_buf[sizeof(struct nvram_header)];
+ 	end = nvram_buf + sizeof(nvram_buf) - 2;
+@@ -103,6 +130,9 @@ char *nvram_get(const char *name)
+ 	if (!nvram_buf[0])
+ 		early_nvram_init();
+ 
+	if (cfe_env)
+		return cfe_env_get(nvram_buf, name);
+
+ 	/* Look for name=value and return value */
+ 	var = &nvram_buf[sizeof(struct nvram_header)];
+ 	end = nvram_buf + sizeof(nvram_buf) - 2;
--- a/target/linux/brcm47xx/patches-2.6.38/830-tg3_add_pci_ids.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/830-tg3_add_pci_ids.patch
@ -0,0 +1,47 @@
+commit 812bcf8f47b45a206948008144233bc47d5747ac
+Author: Hauke Mehrtens <hauke@hauke-m.de>
+Date:   Thu Dec 16 20:01:17 2010 +0100
+
+    Revert "tg3: Remove 5720, 5750, and 5750M"
+    
+    This reverts commit 67b284d476bcb3d100e946da23d6cf9acfd0465c.
+
+--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
+@@ -217,9 +217,12 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_t
+ 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
+ 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
+ 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
+	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
+ 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
+ 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
+	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
+ 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
+	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
+ 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
+ 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
+ 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
+--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
+@@ -2073,6 +2073,7 @@
+ #define PCI_DEVICE_ID_NX2_57711E	0x1650
+ #define PCI_DEVICE_ID_TIGON3_5705	0x1653
+ #define PCI_DEVICE_ID_TIGON3_5705_2	0x1654
+#define PCI_DEVICE_ID_TIGON3_5720	0x1658
+ #define PCI_DEVICE_ID_TIGON3_5721	0x1659
+ #define PCI_DEVICE_ID_TIGON3_5722	0x165a
+ #define PCI_DEVICE_ID_TIGON3_5723	0x165b
+@@ -2086,11 +2087,13 @@
+ #define PCI_DEVICE_ID_TIGON3_5754M	0x1672
+ #define PCI_DEVICE_ID_TIGON3_5755M	0x1673
+ #define PCI_DEVICE_ID_TIGON3_5756	0x1674
+#define PCI_DEVICE_ID_TIGON3_5750	0x1676
+ #define PCI_DEVICE_ID_TIGON3_5751	0x1677
+ #define PCI_DEVICE_ID_TIGON3_5715	0x1678
+ #define PCI_DEVICE_ID_TIGON3_5715S	0x1679
+ #define PCI_DEVICE_ID_TIGON3_5754	0x167a
+ #define PCI_DEVICE_ID_TIGON3_5755	0x167b
+#define PCI_DEVICE_ID_TIGON3_5750M	0x167c
+ #define PCI_DEVICE_ID_TIGON3_5751M	0x167d
+ #define PCI_DEVICE_ID_TIGON3_5751F	0x167e
+ #define PCI_DEVICE_ID_TIGON3_5787F	0x167f
--- a/target/linux/brcm47xx/patches-2.6.38/900-bcm47xx_wdt-noprescale.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/900-bcm47xx_wdt-noprescale.patch
@ -0,0 +1,89 @@
+--- a/drivers/watchdog/bcm47xx_wdt.c
+++ b/drivers/watchdog/bcm47xx_wdt.c
+@@ -31,6 +31,7 @@
+ 
+ #define WDT_DEFAULT_TIME	30	/* seconds */
+ #define WDT_MAX_TIME		255	/* seconds */
+#define WDT_SHIFT		15	/* 32.768 KHz on cores with slow WDT clock */
+ 
+ static int wdt_time = WDT_DEFAULT_TIME;
+ static int nowayout = WATCHDOG_NOWAYOUT;
+@@ -50,11 +51,11 @@ static unsigned long bcm47xx_wdt_busy;
+ static char expect_release;
+ static struct timer_list wdt_timer;
+ static atomic_t ticks;
+static int needs_sw_scale;
+ 
+-static inline void bcm47xx_wdt_hw_start(void)
+static inline void bcm47xx_wdt_hw_start(u32 ticks)
+ {
+-	/* this is 2,5s on 100Mhz clock  and 2s on 133 Mhz */
+-	ssb_watchdog_timer_set(&ssb_bcm47xx, 0xfffffff);
+ 	ssb_watchdog_timer_set(&ssb_bcm47xx, ticks);
+ }
+ 
+ static inline int bcm47xx_wdt_hw_stop(void)
+@@ -65,33 +66,34 @@ static inline int bcm47xx_wdt_hw_stop(vo
+ static void bcm47xx_timer_tick(unsigned long unused)
+ {
+ 	if (!atomic_dec_and_test(&ticks)) {
+-		bcm47xx_wdt_hw_start();
+		/* This is 2,5s on 100Mhz clock and 2s on 133 Mhz */
+		bcm47xx_wdt_hw_start(0xfffffff);
+ 		mod_timer(&wdt_timer, jiffies + HZ);
+ 	} else {
+-		printk(KERN_CRIT DRV_NAME "Watchdog will fire soon!!!\n");
+		printk(KERN_CRIT DRV_NAME ": Watchdog will fire soon!!!\n");
+ 	}
+ }
+ 
+-static inline void bcm47xx_wdt_pet(void)
+static void bcm47xx_wdt_pet(void)
+ {
+-	atomic_set(&ticks, wdt_time);
+	if(needs_sw_scale)
+		atomic_set(&ticks, wdt_time);
+	else
+		bcm47xx_wdt_hw_start(wdt_time << WDT_SHIFT);
+ }
+ 
+ static void bcm47xx_wdt_start(void)
+ {
+ 	bcm47xx_wdt_pet();
+-	bcm47xx_timer_tick(0);
+-}
+-
+-static void bcm47xx_wdt_pause(void)
+-{
+-	del_timer_sync(&wdt_timer);
+-	bcm47xx_wdt_hw_stop();
+	if(needs_sw_scale)
+		bcm47xx_timer_tick(0);
+ }
+ 
+ static void bcm47xx_wdt_stop(void)
+ {
+-	bcm47xx_wdt_pause();
+	if(needs_sw_scale)
+		del_timer_sync(&wdt_timer);
+	bcm47xx_wdt_hw_stop();
+ }
+ 
+ static int bcm47xx_wdt_settimeout(int new_time)
+@@ -243,7 +245,15 @@ static int __init bcm47xx_wdt_init(void)
+ 	if (bcm47xx_wdt_hw_stop() < 0)
+ 		return -ENODEV;
+ 
+-	setup_timer(&wdt_timer, bcm47xx_timer_tick, 0L);
+	/* FIXME Other cores */
+	if(ssb_bcm47xx.chip_id == 0x5354) {
+		/* Slow WDT clock, no pre-scaling */
+		needs_sw_scale = 0;
+	} else {
+		/* Fast WDT clock, needs software pre-scaling */
+		needs_sw_scale = 1;
+		setup_timer(&wdt_timer, bcm47xx_timer_tick, 0L);
+	}
+ 
+ 	if (bcm47xx_wdt_settimeout(wdt_time)) {
+ 		bcm47xx_wdt_settimeout(WDT_DEFAULT_TIME);
--- a/target/linux/brcm47xx/patches-2.6.38/920-cache-wround.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/920-cache-wround.patch
@ -0,0 +1,138 @@
+--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
+@@ -20,10 +20,28 @@
+ #ifdef CONFIG_BCM47XX
+ #include <asm/paccess.h>
+ #include <linux/ssb/ssb.h>
+-#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
+#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
+
+static inline unsigned long bcm4710_dummy_rreg(void)
+{
+      return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
+}
+
+#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
+
+static inline unsigned long bcm4710_fill_tlb(void *addr)
+{
+      return *(unsigned long *)addr;
+}
+
+#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
+
+static inline void bcm4710_protected_fill_tlb(void *addr)
+{
+      unsigned long x;
+      get_dbe(x, (unsigned long *)addr);;
+}
+ 
+-#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
+-#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
+ #else
+ #define BCM4710_DUMMY_RREG()
+ 
+--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
+@@ -834,6 +834,9 @@ build_get_pgde32(u32 **p, unsigned int t
+ #endif
+ 	uasm_i_addu(p, ptr, tmp, ptr);
+ #else
+#ifdef CONFIG_BCM47XX
+	uasm_i_nop(p);
+#endif
+ 	UASM_i_LA_mostly(p, ptr, pgdc);
+ #endif
+ 	uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
+@@ -1187,12 +1190,12 @@ static void __cpuinit build_r4000_tlb_re
+ 			/* No need for uasm_i_nop */
+ 		}
+ 
+-#ifdef CONFIG_BCM47XX
+-		uasm_i_nop(&p);
+-#endif
+ #ifdef CONFIG_64BIT
+ 		build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
+ #else
+# ifdef CONFIG_BCM47XX
+		uasm_i_nop(&p);
+# endif
+ 		build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
+ #endif
+ 
+@@ -1204,6 +1207,9 @@ static void __cpuinit build_r4000_tlb_re
+ 		build_update_entries(&p, K0, K1);
+ 		build_tlb_write_entry(&p, &l, &r, tlb_random);
+ 		uasm_l_leave(&l, p);
+#ifdef CONFIG_BCM47XX
+		uasm_i_nop(&p);
+#endif
+ 		uasm_i_eret(&p); /* return from trap */
+ 	}
+ #ifdef CONFIG_HUGETLB_PAGE
+@@ -1709,12 +1715,12 @@ build_r4000_tlbchange_handler_head(u32 *
+ 				   struct uasm_reloc **r, unsigned int pte,
+ 				   unsigned int ptr)
+ {
+-#ifdef CONFIG_BCM47XX
+-	uasm_i_nop(p);
+-#endif
+ #ifdef CONFIG_64BIT
+ 	build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
+ #else
+# ifdef CONFIG_BCM47XX
+	uasm_i_nop(p);
+# endif
+ 	build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
+ #endif
+ 
+@@ -1751,6 +1757,9 @@ build_r4000_tlbchange_handler_tail(u32 *
+ 	build_update_entries(p, tmp, ptr);
+ 	build_tlb_write_entry(p, l, r, tlb_indexed);
+ 	uasm_l_leave(l, *p);
+#ifdef CONFIG_BCM47XX
+	uasm_i_nop(p);
+#endif
+ 	uasm_i_eret(p); /* return from trap */
+ 
+ #ifdef CONFIG_64BIT
+--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
+@@ -22,6 +22,19 @@
+ #include <asm/page.h>
+ #include <asm/thread_info.h>
+ 
+#ifdef CONFIG_BCM47XX
+# ifdef eret
+#  undef eret
+# endif
+# define eret 					\
+	.set push;				\
+	.set noreorder;				\
+	 nop; 					\
+	 nop;					\
+	 eret;					\
+	.set pop;
+#endif
+
+ #define PANIC_PIC(msg)					\
+ 		.set push;				\
+ 		.set	reorder;			\
+@@ -54,7 +67,6 @@ NESTED(except_vec3_generic, 0, sp)
+ 	.set	noat
+ #ifdef CONFIG_BCM47XX
+ 	nop
+-	nop
+ #endif
+ #if R5432_CP0_INTERRUPT_WAR
+ 	mfc0	k0, CP0_INDEX
+@@ -79,6 +91,9 @@ NESTED(except_vec3_r4000, 0, sp)
+ 	.set	push
+ 	.set	mips3
+ 	.set	noat
+#ifdef CONFIG_BCM47XX
+	nop
+#endif
+ 	mfc0	k1, CP0_CAUSE
+ 	li	k0, 31<<2
+ 	andi	k1, k1, 0x7c
--- a/target/linux/brcm47xx/patches-2.6.38/940-bcm47xx-yenta.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/940-bcm47xx-yenta.patch
@ -0,0 +1,46 @@
+--- a/drivers/pcmcia/yenta_socket.c
+++ b/drivers/pcmcia/yenta_socket.c
+@@ -920,6 +920,8 @@ static unsigned int yenta_probe_irq(stru
+ 	 * Probe for usable interrupts using the force
+ 	 * register to generate bogus card status events.
+ 	 */
+#ifndef CONFIG_BCM47XX
+	/* WRT54G3G does not like this */
+ 	cb_writel(socket, CB_SOCKET_EVENT, -1);
+ 	cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
+ 	reg = exca_readb(socket, I365_CSCINT);
+@@ -935,6 +937,7 @@ static unsigned int yenta_probe_irq(stru
+ 	}
+ 	cb_writel(socket, CB_SOCKET_MASK, 0);
+ 	exca_writeb(socket, I365_CSCINT, reg);
+#endif
+ 
+ 	mask = probe_irq_mask(val) & 0xffff;
+ 
+@@ -1019,6 +1022,10 @@ static void yenta_get_socket_capabilitie
+ 	else
+ 		socket->socket.irq_mask = 0;
+ 
+	/* irq mask probing is broken for the WRT54G3G */
+	if (socket->socket.irq_mask == 0)
+		socket->socket.irq_mask = 0x6f8;
+
+ 	dev_printk(KERN_INFO, &socket->dev->dev,
+ 		   "ISA IRQ mask 0x%04x, PCI irq %d\n",
+ 		   socket->socket.irq_mask, socket->cb_irq);
+@@ -1257,6 +1264,15 @@ static int __devinit yenta_probe(struct
+ 	dev_printk(KERN_INFO, &dev->dev,
+ 		   "Socket status: %08x\n", cb_readl(socket, CB_SOCKET_STATE));
+ 
+	/* Generate an interrupt on card insert/remove */
+	config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK);
+
+	/* Set up Multifunction Routing Status Register */
+	config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */);
+
+	/* Switch interrupts to parallelized */
+	config_writeb(socket, 0x92, 0x64);
+
+ 	yenta_fixup_parent_bridge(dev->subordinate);
+ 
+ 	/* Register it with the pcmcia layer.. */
--- a/target/linux/brcm47xx/patches-2.6.38/951-brcm4716-defines.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/951-brcm4716-defines.patch
@ -0,0 +1,104 @@
+--- a/drivers/ssb/scan.c
+++ b/drivers/ssb/scan.c
+@@ -90,6 +90,14 @@ const char *ssb_core_name(u16 coreid)
+ 		return "ARM 1176";
+ 	case SSB_DEV_ARM_7TDMI:
+ 		return "ARM 7TDMI";
+	case SSB_DEV_ETHERNET_GBIT2:
+		return "Gigabit MAC";
+	case SSB_DEV_MIPS_74K:
+		return "MIPS 74k";
+	case SSB_DEV_DDR_CTRLR:
+		return "DDR1/2 memory controller";
+	case SSB_DEV_I2S:
+		return "I2S";
+ 	}
+ 	return "UNKNOWN";
+ }
+@@ -148,6 +156,7 @@ static u8 chipid_to_nrcores(u16 chipid)
+ 	case 0x4710:
+ 	case 0x4610:
+ 	case 0x4704:
+	case 0x4716:
+ 		return 9;
+ 	default:
+ 		ssb_printk(KERN_ERR PFX
+--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
+@@ -155,9 +155,16 @@ struct ssb_bus_ops {
+ #define SSB_DEV_MINI_MACPHY	0x823
+ #define SSB_DEV_ARM_1176	0x824
+ #define SSB_DEV_ARM_7TDMI	0x825
+#define SSB_DEV_ETHERNET_GBIT2	0x82d
+#define SSB_DEV_MIPS_74K	0x82c
+#define SSB_DEV_DDR_CTRLR	0x82e
+#define SSB_DEV_I2S			0x834
+#define SSB_DEV_DEFAULT		0xfff
+ 
+ /* Vendor-ID values */
+ #define SSB_VENDOR_BROADCOM	0x4243
+#define SSB_VENDOR_BROADCOM2 0x04BF
+#define SSB_VENDOR_ARM		0x43b
+ 
+ /* Some kernel subsystems poke with dev->drvdata, so we must use the
+  * following ugly workaround to get from struct device to struct ssb_device */
+--- a/include/linux/ssb/ssb_regs.h
+++ b/include/linux/ssb/ssb_regs.h
+@@ -11,6 +11,7 @@
+ #define	SSB_SDRAM_SWAPPED	0x10000000U	/* Byteswapped Physical SDRAM */
+ #define SSB_ENUM_BASE    	0x18000000U	/* Enumeration space base */
+ #define	SSB_ENUM_LIMIT		0x18010000U	/* Enumeration space limit */
+#define SSB_AI_BASE		0x18100000		/* base for AI registers */
+ 
+ #define	SSB_FLASH2		0x1c000000U	/* Flash Region 2 (region 1 shadowed here) */
+ #define	SSB_FLASH2_SZ		0x02000000U	/* Size of Flash Region 2 */
+@@ -26,6 +27,7 @@
+ #define	SSB_EUART		(SSB_EXTIF_BASE + 0x00800000)
+ #define	SSB_LED			(SSB_EXTIF_BASE + 0x00900000)
+ 
+#define SSB_EROM_ASD_SZ_BASE 0x00001000
+ 
+ /* Enumeration space constants */
+ #define SSB_CORE_SIZE		0x1000	/* Size of a core MMIO area */
+@@ -499,5 +501,41 @@ enum {
+ #define SSB_ADM_BASE2			0xFFFF0000	/* Type2 base address for the core */
+ #define SSB_ADM_BASE2_SHIFT		16
+ 
+/***** EROM defines for AI type busses *****/
+#define SSB_EROM_VALID			1
+#define SSB_EROM_END			0xe
+#define SSB_EROM_TAG			0xe
+/* Adress Space Descriptor */
+#define SSB_EROM_ASD			0x4
+#define SSB_EROM_ASD_SP_MASK	0x00000f00
+#define SSB_EROM_ASD_SP_SHIFT	8
+#define SSB_EROM_ASD_ST_MASK	0x000000c0
+#define SSB_EROM_ASD_ST_SLAVE	0x00000000
+#define SSB_EROM_ASD_ST_BRIDGE	0x00000040
+#define SSB_EROM_ASD_ST_MWRAP	0x000000c0
+#define SSB_EROM_ASD_ST_SWRAP	0x00000080
+#define SSB_EROM_ASD_ADDR_MASK	0xfffff000
+#define SSB_EROM_ASD_AG32		0x00000008
+#define SSB_EROM_ASD_SZ_MASK	0x00000030
+#define SSB_EROM_ASD_SZ_SZD		0x00000030
+#define SSB_EROM_ASD_SZ_SHIFT	4
+#define SSB_EROM_CI				0
+#define SSB_EROM_CIA_CID_MASK	0x000fff00
+#define SSB_EROM_CIA_CID_SHIFT	8
+#define SSB_EROM_CIA_MFG_MASK	0xfff00000
+#define SSB_EROM_CIA_MFG_SHIFT	20
+#define SSB_EROM_CIB_REV_MASK	0xff000000
+#define SSB_EROM_CIB_REV_SHIFT	24
+#define SSB_EROM_CIB_NMW_MASK	0x0007c000
+#define SSB_EROM_CIB_NSW_MASK	0x00f80000
+#define SSB_EROM_CIB_NSP_MASK	0x00003e00
+
+/***** Registers of AI config space *****/
+#define SSB_AI_RESETCTRL		0x800 /* maybe 0x804 for big endian */
+#define  SSB_AI_RESETCTRL_RESET	1
+#define SSB_AI_IOCTRL			0x408 /* maybe 0x40c for big endian */
+#define SSB_CF_FGC				0x0002
+#define SSB_CF_CLOCK_EN			0x001
+#define SSB_AI_oobselouta30		0x100
+ 
+ #endif /* LINUX_SSB_REGS_H_ */
--- a/target/linux/brcm47xx/patches-2.6.38/976-ssb_increase_pci_delay.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/976-ssb_increase_pci_delay.patch
@ -0,0 +1,11 @@
+--- a/drivers/ssb/driver_pcicore.c
+++ b/drivers/ssb/driver_pcicore.c
+@@ -370,7 +370,7 @@ static void ssb_pcicore_init_hostmode(st
+ 	set_io_port_base(ssb_pcicore_controller.io_map_base);
+ 	/* Give some time to the PCI controller to configure itself with the new
+ 	 * values. Not waiting at this point causes crashes of the machine. */
+-	mdelay(10);
+	mdelay(300);
+ 	register_pci_controller(&ssb_pcicore_controller);
+ }
+ 
--- a/target/linux/brcm47xx/patches-2.6.38/977-ssb_export_fallback_sprom.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/977-ssb_export_fallback_sprom.patch
@ -0,0 +1,20 @@
+--- a/drivers/ssb/sprom.c
+++ b/drivers/ssb/sprom.c
+@@ -176,6 +176,7 @@ const struct ssb_sprom *ssb_get_fallback
+ {
+ 	return fallback_sprom;
+ }
+EXPORT_SYMBOL(ssb_get_fallback_sprom);
+ 
+ /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
+ bool ssb_is_sprom_available(struct ssb_bus *bus)
+--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
+@@ -412,6 +412,7 @@ extern bool ssb_is_sprom_available(struc
+ /* Set a fallback SPROM.
+  * See kdoc at the function definition for complete documentation. */
+ extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
+extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
+ 
+ /* Suspend a SSB bus.
+  * Call this from the parent bus suspend routine. */
--- a/target/linux/brcm47xx/patches-2.6.38/999-wl_exports.patch
+++ b/target/linux/brcm47xx/patches-2.6.38/999-wl_exports.patch
@ -0,0 +1,22 @@
+--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
+@@ -20,7 +20,8 @@
+ #include <asm/mach-bcm47xx/nvram.h>
+ #include <asm/mach-bcm47xx/bcm47xx.h>
+ 
+-static char nvram_buf[NVRAM_SPACE];
+char nvram_buf[NVRAM_SPACE];
+EXPORT_SYMBOL(nvram_buf);
+ static int cfe_env;
+ extern char *cfe_env_get(char *nv_buf, const char *name);
+ 
+--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
+@@ -52,6 +52,7 @@ void (*_dma_cache_wback)(unsigned long s
+ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+ 
+ EXPORT_SYMBOL(_dma_cache_wback_inv);
+EXPORT_SYMBOL(_dma_cache_inv);
+ 
+ #endif /* CONFIG_DMA_NONCOHERENT */
+