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Code

some smaller cleanups and fix for rebooting ar7

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@1570 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd 2005-07-26 13:37:30 +00:00
parent 23c216a0e2
commit 83e7893f56
3 changed files with 335 additions and 419 deletions
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4
openwrt/target/linux/linux-2.4/config/ar7
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@ -25,8 +25,8 @@ CONFIG_AR7=y
# CONFIG_AR7DB is not set
# CONFIG_AR7RD is not set
CONFIG_AR7WRD=y
CONFIG_AR7_CPU_FREQUENCY=150
CONFIG_AR7_SYS_FREQUENCY=125
CONFIG_AR7_CPU=150
CONFIG_AR7_SYS=125
CONFIG_AR7_MEMORY=0x14000000
# CONFIG_MIPS_BOSPORUS is not set
# CONFIG_MIPS_FICMMP is not set

742
openwrt/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch
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File diff suppressed because it is too large Load Diff

8
openwrt/target/linux/linux-2.4/patches/ar7/003-net_driver_cpmac.patch
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@ -2902,7 +2902,7 @@ diff -urN linux.old/drivers/net/avalanche_cpmac/cpmac.c linux.dev/drivers/net/av
+ /* OS Needs to supply CORRECT frequency */
+ if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
+ {
+ *(unsigned int *)value = CONFIG_AR7_SYS_FREQUENCY * 1000 * 1000;
+ *(unsigned int *)value = CONFIG_AR7_SYS * 1000 * 1000;
+ ret_val = 0;
+ }
+ }
@ -2921,7 +2921,7 @@ diff -urN linux.old/drivers/net/avalanche_cpmac/cpmac.c linux.dev/drivers/net/av
+ /* For Sangam MdioBusFreq is off the PBUS */
+ if(cpmac_ci_strcmp(action, "Get") == 0 && value != NULL)
+ {
+ *(unsigned int *)value = CONFIG_AR7_SYS_FREQUENCY * 1000 * 1000;
+ *(unsigned int *)value = CONFIG_AR7_SYS * 1000 * 1000;
+ ret_val = 0;
+ }
+ }
@ -3143,7 +3143,7 @@ diff -urN linux.old/drivers/net/avalanche_cpmac/cpmac.c linux.dev/drivers/net/av
+ int instance_count = CONFIG_MIPS_CPMAC_PORTS;
+
+ //cpmac_cpu_freq = avalanche_clkc_get_freq(CLKC_MIPS);
+ cpmac_cpu_freq = CONFIG_AR7_CPU_FREQUENCY * 1000 * 1000;
+ cpmac_cpu_freq = CONFIG_AR7_CPU * 1000 * 1000;
+
+ build_psp_config();
+
@ -11171,7 +11171,7 @@ diff -urN linux.old/drivers/net/avalanche_cpmac/psp_config_build.c linux.dev/dri
+ unsigned int j= 0, detected_phy_map = 0, auto_select = SELECT_INT_PHY_MAC;
+
+ *reset_cntl |= (1 << AVALANCHE_MDIO_RESET_BIT) | (1 << AVALANCHE_LOW_CPMAC_RESET_BIT) | (1 << AVALANCHE_HIGH_CPMAC_RESET_BIT) | (1 << AVALANCHE_LOW_EPHY_RESET_BIT);
+ *mdio_cntl = (1 << 30) | ((CONFIG_AR7_SYS_FREQUENCY * 1000)/2200);
+ *mdio_cntl = (1 << 30) | ((CONFIG_AR7_SYS * 1000)/2200);
+
+ for(j=0;j < 300000; j++)
+ {