mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 03:13:20 +02:00
several cleanups for ifxmips. removes all code that has not been cleaned up properly
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@18008 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
parent
63b0dfc1a1
commit
88731c199b
@ -1 +1 @@
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obj-y := reset.o prom.o setup.o interrupt.o dma-core.o pmu.o board.o clock.o timer.o gpio.o
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obj-y := reset.o prom.o setup.o interrupt.o dma-core.o pmu.o board.o clock.o gpio.o
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@ -204,6 +204,7 @@ static struct gpio_led easy4010_leds[] = {
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static struct ifxmips_board boards[] = {
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{
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/* infineon eval kit */
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.type = EASY50712,
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.name = "EASY50712",
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.system_type = SYSTEM_DANUBE_CHIPID1,
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@ -214,6 +215,7 @@ static struct ifxmips_board boards[] = {
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.end = (1 << 0) | (1 << 1)},
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.ifxmips_leds = easy50712_leds,
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}, {
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/* infineon eval kit */
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.type = EASY4010,
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.name = "EASY4010",
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.system_type = SYSTEM_TWINPASS_CHIPID,
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@ -224,6 +226,7 @@ static struct ifxmips_board boards[] = {
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.end = (1 << 0) | (1 << 1)},
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.ifxmips_leds = easy4010_leds,
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}, {
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/* arcaydian annex-a board used by thompson, airties, ... */
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.type = ARV4519,
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.name = "ARV4519",
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.system_type = SYSTEM_DANUBE_CHIPID2,
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@ -361,6 +364,7 @@ int __init ifxmips_init_devices(void)
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ifxmips_led_data.num_leds = ARRAY_SIZE(easy4010_leds);
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break;
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case ARV4519:
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/* set some sane defaults for the gpios */
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gpio_set_value(3, 0);
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gpio_set_value(4, 0);
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gpio_set_value(5, 0);
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@ -111,6 +111,8 @@ static struct hw_interrupt_type ifxmips_irq_type = {
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.end = ifxmips_end_irq,
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};
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/* silicon bug causes only the msb set to 1 to be valid. all
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other bits might be bogus */
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static inline int ls1bit32(unsigned long x)
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{
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__asm__ (
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@ -14,6 +14,9 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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* code used for handling the power management unit of the danube. using
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* the pmu we can turn the power of the seperate ip cores on/off.
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*/
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#include <linux/kernel.h>
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@ -32,6 +32,7 @@ unsigned int prom_cp1_size;
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/* for Multithreading (APRP) on MIPS34K */
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unsigned long physical_memsize;
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/* early printk on asc0 or asc1 ? */
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#ifdef CONFIG_IFXMIPS_PROM_ASC0
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#define IFXMIPS_ASC_DIFF 0
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#else
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@ -1,119 +0,0 @@
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//*************************************************************************
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//* Summary of definitions which are used in each peripheral *
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//*************************************************************************
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#ifndef peripheral_definitions_h
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#define peripheral_definitions_h
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////#include "cpu.h"
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//
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///* These files have to be included by each peripheral */
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//#include <sysdefs.h>
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//#include <excep.h>
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//#include <cpusubsys.h>
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//#include <sys_api.h>
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//#include <mips.h>
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//#include "SRAM_address_map.h"
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//
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///* common header files for all CPU's */
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//#include "iiu.h"
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//#include "bcu.h"
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//#include "FPI_address_map.h"
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//#include "direct_interrupts.h"
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/////////////////////////////////////////////////////////////////////////
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//extern int _clz();
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//extern void _nop();
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//extern void _sleep();
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//extern void sys_enable_int();
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typedef unsigned char UINT8;
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typedef signed char INT8;
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typedef unsigned short UINT16;
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typedef signed short INT16;
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typedef unsigned int UINT32;
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typedef signed int INT32;
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typedef unsigned long long UINT64;
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typedef signed long long INT64;
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#define REG8( addr ) (*(volatile UINT8 *) (addr))
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#define REG16( addr ) (*(volatile UINT16 *)(addr))
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#define REG32( addr ) (*(volatile UINT32 *)(addr))
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#define REG64( addr ) (*(volatile UINT64 *)(addr))
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/* define routine to set FPI access in Supervisor Mode */
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#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01
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/* Supervisor mode ends, following functions will be done in User mode */
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#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00
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/* Supervisor mode ends, following functions will be done in User mode */
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#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG)
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/* Supervisor mode ends, following functions will be done in User mode */
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#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm
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/* enable all Interrupts in IIU */
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//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask
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///* get all high priority interrupt bits in IIU */
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//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED)
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///* signal ends of interrupt to IIU */
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//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit
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///* force IIU interrupt register */
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//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data
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///* get all bits of interrupt register */
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//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR)
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/* insert a NOP instruction */
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#define NOP _nop()
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/* CPU goes to power down mode until interrupt occurs */
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#define IFX_CPU_SLEEP _sleep()
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/* enable all interrupts to CPU */
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#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int()
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/* get all low priority interrupt bits in peripheral */
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#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg)
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/* clear low priority interrupt bit in peripheral */
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#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit
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/* write FPI bus */
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#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data
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#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data
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#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data
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/* read FPI bus */
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#define READ_FPI_BYTE(addr) REG8(addr)
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#define READ_FPI_16BIT(addr) REG16(addr)
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#define READ_FPI_32BIT(addr) REG32(addr)
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/* write peripheral register */
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#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data
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#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data
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#else //not CONFIG_CPU_LITTLE_ENDIAN
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#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data
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#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data
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#endif //CONFIG_CPU_LITTLE_ENDIAN
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/* read peripheral register */
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#define READ_PERIPHERAL_REGISTER(addr) REG32(addr)
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/* read/modify(or)/write peripheral register */
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#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data
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/* read/modify(and)/write peripheral register */
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#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data
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/* CPU-independent mnemonic constants */
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/* CLC register bits */
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#define IFX_CLC_ENABLE 0x00000000
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#define IFX_CLC_DISABLE 0x00000001
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#define IFX_CLC_DISABLE_STATUS 0x00000002
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#define IFX_CLC_SUSPEND_ENABLE 0x00000004
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#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008
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#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010
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#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020
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#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00
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#define IFX_CLC_RUN_DIVIDER_OFFSET 8
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#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000
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#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16
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#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000
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#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24
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/* number of cycles to wait for interrupt service routine to be called */
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#define WAIT_CYCLES 50
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#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */
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@ -1,258 +0,0 @@
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/*
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* ifx_ssc.h defines some data sructures used in ifx_ssc.c
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*
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* Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT)
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*
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*
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*/
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#ifndef __IFX_SSC_H
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#define __IFX_SSC_H
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#ifdef __KERNEL__
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#include <asm/ifxmips/ifx_ssc_defines.h>
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#endif //__KERNEL__
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#define PORT_CNT 1 // assume default value
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/* symbolic constants to be used in SSC routines */
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// ### TO DO: bad performance
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#define IFX_SSC_TXFIFO_ITL 1
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#define IFX_SSC_RXFIFO_ITL 1
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struct ifx_ssc_statistics {
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unsigned int abortErr; /* abort error */
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unsigned int modeErr; /* master/slave mode error */
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unsigned int txOvErr; /* TX Overflow error */
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unsigned int txUnErr; /* TX Underrun error */
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unsigned int rxOvErr; /* RX Overflow error */
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unsigned int rxUnErr; /* RX Underrun error */
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unsigned int rxBytes;
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unsigned int txBytes;
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};
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struct ifx_ssc_hwopts {
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unsigned int AbortErrDetect:1; /* Abort Error detection (in slave mode) */
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unsigned int rxOvErrDetect:1; /* Receive Overflow Error detection */
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unsigned int rxUndErrDetect:1; /* Receive Underflow Error detection */
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unsigned int txOvErrDetect:1; /* Transmit Overflow Error detection */
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unsigned int txUndErrDetect:1; /* Transmit Underflow Error detection */
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unsigned int echoMode:1; /* Echo mode */
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unsigned int loopBack:1; /* Loopback mode */
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unsigned int idleValue:1; /* Idle value */
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unsigned int clockPolarity:1; /* Idle clock is high or low */
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unsigned int clockPhase:1; /* Tx on trailing or leading edge */
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unsigned int headingControl:1; /* LSB first or MSB first */
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unsigned int dataWidth:6; /* from 2 up to 32 bits */
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unsigned int masterSelect:1; /* Master or Slave mode */
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unsigned int modeRxTx:2; /* rx/tx mode */
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unsigned int gpoCs:8; /* choose outputs to use for chip select */
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unsigned int gpoInv:8; /* invert GPO outputs */
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};
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struct ifx_ssc_frm_opts {
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bool FrameEnable; // SFCON.SFEN
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unsigned int DataLength; // SFCON.DLEN
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unsigned int PauseLength; // SFCON.PLEN
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unsigned int IdleData; // SFCON.IDAT
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unsigned int IdleClock; // SFCON.ICLK
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bool StopAfterPause; // SFCON.STOP
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};
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struct ifx_ssc_frm_status {
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bool DataBusy; // SFSTAT.DBSY
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bool PauseBusy; // SFSTAT.PBSY
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unsigned int DataCount; // SFSTAT.DCNT
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unsigned int PauseCount; // SFSTAT.PCNT
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bool EnIntAfterData; // SFCON.IBEN
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bool EnIntAfterPause; // SFCON.IAEN
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};
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typedef struct {
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char *buf;
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size_t len;
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} ifx_ssc_buf_item_t;
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// data structures for batch execution
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typedef union {
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struct {
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bool save_options;
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} init;
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ifx_ssc_buf_item_t read;
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ifx_ssc_buf_item_t write;
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ifx_ssc_buf_item_t rd_wr;
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unsigned int set_baudrate;
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struct ifx_ssc_frm_opts set_frm;
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unsigned int set_gpo;
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struct ifx_ssc_hwopts set_hwopts;
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} ifx_ssc_batch_cmd_param;
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struct ifx_ssc_batch_list {
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unsigned int cmd;
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ifx_ssc_batch_cmd_param cmd_param;
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struct ifx_ssc_batch_list *next;
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};
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#ifdef __KERNEL__
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#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE)
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struct ifx_ssc_port {
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unsigned long mapbase;
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struct ifx_ssc_hwopts opts;
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struct ifx_ssc_statistics stats;
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struct ifx_ssc_frm_status frm_status;
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struct ifx_ssc_frm_opts frm_opts;
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/* wait queue for ifx_ssc_read() */
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wait_queue_head_t rwait, pwait;
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int port_nr;
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char port_is_open; /* exclusive open - boolean */
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// int no_of_bits; /* number of _valid_ bits */
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// int elem_size; /* shift for element (no of bytes)*/
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/* buffer and pointers to the read/write position */
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char *rxbuf; /* buffer for RX */
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char *rxbuf_end; /* buffer end pointer for RX */
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volatile char *rxbuf_ptr; /* buffer write pointer for RX */
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char *txbuf; /* buffer for TX */
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char *txbuf_end; /* buffer end pointer for TX */
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volatile char *txbuf_ptr; /* buffer read pointer for TX */
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unsigned int baud;
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/* each channel has its own interrupts */
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/* (transmit/receive/error/frame) */
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unsigned int txirq, rxirq, errirq, frmirq;
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};
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/* default values for SSC configuration */
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// values of CON
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#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */
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#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */
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#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */
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#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */
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#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */
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#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */
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#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */
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#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */
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#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST
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#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX
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// other values
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#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */
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#ifdef CONFIG_USE_EMULATOR
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#define IFX_SSC_DEF_BAUDRATE 10000
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#else
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#define IFX_SSC_DEF_BAUDRATE 2000000
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#endif
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#define IFX_SSC_DEF_RMC 0x10
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#define IFX_SSC_DEF_TXFIFO_FL 8
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#define IFX_SSC_DEF_RXFIFO_FL 1
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#if 1 //TODO
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#define IFX_SSC_DEF_GPO_CS 0x3 /* no chip select */
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#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */
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#else
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#error "what is ur Chip Select???"
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#endif
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#define IFX_SSC_DEF_SFCON 0 /* no serial framing */
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#if 0
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#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
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IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT
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#endif
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#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
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IFX_SSC_R_BIT | IFX_SSC_E_BIT
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#endif /* __KERNEL__ */
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// batch execution commands
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#define IFX_SSC_BATCH_CMD_INIT 1
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#define IFX_SSC_BATCH_CMD_READ 2
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#define IFX_SSC_BATCH_CMD_WRITE 3
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#define IFX_SSC_BATCH_CMD_RD_WR 4
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#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5
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#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6
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#define IFX_SSC_BATCH_CMD_SET_FRM 7
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#define IFX_SSC_BATCH_CMD_SET_GPO 8
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#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9
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//#define IFX_SSC_BATCH_CMD_
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//#define IFX_SSC_BATCH_CMD_
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#define IFX_SSC_BATCH_CMD_END_EXEC 0
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/* Macros to configure SSC hardware */
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/* headingControl: */
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#define IFX_SSC_LSB_FIRST 0
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#define IFX_SSC_MSB_FIRST 1
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/* dataWidth: */
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#define IFX_SSC_MIN_DATA_WIDTH 2
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#define IFX_SSC_MAX_DATA_WIDTH 32
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/* master/slave mode select */
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#define IFX_SSC_MASTER_MODE 1
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#define IFX_SSC_SLAVE_MODE 0
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/* rx/tx mode */
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// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h
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#define IFX_SSC_MODE_RXTX 0
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#define IFX_SSC_MODE_RX 1
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#define IFX_SSC_MODE_TX 2
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#define IFX_SSC_MODE_OFF 3
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#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX
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/* GPO values */
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#define IFX_SSC_MAX_GPO_OUT 7
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#define IFX_SSC_RXREQ_BLOCK_SIZE 32768
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/***********************/
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/* defines for ioctl's */
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/***********************/
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#define IFX_SSC_IOCTL_MAGIC 'S'
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/* read out the statistics */
|
||||
#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics)
|
||||
/* clear the statistics */
|
||||
#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2)
|
||||
/* set the baudrate */
|
||||
#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int)
|
||||
/* get the current baudrate */
|
||||
#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int)
|
||||
/* set hardware options */
|
||||
#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts)
|
||||
/* get the current hardware options */
|
||||
#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts)
|
||||
/* set transmission mode */
|
||||
#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int)
|
||||
/* get the current transmission mode */
|
||||
#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int)
|
||||
/* abort transmission */
|
||||
#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9)
|
||||
#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9)
|
||||
|
||||
/* set general purpose outputs */
|
||||
#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int)
|
||||
/* clear general purpose outputs */
|
||||
#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int)
|
||||
/* get general purpose outputs */
|
||||
#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int)
|
||||
|
||||
/*** serial framing ***/
|
||||
/* get status of serial framing */
|
||||
#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status)
|
||||
/* get counter reload values and control bits */
|
||||
#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts)
|
||||
/* set counter reload values and control bits */
|
||||
#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts)
|
||||
|
||||
/*** batch execution ***/
|
||||
/* do batch execution */
|
||||
#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list)
|
||||
|
||||
#ifdef __KERNEL__
|
||||
// routines from ifx_ssc.c
|
||||
// ### TO DO
|
||||
/* kernel interface for read and write */
|
||||
ssize_t ifx_ssc_kread (int, char *, size_t);
|
||||
ssize_t ifx_ssc_kwrite (int, const char *, size_t);
|
||||
|
||||
#ifdef CONFIG_IFX_VP_KERNEL_TEST
|
||||
void ifx_ssc_tc (void);
|
||||
#endif // CONFIG_IFX_VP_KERNEL_TEST
|
||||
|
||||
#endif //__KERNEL__
|
||||
#endif // __IFX_SSC_H
|
||||
@ -1,547 +0,0 @@
|
||||
#ifndef IFX_SSC_DEFINES_H
|
||||
#define IFX_SSC_DEFINES_H
|
||||
|
||||
#include "ifx_peripheral_definitions.h"
|
||||
|
||||
/* maximum SSC FIFO size */
|
||||
#define IFX_SSC_MAX_FIFO_SIZE 32
|
||||
|
||||
/* register map of SSC */
|
||||
|
||||
/* address of the Clock Control Register of the SSC */
|
||||
#define IFX_SSC_CLC 0x00000000
|
||||
/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0
|
||||
bit 1 is hardware modified*/
|
||||
#define IFX_SSC_CLC_readmask 0x00FFFFEF
|
||||
#define IFX_SSC_CLC_writemask 0x00FFFF3D
|
||||
#define IFX_SSC_CLC_hwmask 0x00000002
|
||||
#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask)
|
||||
|
||||
/* address of Port Input Select Register of the SSC */
|
||||
#define IFX_SSC_PISEL 0x00000004
|
||||
/* IFX_SSC_PISEL register is significant in lowest three bits only */
|
||||
#define IFX_SSC_PISEL_readmask 0x00000007
|
||||
#define IFX_SSC_PISEL_writemask 0x00000007
|
||||
#define IFX_SSC_PISEL_hwmask 0x00000000
|
||||
#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask)
|
||||
|
||||
/* address of Identification Register of the SSC */
|
||||
#define IFX_SSC_ID 0x00000008
|
||||
/* IFX_SSC_ID register is significant in no bit */
|
||||
#define IFX_SSC_ID_readmask 0x0000FF3F
|
||||
#define IFX_SSC_ID_writemask 0x00000000
|
||||
#define IFX_SSC_ID_hwmask 0x00000000
|
||||
#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask)
|
||||
|
||||
/* address of the Control Register of the SSC */
|
||||
#define IFX_SSC_CON 0x00000010
|
||||
/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */
|
||||
#define IFX_SSC_CON_readmask 0x01DF1FFF
|
||||
#define IFX_SSC_CON_writemask 0x01DF1FFF
|
||||
#define IFX_SSC_CON_hwmask 0x00000000
|
||||
#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask)
|
||||
|
||||
/* address of the Status Register of the SSC */
|
||||
#define IFX_SSC_STATE 0x00000014
|
||||
/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0
|
||||
all bits except 1:0 are hardware modified */
|
||||
#define IFX_SSC_STATE_readmask 0x771F3F87
|
||||
#define IFX_SSC_STATE_writemask 0x00000000
|
||||
#define IFX_SSC_STATE_hwmask 0x771F3F84
|
||||
#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask)
|
||||
|
||||
/* address of the Write Hardware Modified Control Register Bits of the SSC */
|
||||
#define IFX_SSC_WHBSTATE 0x00000018
|
||||
/* IFX_SSC_WHBSTATE register is write only */
|
||||
#define IFX_SSC_WHBSTATE_readmask 0x00000000
|
||||
#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF
|
||||
#define IFX_SSC_WHBSTATE_hwmask 0x00000000
|
||||
#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask)
|
||||
|
||||
/* address of the Baudrate Timer Reload Register of the SSC */
|
||||
#define IFX_SSC_BR 0x00000040
|
||||
/* IFX_SSC_BR register is significant in bit 15 downto 0*/
|
||||
#define IFX_SSC_BR_readmask 0x0000FFFF
|
||||
#define IFX_SSC_BR_writemask 0x0000FFFF
|
||||
#define IFX_SSC_BR_hwmask 0x00000000
|
||||
#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask)
|
||||
|
||||
/* address of the Baudrate Timer Status Register of the SSC */
|
||||
#define IFX_SSC_BRSTAT 0x00000044
|
||||
/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/
|
||||
#define IFX_SSC_BRSTAT_readmask 0x0000FFFF
|
||||
#define IFX_SSC_BRSTAT_writemask 0x00000000
|
||||
#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF
|
||||
#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask)
|
||||
|
||||
/* address of the Transmitter Buffer Register of the SSC */
|
||||
#define IFX_SSC_TB 0x00000020
|
||||
/* IFX_SSC_TB register is significant in bit 31 downto 0*/
|
||||
#define IFX_SSC_TB_readmask 0xFFFFFFFF
|
||||
#define IFX_SSC_TB_writemask 0xFFFFFFFF
|
||||
#define IFX_SSC_TB_hwmask 0x00000000
|
||||
#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask)
|
||||
|
||||
/* address of the Reciver Buffer Register of the SSC */
|
||||
#define IFX_SSC_RB 0x00000024
|
||||
/* IFX_SSC_RB register is significant in no bits*/
|
||||
#define IFX_SSC_RB_readmask 0xFFFFFFFF
|
||||
#define IFX_SSC_RB_writemask 0x00000000
|
||||
#define IFX_SSC_RB_hwmask 0xFFFFFFFF
|
||||
#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask)
|
||||
|
||||
/* address of the Receive FIFO Control Register of the SSC */
|
||||
#define IFX_SSC_RXFCON 0x00000030
|
||||
/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
|
||||
#define IFX_SSC_RXFCON_readmask 0x00003F03
|
||||
#define IFX_SSC_RXFCON_writemask 0x00003F03
|
||||
#define IFX_SSC_RXFCON_hwmask 0x00000000
|
||||
#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask)
|
||||
|
||||
/* address of the Transmit FIFO Control Register of the SSC */
|
||||
#define IFX_SSC_TXFCON 0x00000034
|
||||
/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
|
||||
#define IFX_SSC_TXFCON_readmask 0x00003F03
|
||||
#define IFX_SSC_TXFCON_writemask 0x00003F03
|
||||
#define IFX_SSC_TXFCON_hwmask 0x00000000
|
||||
#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask)
|
||||
|
||||
/* address of the FIFO Status Register of the SSC */
|
||||
#define IFX_SSC_FSTAT 0x00000038
|
||||
/* IFX_SSC_FSTAT register is significant in no bit*/
|
||||
#define IFX_SSC_FSTAT_readmask 0x00003F3F
|
||||
#define IFX_SSC_FSTAT_writemask 0x00000000
|
||||
#define IFX_SSC_FSTAT_hwmask 0x00003F3F
|
||||
#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask)
|
||||
|
||||
/* address of the Data Frame Control register of the SSC */
|
||||
#define IFX_SSC_SFCON 0x00000060
|
||||
#define IFX_SSC_SFCON_readmask 0xFFDFFFFD
|
||||
#define IFX_SSC_SFCON_writemask 0xFFDFFFFD
|
||||
#define IFX_SSC_SFCON_hwmask 0x00000000
|
||||
#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask)
|
||||
|
||||
/* address of the Data Frame Status register of the SSC */
|
||||
#define IFX_SSC_SFSTAT 0x00000064
|
||||
#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3
|
||||
#define IFX_SSC_SFSTAT_writemask 0x00000000
|
||||
#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3
|
||||
#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask)
|
||||
|
||||
/* address of the General Purpose Output Control register of the SSC */
|
||||
#define IFX_SSC_GPOCON 0x00000070
|
||||
#define IFX_SSC_GPOCON_readmask 0x0000FFFF
|
||||
#define IFX_SSC_GPOCON_writemask 0x0000FFFF
|
||||
#define IFX_SSC_GPOCON_hwmask 0x00000000
|
||||
#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask)
|
||||
|
||||
/* address of the General Purpose Output Status register of the SSC */
|
||||
#define IFX_SSC_GPOSTAT 0x00000074
|
||||
#define IFX_SSC_GPOSTAT_readmask 0x000000FF
|
||||
#define IFX_SSC_GPOSTAT_writemask 0x00000000
|
||||
#define IFX_SSC_GPOSTAT_hwmask 0x00000000
|
||||
#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask)
|
||||
|
||||
/* address of the Force GPO Status register of the SSC */
|
||||
#define IFX_SSC_WHBGPOSTAT 0x00000078
|
||||
#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000
|
||||
#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF
|
||||
#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000
|
||||
#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask)
|
||||
|
||||
/* address of the Receive Request Register of the SSC */
|
||||
#define IFX_SSC_RXREQ 0x00000080
|
||||
#define IFX_SSC_RXREQ_readmask 0x0000FFFF
|
||||
#define IFX_SSC_RXREQ_writemask 0x0000FFFF
|
||||
#define IFX_SSC_RXREQ_hwmask 0x00000000
|
||||
#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask)
|
||||
|
||||
/* address of the Receive Count Register of the SSC */
|
||||
#define IFX_SSC_RXCNT 0x00000084
|
||||
#define IFX_SSC_RXCNT_readmask 0x0000FFFF
|
||||
#define IFX_SSC_RXCNT_writemask 0x00000000
|
||||
#define IFX_SSC_RXCNT_hwmask 0x0000FFFF
|
||||
#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask)
|
||||
|
||||
/* address of the DMA Configuration Register of the SSC */
|
||||
#define IFX_SSC_DMACON 0x000000EC
|
||||
#define IFX_SSC_DMACON_readmask 0x0000FFFF
|
||||
#define IFX_SSC_DMACON_writemask 0x00000000
|
||||
#define IFX_SSC_DMACON_hwmask 0x0000FFFF
|
||||
#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask)
|
||||
|
||||
//------------------------------------------------------
|
||||
// interrupt register for enabling interrupts, mask register of irq_reg
|
||||
#define IFX_SSC_IRN_EN 0xF4
|
||||
// read/write
|
||||
#define IFX_SSC_IRN_EN_readmask 0x0000000F
|
||||
#define IFX_SSC_IRN_EN_writemask 0x0000000F
|
||||
#define IFX_SSC_IRN_EN_hwmask 0x00000000
|
||||
#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask)
|
||||
|
||||
// interrupt register for accessing interrupts
|
||||
#define IFX_SSC_IRN_CR 0xF8
|
||||
// read/write
|
||||
#define IFX_SSC_IRN_CR_readmask 0x0000000F
|
||||
#define IFX_SSC_IRN_CR_writemask 0x0000000F
|
||||
#define IFX_SSC_IRN_CR_hwmask 0x0000000F
|
||||
#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask)
|
||||
|
||||
// interrupt register for stimulating interrupts
|
||||
#define IFX_SSC_IRN_ICR 0xFC
|
||||
// read/write
|
||||
#define IFX_SSC_IRN_ICR_readmask 0x0000000F
|
||||
#define IFX_SSC_IRN_ICR_writemask 0x0000000F
|
||||
#define IFX_SSC_IRN_ICR_hwmask 0x00000000
|
||||
#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask)
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// Number of IRQs and bitposition of IRQ
|
||||
#define IFX_SSC_NUM_IRQ 4
|
||||
#define IFX_SSC_T_BIT 0x00000001
|
||||
#define IFX_SSC_R_BIT 0x00000002
|
||||
#define IFX_SSC_E_BIT 0x00000004
|
||||
#define IFX_SSC_F_BIT 0x00000008
|
||||
|
||||
/* bit masks for SSC registers */
|
||||
|
||||
/* ID register */
|
||||
#define IFX_SSC_PERID_REV_MASK 0x0000001F
|
||||
#define IFX_SSC_PERID_CFG_MASK 0x00000020
|
||||
#define IFX_SSC_PERID_ID_MASK 0x0000FF00
|
||||
#define IFX_SSC_PERID_REV_OFFSET 0
|
||||
#define IFX_SSC_PERID_CFG_OFFSET 5
|
||||
#define IFX_SSC_PERID_ID_OFFSET 8
|
||||
#define IFX_SSC_PERID_ID 0x45
|
||||
#define IFX_SSC_PERID_DMA_ON 0x00000020
|
||||
#define IFX_SSC_PERID_RXFS_MASK 0x003F0000
|
||||
#define IFX_SSC_PERID_RXFS_OFFSET 16
|
||||
#define IFX_SSC_PERID_TXFS_MASK 0x3F000000
|
||||
#define IFX_SSC_PERID_TXFS_OFFSET 24
|
||||
|
||||
/* PISEL register */
|
||||
#define IFX_SSC_PISEL_MASTER_IN_A 0x0000
|
||||
#define IFX_SSC_PISEL_MASTER_IN_B 0x0001
|
||||
#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000
|
||||
#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002
|
||||
#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000
|
||||
#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004
|
||||
|
||||
/* IFX_SSC_CON register */
|
||||
#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000
|
||||
#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000
|
||||
#define IFX_SSC_CON_IDLE_HIGH 0x00800000
|
||||
#define IFX_SSC_CON_IDLE_LOW 0x00000000
|
||||
#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000
|
||||
#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000
|
||||
#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16
|
||||
#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000
|
||||
#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK)
|
||||
|
||||
#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000
|
||||
#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000
|
||||
|
||||
#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000
|
||||
#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000
|
||||
#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800
|
||||
#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000
|
||||
#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400
|
||||
#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000
|
||||
#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200
|
||||
#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000
|
||||
#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100
|
||||
#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000
|
||||
#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00
|
||||
#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000
|
||||
|
||||
#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080
|
||||
#define IFX_SSC_CON_NO_LOOPBACK 0x00000000
|
||||
#define IFX_SSC_CON_HALF_DUPLEX 0x00000080
|
||||
#define IFX_SSC_CON_FULL_DUPLEX 0x00000000
|
||||
#define IFX_SSC_CON_CLOCK_FALL 0x00000040
|
||||
#define IFX_SSC_CON_CLOCK_RISE 0x00000000
|
||||
#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000
|
||||
#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020
|
||||
#define IFX_SSC_CON_MSB_FIRST 0x00000010
|
||||
#define IFX_SSC_CON_LSB_FIRST 0x00000000
|
||||
#define IFX_SSC_CON_ENABLE_CSB 0x00000008
|
||||
#define IFX_SSC_CON_DISABLE_CSB 0x00000000
|
||||
#define IFX_SSC_CON_INVERT_CSB 0x00000004
|
||||
#define IFX_SSC_CON_TRUE_CSB 0x00000000
|
||||
#define IFX_SSC_CON_RX_OFF 0x00000002
|
||||
#define IFX_SSC_CON_RX_ON 0x00000000
|
||||
#define IFX_SSC_CON_TX_OFF 0x00000001
|
||||
#define IFX_SSC_CON_TX_ON 0x00000000
|
||||
|
||||
/* IFX_SSC_STATE register */
|
||||
#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28
|
||||
#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000
|
||||
#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET)
|
||||
#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24
|
||||
#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000
|
||||
#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET)
|
||||
#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16
|
||||
#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000
|
||||
#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1)
|
||||
#define IFX_SSC_STATE_BUSY 0x00002000
|
||||
#define IFX_SSC_STATE_RX_UFL 0x00001000
|
||||
#define IFX_SSC_STATE_TX_UFL 0x00000800
|
||||
#define IFX_SSC_STATE_ABORT_ERR 0x00000400
|
||||
#define IFX_SSC_STATE_RX_OFL 0x00000200
|
||||
#define IFX_SSC_STATE_TX_OFL 0x00000100
|
||||
#define IFX_SSC_STATE_MODE_ERR 0x00000080
|
||||
#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004
|
||||
#define IFX_SSC_STATE_IS_MASTER 0x00000002
|
||||
#define IFX_SSC_STATE_IS_ENABLED 0x00000001
|
||||
|
||||
/* WHBSTATE register */
|
||||
#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001
|
||||
#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001
|
||||
#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001
|
||||
|
||||
#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002
|
||||
#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002
|
||||
#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002
|
||||
|
||||
#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004
|
||||
#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004
|
||||
|
||||
#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008
|
||||
#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008
|
||||
|
||||
#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010
|
||||
#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020
|
||||
|
||||
#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040
|
||||
#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080
|
||||
|
||||
#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100
|
||||
#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200
|
||||
#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400
|
||||
#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800
|
||||
#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000
|
||||
#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000
|
||||
#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000
|
||||
#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000
|
||||
#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50
|
||||
#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0
|
||||
|
||||
/* BR register */
|
||||
#define IFX_SSC_BR_BAUDRATE_OFFSET 0
|
||||
#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF
|
||||
|
||||
/* BR_STAT register */
|
||||
#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0
|
||||
#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF
|
||||
|
||||
/* TB register */
|
||||
#define IFX_SSC_TB_DATA_OFFSET 0
|
||||
#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF
|
||||
|
||||
/* RB register */
|
||||
#define IFX_SSC_RB_DATA_OFFSET 0
|
||||
#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF
|
||||
|
||||
/* RXFCON and TXFCON registers */
|
||||
#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000
|
||||
#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001
|
||||
#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002
|
||||
#define IFX_SSC_XFCON_ITL_MASK 0x00003F00
|
||||
#define IFX_SSC_XFCON_ITL_OFFSET 8
|
||||
|
||||
/* FSTAT register */
|
||||
#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0
|
||||
#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F
|
||||
#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8
|
||||
#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00
|
||||
|
||||
/* GPOCON register */
|
||||
#define IFX_SSC_GPOCON_INVOUT0_POS 0
|
||||
#define IFX_SSC_GPOCON_INV_OUT0 0x00000001
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT1_POS 1
|
||||
#define IFX_SSC_GPOCON_INV_OUT1 0x00000002
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT2_POS 2
|
||||
#define IFX_SSC_GPOCON_INV_OUT2 0x00000003
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT3_POS 3
|
||||
#define IFX_SSC_GPOCON_INV_OUT3 0x00000008
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT4_POS 4
|
||||
#define IFX_SSC_GPOCON_INV_OUT4 0x00000010
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT5_POS 5
|
||||
#define IFX_SSC_GPOCON_INV_OUT5 0x00000020
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT6_POS 6
|
||||
#define IFX_SSC_GPOCON_INV_OUT6 0x00000040
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT7_POS 7
|
||||
#define IFX_SSC_GPOCON_INV_OUT7 0x00000080
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000
|
||||
#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000
|
||||
|
||||
#define IFX_SSC_GPOCON_ISCSB0_POS 8
|
||||
#define IFX_SSC_GPOCON_IS_CSB0 0x00000100
|
||||
#define IFX_SSC_GPOCON_IS_GPO0 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB1_POS 9
|
||||
#define IFX_SSC_GPOCON_IS_CSB1 0x00000200
|
||||
#define IFX_SSC_GPOCON_IS_GPO1 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB2_POS 10
|
||||
#define IFX_SSC_GPOCON_IS_CSB2 0x00000400
|
||||
#define IFX_SSC_GPOCON_IS_GPO2 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB3_POS 11
|
||||
#define IFX_SSC_GPOCON_IS_CSB3 0x00000800
|
||||
#define IFX_SSC_GPOCON_IS_GPO3 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB4_POS 12
|
||||
#define IFX_SSC_GPOCON_IS_CSB4 0x00001000
|
||||
#define IFX_SSC_GPOCON_IS_GPO4 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB5_POS 13
|
||||
#define IFX_SSC_GPOCON_IS_CSB5 0x00002000
|
||||
#define IFX_SSC_GPOCON_IS_GPO5 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB6_POS 14
|
||||
#define IFX_SSC_GPOCON_IS_CSB6 0x00004000
|
||||
#define IFX_SSC_GPOCON_IS_GPO6 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB7_POS 15
|
||||
#define IFX_SSC_GPOCON_IS_CSB7 0x00008000
|
||||
#define IFX_SSC_GPOCON_IS_GPO7 0x00000000
|
||||
#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00
|
||||
#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000
|
||||
|
||||
/* GPOSTAT register */
|
||||
#define IFX_SSC_GPOSTAT_OUT0 0x00000001
|
||||
#define IFX_SSC_GPOSTAT_OUT1 0x00000002
|
||||
#define IFX_SSC_GPOSTAT_OUT2 0x00000004
|
||||
#define IFX_SSC_GPOSTAT_OUT3 0x00000008
|
||||
#define IFX_SSC_GPOSTAT_OUT4 0x00000010
|
||||
#define IFX_SSC_GPOSTAT_OUT5 0x00000020
|
||||
#define IFX_SSC_GPOSTAT_OUT6 0x00000040
|
||||
#define IFX_SSC_GPOSTAT_OUT7 0x00000080
|
||||
#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF
|
||||
|
||||
/* WHBGPOSTAT register */
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF
|
||||
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7
|
||||
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00
|
||||
|
||||
/* SFCON register */
|
||||
#define IFX_SSC_SFCON_SF_ENABLE 0x00000001
|
||||
#define IFX_SSC_SFCON_SF_DISABLE 0x00000000
|
||||
#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004
|
||||
#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000
|
||||
#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008
|
||||
#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000
|
||||
#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0
|
||||
#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4
|
||||
#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000
|
||||
#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16
|
||||
#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000
|
||||
#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000
|
||||
#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000
|
||||
#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000
|
||||
#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000
|
||||
#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000
|
||||
#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22
|
||||
#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096
|
||||
#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024
|
||||
|
||||
#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET)
|
||||
#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET)
|
||||
#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK)
|
||||
#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK)
|
||||
|
||||
/* SFSTAT register */
|
||||
#define IFX_SSC_SFSTAT_IN_DATA 0x00000001
|
||||
#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002
|
||||
#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0
|
||||
#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4
|
||||
#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000
|
||||
#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20
|
||||
|
||||
#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET)
|
||||
#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET)
|
||||
|
||||
/* RXREQ register */
|
||||
#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF
|
||||
#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0
|
||||
|
||||
/* RXCNT register */
|
||||
#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF
|
||||
#define IFX_SSC_RXCNT_TODO_OFFSET 0
|
||||
|
||||
/* DMACON register */
|
||||
#define IFX_SSC_DMACON_RXON 0x00000001
|
||||
#define IFX_SSC_DMACON_RXOFF 0x00000000
|
||||
#define IFX_SSC_DMACON_TXON 0x00000002
|
||||
#define IFX_SSC_DMACON_TXOFF 0x00000000
|
||||
#define IFX_SSC_DMACON_DMAON 0x00000003
|
||||
#define IFX_SSC_DMACON_DMAOFF 0x00000000
|
||||
#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C
|
||||
#define IFX_SSC_DMACON_CLASS_OFFSET 2
|
||||
|
||||
/* register access macros */
|
||||
#define ifx_ssc_fstat_received_words(status) (status & 0x003F)
|
||||
#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8)
|
||||
|
||||
#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE))
|
||||
#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON))
|
||||
#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON))
|
||||
#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE))
|
||||
#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB))
|
||||
#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB))
|
||||
#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT))
|
||||
#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR))
|
||||
|
||||
#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET)
|
||||
#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
|
||||
|
||||
#endif
|
||||
@ -1,270 +0,0 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : danube_mei.h
|
||||
** PROJECT : Danube
|
||||
** MODULES : MEI
|
||||
**
|
||||
** DATE : 1 Jan 2006
|
||||
** AUTHOR : TC Chen
|
||||
** DESCRIPTION : MEI Driver
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Version $Date $Author $Comment
|
||||
*******************************************************************************/
|
||||
#ifndef _IFXMIPS_MEI_H
|
||||
#define _IFXMIPS_MEI_H
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "ifxmips_mei_app.h"
|
||||
|
||||
#define IFXMIPS_MEI_DEBUG
|
||||
#define IFXMIPS_MEI_CMV_EXTRA
|
||||
#define IFXMIPS_MEI_MAJOR 106
|
||||
|
||||
/*
|
||||
** Define where in ME Processor's memory map the Stratify chip lives
|
||||
*/
|
||||
|
||||
#define MAXSWAPSIZE 8 * 1024 //8k *(32bits)
|
||||
|
||||
// Mailboxes
|
||||
#define MSG_LENGTH 16 // x16 bits
|
||||
#define YES_REPLY 1
|
||||
#define NO_REPLY 0
|
||||
|
||||
#define CMV_TIMEOUT 100 //jiffies
|
||||
#define MIB_INTERVAL 10000 //msec
|
||||
|
||||
/*** Bit definitions ***/
|
||||
|
||||
#define FALSE 0
|
||||
#define TRUE 1
|
||||
#define BIT0 1<<0
|
||||
#define BIT1 1<<1
|
||||
#define BIT2 1<<2
|
||||
#define BIT3 1<<3
|
||||
#define BIT4 1<<4
|
||||
#define BIT5 1<<5
|
||||
#define BIT6 1<<6
|
||||
#define BIT7 1<<7
|
||||
#define BIT8 1<<8
|
||||
#define BIT9 1<<9
|
||||
#define BIT10 1<<10
|
||||
#define BIT11 1<<11
|
||||
#define BIT12 1<<12
|
||||
#define BIT13 1<<13
|
||||
#define BIT14 1<<14
|
||||
#define BIT15 1<<15
|
||||
#define BIT16 1<<16
|
||||
#define BIT17 1<<17
|
||||
#define BIT18 1<<18
|
||||
#define BIT19 1<<19
|
||||
#define BIT20 1<<20
|
||||
#define BIT21 1<<21
|
||||
#define BIT22 1<<22
|
||||
#define BIT23 1<<23
|
||||
#define BIT24 1<<24
|
||||
#define BIT25 1<<25
|
||||
#define BIT26 1<<26
|
||||
#define BIT27 1<<27
|
||||
#define BIT28 1<<28
|
||||
#define BIT29 1<<29
|
||||
#define BIT30 1<<30
|
||||
#define BIT31 1<<31
|
||||
|
||||
// ARC register addresss
|
||||
#define ARC_STATUS 0x0
|
||||
#define ARC_LP_START 0x2
|
||||
#define ARC_LP_END 0x3
|
||||
#define ARC_DEBUG 0x5
|
||||
#define ARC_INT_MASK 0x10A
|
||||
|
||||
#define IRAM0_BASE (0x00000)
|
||||
#define IRAM1_BASE (0x04000)
|
||||
#define BRAM_BASE (0x0A000)
|
||||
|
||||
#define ADSL_BASE (0x20000)
|
||||
#define CRI_BASE (ADSL_BASE + 0x11F00)
|
||||
#define CRI_CCR0 (CRI_BASE + 0x00)
|
||||
#define CRI_RST (CRI_BASE + 0x04*4)
|
||||
#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
|
||||
|
||||
//
|
||||
#define IRAM0_ADDR_BIT_MASK 0xFFF
|
||||
#define IRAM1_ADDR_BIT_MASK 0xFFF
|
||||
#define BRAM_ADDR_BIT_MASK 0xFFF
|
||||
#define RX_DILV_ADDR_BIT_MASK 0x1FFF
|
||||
|
||||
// CRI_CCR0 Register definitions
|
||||
#define CLK_2M_MODE_ENABLE BIT6
|
||||
#define ACL_CLK_MODE_ENABLE BIT4
|
||||
#define FDF_CLK_MODE_ENABLE BIT2
|
||||
#define STM_CLK_MODE_ENABLE BIT0
|
||||
|
||||
// CRI_RST Register definitions
|
||||
#define FDF_SRST BIT3
|
||||
#define MTE_SRST BIT2
|
||||
#define FCI_SRST BIT1
|
||||
#define AAI_SRST BIT0
|
||||
|
||||
// MEI_TO_ARC_INTERRUPT Register definitions
|
||||
#define MEI_TO_ARC_INT1 BIT3
|
||||
#define MEI_TO_ARC_INT0 BIT2
|
||||
#define MEI_TO_ARC_CS_DONE BIT1 //need to check
|
||||
#define MEI_TO_ARC_MSGAV BIT0
|
||||
|
||||
// ARC_TO_MEI_INTERRUPT Register definitions
|
||||
#define ARC_TO_MEI_INT1 BIT8
|
||||
#define ARC_TO_MEI_INT0 BIT7
|
||||
#define ARC_TO_MEI_CS_REQ BIT6
|
||||
#define ARC_TO_MEI_DBG_DONE BIT5
|
||||
#define ARC_TO_MEI_MSGACK BIT4
|
||||
#define ARC_TO_MEI_NO_ACCESS BIT3
|
||||
#define ARC_TO_MEI_CHECK_AAITX BIT2
|
||||
#define ARC_TO_MEI_CHECK_AAIRX BIT1
|
||||
#define ARC_TO_MEI_MSGAV BIT0
|
||||
|
||||
// ARC_TO_MEI_INTERRUPT_MASK Register definitions
|
||||
#define GP_INT1_EN BIT8
|
||||
#define GP_INT0_EN BIT7
|
||||
#define CS_REQ_EN BIT6
|
||||
#define DBG_DONE_EN BIT5
|
||||
#define MSGACK_EN BIT4
|
||||
#define NO_ACC_EN BIT3
|
||||
#define AAITX_EN BIT2
|
||||
#define AAIRX_EN BIT1
|
||||
#define MSGAV_EN BIT0
|
||||
|
||||
#define MEI_SOFT_RESET BIT0
|
||||
|
||||
#define HOST_MSTR BIT0
|
||||
|
||||
#define JTAG_MASTER_MODE 0x0
|
||||
#define MEI_MASTER_MODE HOST_MSTR
|
||||
|
||||
// MEI_DEBUG_DECODE Register definitions
|
||||
#define MEI_DEBUG_DEC_MASK (0x3)
|
||||
#define MEI_DEBUG_DEC_AUX_MASK (0x0)
|
||||
#define MEI_DEBUG_DEC_DMP1_MASK (0x1)
|
||||
#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
|
||||
#define MEI_DEBUG_DEC_CORE_MASK (0x3)
|
||||
|
||||
#define AUX_STATUS (0x0)
|
||||
// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
|
||||
// page swap requests.
|
||||
#define MEI_TO_ARC_MAILBOX (0xDFD0)
|
||||
#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
|
||||
|
||||
#define ARC_TO_MEI_MAILBOX (0xDFA0)
|
||||
#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
|
||||
|
||||
// Codeswap request messages are indicated by setting BIT31
|
||||
#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
|
||||
|
||||
// Clear Eoc messages received are indicated by setting BIT17
|
||||
#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
|
||||
|
||||
/*
|
||||
** Swap page header
|
||||
*/
|
||||
// Page must be loaded at boot time if size field has BIT31 set
|
||||
#define BOOT_FLAG (BIT31)
|
||||
#define BOOT_FLAG_MASK ~BOOT_FLAG
|
||||
|
||||
#define FREE_RELOAD 1
|
||||
#define FREE_SHOWTIME 2
|
||||
#define FREE_ALL 3
|
||||
|
||||
#define IFX_POP_EOC_DONE 0
|
||||
#define IFX_POP_EOC_FAIL -1
|
||||
|
||||
#define CLREOC_BUFF_SIZE 12 //number of clreoc commands being buffered
|
||||
|
||||
// marcos
|
||||
#define IFXMIPS_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data);} while (0)
|
||||
#define IFXMIPS_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
|
||||
#define SET_BIT(reg, mask) reg |= (mask)
|
||||
#define CLEAR_BIT(reg, mask) reg &= (~mask)
|
||||
#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
|
||||
#define SET_BITS(reg, mask) SET_BIT(reg, mask)
|
||||
#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
|
||||
|
||||
#define ALIGN_SIZE ( 1L<<10 ) //1K size align
|
||||
#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
|
||||
|
||||
// swap marco
|
||||
#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
|
||||
#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
|
||||
|
||||
// Swap page header describes size in 32-bit words, load location, and image offset
|
||||
// for program and/or data segments
|
||||
typedef struct _arc_swp_page_hdr {
|
||||
u32 p_offset; //Offset bytes of progseg from beginning of image
|
||||
u32 p_dest; //Destination addr of progseg on processor
|
||||
u32 p_size; //Size in 32-bitwords of program segment
|
||||
u32 d_offset; //Offset bytes of dataseg from beginning of image
|
||||
u32 d_dest; //Destination addr of dataseg on processor
|
||||
u32 d_size; //Size in 32-bitwords of data segment
|
||||
} ARC_SWP_PAGE_HDR;
|
||||
|
||||
#ifdef CONFIG_PROC_FS
|
||||
typedef struct reg_entry {
|
||||
int *flag;
|
||||
char name[30]; // big enough to hold names
|
||||
char description[100]; // big enough to hold description
|
||||
unsigned short low_ino;
|
||||
} reg_entry_t;
|
||||
#endif
|
||||
|
||||
/*
|
||||
** Swap image header
|
||||
*/
|
||||
#define GET_PROG 0 // Flag used for program mem segment
|
||||
#define GET_DATA 1 // Flag used for data mem segment
|
||||
|
||||
// Image header contains size of image, checksum for image, and count of
|
||||
// page headers. Following that are 'count' page headers followed by
|
||||
// the code and/or data segments to be loaded
|
||||
typedef struct _arc_img_hdr {
|
||||
u32 size; // Size of binary image in bytes
|
||||
u32 checksum; // Checksum for image
|
||||
u32 count; // Count of swp pages in image
|
||||
ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
|
||||
} ARC_IMG_HDR;
|
||||
|
||||
typedef struct smmu_mem_info {
|
||||
int type;
|
||||
unsigned long nCopy;
|
||||
unsigned long size;
|
||||
unsigned char *address;
|
||||
unsigned char *org_address;
|
||||
} smmu_mem_info_t;
|
||||
|
||||
/*
|
||||
** Native size for the Stratiphy interface is 32-bits. All reads and writes
|
||||
** MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or
|
||||
** byte data. Read routines are provided. Write routines are probably a bad idea, as the
|
||||
** Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle
|
||||
** could very well have unintended results.
|
||||
*/
|
||||
MEI_ERROR meiCMV (u16 *, int, u16 *); // first arg is CMV to ARC, second to indicate whether need reply
|
||||
|
||||
MEI_ERROR meiDebugWrite (u32 destaddr, u32 * databuff, u32 databuffsize);
|
||||
extern int ifx_mei_hdlc_send (char *hdlc_pkt, int hdlc_pkt_len);
|
||||
extern int ifx_mei_hdlc_read (char *hdlc_pkt, int max_hdlc_pkt_len);
|
||||
#if defined(__KERNEL__) || defined (IFXMIPS_PORT_RTEMS)
|
||||
extern void makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size,
|
||||
u16 * data, u16 * CMVMSG);
|
||||
int ifx_mei_hdlc_send (char *, int);
|
||||
int ifx_mei_hdlc_read (char *, int);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,116 +0,0 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_mei_app.h
|
||||
** PROJECT : Danube
|
||||
** MODULES : MEI
|
||||
**
|
||||
** DATE : 1 Jan 2006
|
||||
** AUTHOR : TC Chen
|
||||
** DESCRIPTION : MEI Driver
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Version $Date $Author $Comment
|
||||
*******************************************************************************/
|
||||
#ifndef _IFXMIPS_MEI_APP_H
|
||||
#define _IFXMIPS_MEI_APP_H
|
||||
// ioctl control
|
||||
#define IFXMIPS_MEI_START 300
|
||||
#define IFXMIPS_MEI_REPLY 301
|
||||
#define IFXMIPS_MEI_NOREPLY 302
|
||||
|
||||
#define IFXMIPS_MEI_RESET 303
|
||||
#define IFXMIPS_MEI_REBOOT 304
|
||||
#define IFXMIPS_MEI_HALT 305
|
||||
#define IFXMIPS_MEI_CMV_WINHOST 306
|
||||
#define IFXMIPS_MEI_CMV_READ 307
|
||||
#define IFXMIPS_MEI_CMV_WRITE 308
|
||||
#define IFXMIPS_MEI_MIB_DAEMON 309
|
||||
#define IFXMIPS_MEI_SHOWTIME 310
|
||||
#define IFXMIPS_MEI_REMOTE 311
|
||||
#define IFXMIPS_MEI_READDEBUG 312
|
||||
#define IFXMIPS_MEI_WRITEDEBUG 313
|
||||
#define IFXMIPS_MEI_LOP 314
|
||||
|
||||
#define IFXMIPS_MEI_PCM_SETUP 315
|
||||
#define IFXMIPS_MEI_PCM_START_TIMER 316
|
||||
#define IFXMIPS_MEI_PCM_STOP_TIMER 317
|
||||
#define IFXMIPS_MEI_PCM_CHECK 318
|
||||
#define IFXMIPS_MEI_GET_EOC_LEN 319
|
||||
#define IFXMIPS_MEI_GET_EOC_DATA 320
|
||||
#define IFXMIPS_MEI_PCM_GETDATA 321
|
||||
#define IFXMIPS_MEI_PCM_GPIO 322
|
||||
#define IFXMIPS_MEI_EOC_SEND 323
|
||||
#define IFXMIPS_MEI_DOWNLOAD 326
|
||||
#define IFXMIPS_MEI_JTAG_ENABLE 327
|
||||
#define IFXMIPS_MEI_RUN 328
|
||||
#define IFXMIPS_MEI_DEBUG_MODE 329
|
||||
|
||||
/* Loop diagnostics mode of the ADSL line related constants */
|
||||
#define SET_ADSL_LOOP_DIAGNOSTICS_MODE 330
|
||||
#define GET_ADSL_LOOP_DIAGNOSTICS_MODE 331
|
||||
#define LOOP_DIAGNOSTIC_MODE_COMPLETE 332
|
||||
#define IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE 333
|
||||
|
||||
/* L3 Power Mode */
|
||||
/* Get current Power Moaagement Mode Status*/
|
||||
#define GET_POWER_MANAGEMENT_MODE 334
|
||||
/* Set L3 Power Mode /disable L3 power mode */
|
||||
#define SET_L3_POWER_MODE 335
|
||||
|
||||
/* get current dual latency configuration */
|
||||
#define GET_ADSL_DUAL_LATENCY 336
|
||||
/* enable/disable dual latency path */
|
||||
#define SET_ADSL_DUAL_LATENCY 337
|
||||
|
||||
/* Enable/Disable autoboot mode. */
|
||||
/* When the autoboot mode is disabled, the driver will excute some cmv
|
||||
commands for led control and dual latency when DSL startup.*/
|
||||
#define AUTOBOOT_ENABLE_SET 338
|
||||
|
||||
/* Enable/Disable Quiet Mode*/
|
||||
/* Quiet mode is used for firmware debug. if the quiet mode enable, the autoboot daemon will not reset arc when the arc need to reboot */
|
||||
#define QUIET_MODE_GET 339
|
||||
#define QUIET_MODE_SET 340
|
||||
|
||||
/* Enable/Disable showtime lock*/
|
||||
/* showtime lock is used for firmware debug. if the showtime lock enable, the autoboot daemon will not reset arc when the arc reach showtime and need to reboot */
|
||||
#define SHOWTIME_LOCK_GET 341
|
||||
#define SHOWTIME_LOCK_SET 342
|
||||
|
||||
#define L0_POWER_MODE 0
|
||||
#define L2_POWER_MODE 2
|
||||
#define L3_POWER_MODE 3
|
||||
|
||||
#define DUAL_LATENCY_US_DS_DISABLE 0
|
||||
#define DUAL_LATENCY_US_ENABLE (1<<0)
|
||||
#define DUAL_LATENCY_DS_ENABLE (1<<1)
|
||||
#define DUAL_LATENCY_US_DS_ENABLE (DUAL_LATENCY_US_ENABLE|DUAL_LATENCY_DS_ENABLE)
|
||||
|
||||
#define ME_HDLC_IDLE 0
|
||||
#define ME_HDLC_INVALID_MSG 1
|
||||
#define ME_HDLC_MSG_QUEUED 2
|
||||
#define ME_HDLC_MSG_SENT 3
|
||||
#define ME_HDLC_RESP_RCVD 4
|
||||
#define ME_HDLC_RESP_TIMEOUT 5
|
||||
#define ME_HDLC_RX_BUF_OVERFLOW 6
|
||||
#define ME_HDLC_UNRESOLVED 1
|
||||
#define ME_HDLC_RESOLVED 2
|
||||
|
||||
/*** Enums ***/
|
||||
typedef enum mei_error {
|
||||
MEI_SUCCESS = 0,
|
||||
MEI_FAILURE = -1,
|
||||
MEI_MAILBOX_FULL = -2,
|
||||
MEI_MAILBOX_EMPTY = -3,
|
||||
MEI_MAILBOX_TIMEOUT = -4,
|
||||
} MEI_ERROR;
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,308 +0,0 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_mei_bsp.h
|
||||
** PROJECT : Danube
|
||||
** MODULES : MEI
|
||||
**
|
||||
** DATE : 1 Jan 2006
|
||||
** AUTHOR : TC Chen
|
||||
** DESCRIPTION : MEI Driver
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Version $Date $Author $Comment
|
||||
*******************************************************************************/
|
||||
#ifndef _IFXMIPS_MEI_BSP_H_
|
||||
#define _IFXMIPS_MEI_BSP_H_
|
||||
|
||||
/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
|
||||
#define MEI_DATA_XFR_OFFSET (0x0000)
|
||||
#define MEI_VERSION_OFFSET (0x0004)
|
||||
#define MEI_ARC_GP_STAT_OFFSET (0x0008)
|
||||
#define MEI_DATA_XFR_STAT_OFFSET (0x000C)
|
||||
#define MEI_XFR_ADDR_OFFSET (0x0010)
|
||||
#define MEI_MAX_WAIT_OFFSET (0x0014)
|
||||
#define MEI_TO_ARC_INT_OFFSET (0x0018)
|
||||
#define ARC_TO_MEI_INT_OFFSET (0x001C)
|
||||
#define ARC_TO_MEI_INT_MASK_OFFSET (0x0020)
|
||||
#define MEI_DEBUG_WAD_OFFSET (0x0024)
|
||||
#define MEI_DEBUG_RAD_OFFSET (0x0028)
|
||||
#define MEI_DEBUG_DATA_OFFSET (0x002C)
|
||||
#define MEI_DEBUG_DEC_OFFSET (0x0030)
|
||||
#define MEI_CONFIG_OFFSET (0x0034)
|
||||
#define MEI_RST_CONTROL_OFFSET (0x0038)
|
||||
#define MEI_DBG_MASTER_OFFSET (0x003C)
|
||||
#define MEI_CLK_CONTROL_OFFSET (0x0040)
|
||||
#define MEI_BIST_CONTROL_OFFSET (0x0044)
|
||||
#define MEI_BIST_STAT_OFFSET (0x0048)
|
||||
#define MEI_XDATA_BASE_SH_OFFSET (0x004c)
|
||||
#define MEI_XDATA_BASE_OFFSET (0x0050)
|
||||
#define MEI_XMEM_BAR_BASE_OFFSET (0x0054)
|
||||
#define MEI_XMEM_BAR0_OFFSET (0x0054)
|
||||
#define MEI_XMEM_BAR1_OFFSET (0x0058)
|
||||
#define MEI_XMEM_BAR2_OFFSET (0x005C)
|
||||
#define MEI_XMEM_BAR3_OFFSET (0x0060)
|
||||
#define MEI_XMEM_BAR4_OFFSET (0x0064)
|
||||
#define MEI_XMEM_BAR5_OFFSET (0x0068)
|
||||
#define MEI_XMEM_BAR6_OFFSET (0x006C))
|
||||
#define MEI_XMEM_BAR7_OFFSET (0x0070)
|
||||
#define MEI_XMEM_BAR8_OFFSET (0x0074)
|
||||
#define MEI_XMEM_BAR9_OFFSET (0x0078)
|
||||
#define MEI_XMEM_BAR10_OFFSET (0x007C)
|
||||
#define MEI_XMEM_BAR11_OFFSET (0x0080)
|
||||
#define MEI_XMEM_BAR12_OFFSET (0x0084)
|
||||
#define MEI_XMEM_BAR13_OFFSET (0x0088)
|
||||
#define MEI_XMEM_BAR14_OFFSET (0x008C)
|
||||
#define MEI_XMEM_BAR15_OFFSET (0x0090)
|
||||
#define MEI_XMEM_BAR16_OFFSET (0x0094)
|
||||
|
||||
#define WHILE_DELAY 20000
|
||||
/*
|
||||
** Define where in ME Processor's memory map the Stratify chip lives
|
||||
*/
|
||||
|
||||
#define MAXSWAPSIZE 8 * 1024 //8k *(32bits)
|
||||
|
||||
// Mailboxes
|
||||
#define MSG_LENGTH 16 // x16 bits
|
||||
#define YES_REPLY 1
|
||||
#define NO_REPLY 0
|
||||
|
||||
#define CMV_TIMEOUT 1000 //jiffies
|
||||
|
||||
// Block size per BAR
|
||||
#define SDRAM_SEGMENT_SIZE (64*1024)
|
||||
// Number of Bar registers
|
||||
#define MAX_BAR_REGISTERS (17)
|
||||
|
||||
#define XDATA_REGISTER (15)
|
||||
|
||||
#define IFXMIPS_MEI_IOCTL_CMV_WINHOST IFX_ADSL_IOC_CMV_WINHOST
|
||||
|
||||
#define IFXMIPS_MEI_IOCTL_CMV_READ IFX_ADSL_IOC_CMV_READ
|
||||
#define IFXMIPS_MEI_IOCTL_CMV_WRITE IFX_ADSL_IOC_CMV_WRITE
|
||||
|
||||
#define IFXMIPS_MEI_IOCTL_GET_BASE_ADDRESS IFX_ADSL_IOC_GET_BASE_ADDRESS
|
||||
|
||||
// ARC register addresss
|
||||
#define ARC_STATUS 0x0
|
||||
#define ARC_LP_START 0x2
|
||||
#define ARC_LP_END 0x3
|
||||
#define ARC_DEBUG 0x5
|
||||
#define ARC_INT_MASK 0x10A
|
||||
|
||||
#define IRAM0_BASE (0x00000)
|
||||
#define IRAM1_BASE (0x04000)
|
||||
#define BRAM_BASE (0x0A000)
|
||||
|
||||
#define ADSL_BASE (0x20000)
|
||||
#define CRI_BASE (ADSL_BASE + 0x11F00)
|
||||
#define CRI_CCR0 (CRI_BASE + 0x00)
|
||||
#define CRI_RST (CRI_BASE + 0x04*4)
|
||||
#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
|
||||
|
||||
//
|
||||
#define IRAM0_ADDR_BIT_MASK 0xFFF
|
||||
#define IRAM1_ADDR_BIT_MASK 0xFFF
|
||||
#define BRAM_ADDR_BIT_MASK 0xFFF
|
||||
#define RX_DILV_ADDR_BIT_MASK 0x1FFF
|
||||
|
||||
/*** Bit definitions ***/
|
||||
|
||||
#define FALSE 0
|
||||
#define TRUE 1
|
||||
#define BIT0 1<<0
|
||||
#define BIT1 1<<1
|
||||
#define BIT2 1<<2
|
||||
#define BIT3 1<<3
|
||||
#define BIT4 1<<4
|
||||
#define BIT5 1<<5
|
||||
#define BIT6 1<<6
|
||||
#define BIT7 1<<7
|
||||
#define BIT8 1<<8
|
||||
#define BIT9 1<<9
|
||||
#define BIT10 1<<10
|
||||
#define BIT11 1<<11
|
||||
#define BIT12 1<<12
|
||||
#define BIT13 1<<13
|
||||
#define BIT14 1<<14
|
||||
#define BIT15 1<<15
|
||||
#define BIT16 1<<16
|
||||
#define BIT17 1<<17
|
||||
#define BIT18 1<<18
|
||||
#define BIT19 1<<19
|
||||
#define BIT20 1<<20
|
||||
#define BIT21 1<<21
|
||||
#define BIT22 1<<22
|
||||
#define BIT23 1<<23
|
||||
#define BIT24 1<<24
|
||||
#define BIT25 1<<25
|
||||
#define BIT26 1<<26
|
||||
#define BIT27 1<<27
|
||||
#define BIT28 1<<28
|
||||
#define BIT29 1<<29
|
||||
#define BIT30 1<<30
|
||||
#define BIT31 1<<31
|
||||
|
||||
// CRI_CCR0 Register definitions
|
||||
#define CLK_2M_MODE_ENABLE BIT6
|
||||
#define ACL_CLK_MODE_ENABLE BIT4
|
||||
#define FDF_CLK_MODE_ENABLE BIT2
|
||||
#define STM_CLK_MODE_ENABLE BIT0
|
||||
|
||||
// CRI_RST Register definitions
|
||||
#define FDF_SRST BIT3
|
||||
#define MTE_SRST BIT2
|
||||
#define FCI_SRST BIT1
|
||||
#define AAI_SRST BIT0
|
||||
|
||||
// MEI_TO_ARC_INTERRUPT Register definitions
|
||||
#define MEI_TO_ARC_INT1 BIT3
|
||||
#define MEI_TO_ARC_INT0 BIT2
|
||||
#define MEI_TO_ARC_CS_DONE BIT1 //need to check
|
||||
#define MEI_TO_ARC_MSGAV BIT0
|
||||
|
||||
// ARC_TO_MEI_INTERRUPT Register definitions
|
||||
#define ARC_TO_MEI_INT1 BIT8
|
||||
#define ARC_TO_MEI_INT0 BIT7
|
||||
#define ARC_TO_MEI_CS_REQ BIT6
|
||||
#define ARC_TO_MEI_DBG_DONE BIT5
|
||||
#define ARC_TO_MEI_MSGACK BIT4
|
||||
#define ARC_TO_MEI_NO_ACCESS BIT3
|
||||
#define ARC_TO_MEI_CHECK_AAITX BIT2
|
||||
#define ARC_TO_MEI_CHECK_AAIRX BIT1
|
||||
#define ARC_TO_MEI_MSGAV BIT0
|
||||
|
||||
// ARC_TO_MEI_INTERRUPT_MASK Register definitions
|
||||
#define GP_INT1_EN BIT8
|
||||
#define GP_INT0_EN BIT7
|
||||
#define CS_REQ_EN BIT6
|
||||
#define DBG_DONE_EN BIT5
|
||||
#define MSGACK_EN BIT4
|
||||
#define NO_ACC_EN BIT3
|
||||
#define AAITX_EN BIT2
|
||||
#define AAIRX_EN BIT1
|
||||
#define MSGAV_EN BIT0
|
||||
|
||||
#define MEI_SOFT_RESET BIT0
|
||||
|
||||
#define HOST_MSTR BIT0
|
||||
|
||||
#define JTAG_MASTER_MODE 0x0
|
||||
#define MEI_MASTER_MODE HOST_MSTR
|
||||
|
||||
// MEI_DEBUG_DECODE Register definitions
|
||||
#define MEI_DEBUG_DEC_MASK (0x3)
|
||||
#define MEI_DEBUG_DEC_AUX_MASK (0x0)
|
||||
#define MEI_DEBUG_DEC_DMP1_MASK (0x1)
|
||||
#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
|
||||
#define MEI_DEBUG_DEC_CORE_MASK (0x3)
|
||||
|
||||
#define AUX_STATUS (0x0)
|
||||
// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
|
||||
// page swap requests.
|
||||
#define MEI_TO_ARC_MAILBOX (0xDFD0)
|
||||
#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
|
||||
|
||||
#define ARC_TO_MEI_MAILBOX (0xDFA0)
|
||||
#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
|
||||
|
||||
// Codeswap request messages are indicated by setting BIT31
|
||||
#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
|
||||
|
||||
// Clear Eoc messages received are indicated by setting BIT17
|
||||
#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
|
||||
|
||||
/*
|
||||
** Swap page header
|
||||
*/
|
||||
// Page must be loaded at boot time if size field has BIT31 set
|
||||
#define BOOT_FLAG (BIT31)
|
||||
#define BOOT_FLAG_MASK ~BOOT_FLAG
|
||||
|
||||
#define FREE_RELOAD 1
|
||||
#define FREE_SHOWTIME 2
|
||||
#define FREE_ALL 3
|
||||
|
||||
// marcos
|
||||
#define IFXMIPS_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data);} while (0)
|
||||
#define IFXMIPS_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
|
||||
#define SET_BIT(reg, mask) reg |= (mask)
|
||||
#define CLEAR_BIT(reg, mask) reg &= (~mask)
|
||||
#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
|
||||
#define SET_BITS(reg, mask) SET_BIT(reg, mask)
|
||||
#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
|
||||
|
||||
#define ALIGN_SIZE ( 1L<<10 ) //1K size align
|
||||
#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
|
||||
|
||||
// swap marco
|
||||
#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
|
||||
#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
|
||||
|
||||
// Swap page header describes size in 32-bit words, load location, and image offset
|
||||
// for program and/or data segments
|
||||
typedef struct _arc_swp_page_hdr {
|
||||
u32 p_offset; //Offset bytes of progseg from beginning of image
|
||||
u32 p_dest; //Destination addr of progseg on processor
|
||||
u32 p_size; //Size in 32-bitwords of program segment
|
||||
u32 d_offset; //Offset bytes of dataseg from beginning of image
|
||||
u32 d_dest; //Destination addr of dataseg on processor
|
||||
u32 d_size; //Size in 32-bitwords of data segment
|
||||
} ARC_SWP_PAGE_HDR;
|
||||
|
||||
/*
|
||||
** Swap image header
|
||||
*/
|
||||
#define GET_PROG 0 // Flag used for program mem segment
|
||||
#define GET_DATA 1 // Flag used for data mem segment
|
||||
|
||||
// Image header contains size of image, checksum for image, and count of
|
||||
// page headers. Following that are 'count' page headers followed by
|
||||
// the code and/or data segments to be loaded
|
||||
typedef struct _arc_img_hdr {
|
||||
u32 size; // Size of binary image in bytes
|
||||
u32 checksum; // Checksum for image
|
||||
u32 count; // Count of swp pages in image
|
||||
ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
|
||||
} ARC_IMG_HDR;
|
||||
|
||||
typedef struct smmu_mem_info {
|
||||
int type;
|
||||
unsigned long nCopy;
|
||||
unsigned long size;
|
||||
unsigned char *address;
|
||||
unsigned char *org_address;
|
||||
} smmu_mem_info_t;
|
||||
|
||||
typedef struct ifxmips_mei_device_private {
|
||||
int modem_ready;
|
||||
int arcmsgav;
|
||||
int cmv_reply;
|
||||
int cmv_waiting;
|
||||
// Mei to ARC CMV count, reply count, ARC Indicator count
|
||||
int indicator_count;
|
||||
int cmv_count;
|
||||
int reply_count;
|
||||
unsigned long image_size;
|
||||
int nBar;
|
||||
u16 Recent_indicator[MSG_LENGTH];
|
||||
|
||||
u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
|
||||
|
||||
smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
|
||||
ARC_IMG_HDR *img_hdr;
|
||||
// to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
|
||||
wait_queue_head_t wait_queue_arcmsgav;
|
||||
wait_queue_head_t wait_queue_modemready;
|
||||
MEI_mutex_t mei_cmv_sema;
|
||||
} ifxmips_mei_device_private_t;
|
||||
|
||||
#endif //_IFXMIPS_MEI_BSP_H_
|
||||
@ -1,734 +0,0 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_mei_ioctl.h
|
||||
** PROJECT : Danube
|
||||
** MODULES : MEI
|
||||
**
|
||||
** DATE : 1 Jan 2006
|
||||
** AUTHOR : TC Chen
|
||||
** DESCRIPTION : MEI Driver
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Version $Date $Author $Comment
|
||||
*******************************************************************************/
|
||||
#ifndef _IFXMIPS_MEI_IOCTL_H
|
||||
#define _IFXMIPS_MEI_IOCTL_H
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
#define PCM_BUFF_SIZE 1024 //bytes
|
||||
// interrupt numbers
|
||||
|
||||
#if !(defined(_IFXMIPS_ADSL_APP) || defined (_AMAZON_ADSL_APP))
|
||||
|
||||
// Number of intervals
|
||||
#define INTERVAL_NUM 192 //two days
|
||||
typedef struct ifxmips_mei_mib {
|
||||
struct list_head list;
|
||||
struct timeval start_time; //start of current interval
|
||||
|
||||
int AtucPerfLof;
|
||||
int AtucPerfLos;
|
||||
int AtucPerfEs;
|
||||
int AtucPerfInit;
|
||||
|
||||
int AturPerfLof;
|
||||
int AturPerfLos;
|
||||
int AturPerfLpr;
|
||||
int AturPerfEs;
|
||||
|
||||
int AturChanPerfRxBlk;
|
||||
int AturChanPerfTxBlk;
|
||||
int AturChanPerfCorrBlk;
|
||||
int AturChanPerfUncorrBlk;
|
||||
|
||||
//RFC-3440
|
||||
int AtucPerfStatFastR;
|
||||
int AtucPerfStatFailedFastR;
|
||||
int AtucPerfStatSesL;
|
||||
int AtucPerfStatUasL;
|
||||
int AturPerfStatSesL;
|
||||
int AturPerfStatUasL;
|
||||
} ifxmips_mei_mib;
|
||||
|
||||
typedef struct adslChanPrevTxRate {
|
||||
u32 adslAtucChanPrevTxRate;
|
||||
u32 adslAturChanPrevTxRate;
|
||||
} adslChanPrevTxRate;
|
||||
|
||||
typedef struct adslPhysCurrStatus {
|
||||
u32 adslAtucCurrStatus;
|
||||
u32 adslAturCurrStatus;
|
||||
} adslPhysCurrStatus;
|
||||
|
||||
typedef struct ChanType {
|
||||
int interleave;
|
||||
int fast;
|
||||
int bearchannel0;
|
||||
int bearchannel1;
|
||||
} ChanType;
|
||||
|
||||
typedef struct mib_previous_read {
|
||||
u16 ATUC_PERF_ESS;
|
||||
u16 ATUR_PERF_ESS;
|
||||
u32 ATUR_CHAN_RECV_BLK;
|
||||
u16 ATUR_CHAN_CORR_BLK_INTL;
|
||||
u16 ATUR_CHAN_CORR_BLK_FAST;
|
||||
u16 ATUR_CHAN_UNCORR_BLK_INTL;
|
||||
u16 ATUR_CHAN_UNCORR_BLK_FAST;
|
||||
u16 ATUC_PERF_STAT_FASTR;
|
||||
u16 ATUC_PERF_STAT_FAILED_FASTR;
|
||||
u16 ATUC_PERF_STAT_SESL;
|
||||
u16 ATUC_PERF_STAT_UASL;
|
||||
u16 ATUR_PERF_STAT_SESL;
|
||||
} mib_previous_read;
|
||||
|
||||
typedef struct mib_flags_pretime {
|
||||
struct timeval ATUC_PERF_LOSS_PTIME;
|
||||
struct timeval ATUC_PERF_LOFS_PTIME;
|
||||
struct timeval ATUR_PERF_LOSS_PTIME;
|
||||
struct timeval ATUR_PERF_LOFS_PTIME;
|
||||
struct timeval ATUR_PERF_LPR_PTIME;
|
||||
} mib_flags_pretime;
|
||||
|
||||
// cmv message structures
|
||||
#define MP_PAYLOAD_SIZE 12
|
||||
typedef struct mpmessage {
|
||||
u16 iFunction;
|
||||
u16 iGroup;
|
||||
u16 iAddress;
|
||||
u16 iIndex;
|
||||
u16 iPayload[MP_PAYLOAD_SIZE];
|
||||
} MPMessage;
|
||||
#endif
|
||||
|
||||
typedef struct meireg {
|
||||
u32 iAddress;
|
||||
u32 iData;
|
||||
} meireg;
|
||||
|
||||
#define MEIDEBUG_BUFFER_SIZES 50
|
||||
typedef struct meidebug {
|
||||
u32 iAddress;
|
||||
u32 iCount;
|
||||
u32 buffer[MEIDEBUG_BUFFER_SIZES];
|
||||
} meidebug;
|
||||
|
||||
//==============================================================================
|
||||
// Group definitions
|
||||
//==============================================================================
|
||||
#define OPTN 5
|
||||
#define CNFG 8
|
||||
#define CNTL 1
|
||||
#define STAT 2
|
||||
#define RATE 6
|
||||
#define PLAM 7
|
||||
#define INFO 3
|
||||
#define TEST 4
|
||||
//==============================================================================
|
||||
// Opcode definitions
|
||||
//==============================================================================
|
||||
#define H2D_CMV_READ 0x00
|
||||
#define H2D_CMV_WRITE 0x04
|
||||
#define H2D_CMV_INDICATE_REPLY 0x10
|
||||
#define H2D_ERROR_OPCODE_UNKNOWN 0x20
|
||||
#define H2D_ERROR_CMV_UNKNOWN 0x30
|
||||
|
||||
#define D2H_CMV_READ_REPLY 0x01
|
||||
#define D2H_CMV_WRITE_REPLY 0x05
|
||||
#define D2H_CMV_INDICATE 0x11
|
||||
#define D2H_ERROR_OPCODE_UNKNOWN 0x21
|
||||
#define D2H_ERROR_CMV_UNKNOWN 0x31
|
||||
#define D2H_ERROR_CMV_READ_NOT_AVAILABLE 0x41
|
||||
#define D2H_ERROR_CMV_WRITE_ONLY 0x51
|
||||
#define D2H_ERROR_CMV_READ_ONLY 0x61
|
||||
|
||||
#define H2D_DEBUG_READ_DM 0x02
|
||||
#define H2D_DEBUG_READ_PM 0x06
|
||||
#define H2D_DEBUG_WRITE_DM 0x0a
|
||||
#define H2D_DEBUG_WRITE_PM 0x0e
|
||||
|
||||
#define D2H_DEBUG_READ_DM_REPLY 0x03
|
||||
#define D2H_DEBUG_READ_FM_REPLY 0x07
|
||||
#define D2H_DEBUG_WRITE_DM_REPLY 0x0b
|
||||
#define D2H_DEBUG_WRITE_FM_REPLY 0x0f
|
||||
#define D2H_ERROR_ADDR_UNKNOWN 0x33
|
||||
|
||||
#define D2H_AUTONOMOUS_MODEM_READY_MSG 0xf1
|
||||
//==============================================================================
|
||||
// INFO register address field definitions
|
||||
//==============================================================================
|
||||
|
||||
#define INFO_TxState 0
|
||||
#define INFO_RxState 1
|
||||
#define INFO_TxNextState 2
|
||||
#define INFO_RxNextState 3
|
||||
#define INFO_TxStateJumpFrom 4
|
||||
#define INFO_RxStateJumpFrom 5
|
||||
|
||||
#define INFO_ReverbSnrBuf 8
|
||||
#define INFO_ReverbEchoSnrBuf 9
|
||||
#define INFO_MedleySnrBuf 10
|
||||
#define INFO_RxShowtimeSnrBuf 11
|
||||
#define INFO_DECdelay 12
|
||||
#define INFO_DECExponent 13
|
||||
#define INFO_DECTaps 14
|
||||
#define INFO_AECdelay 15
|
||||
#define INFO_AECExponent 16
|
||||
#define INFO_AECTaps 17
|
||||
#define INFO_TDQExponent 18
|
||||
#define INFO_TDQTaps 19
|
||||
#define INFO_FDQExponent 20
|
||||
#define INFO_FDQTaps 21
|
||||
#define INFO_USBat 22
|
||||
#define INFO_DSBat 23
|
||||
#define INFO_USFineGains 24
|
||||
#define INFO_DSFineGains 25
|
||||
#define INFO_BitloadFirstChannel 26
|
||||
#define INFO_BitloadLastChannel 27
|
||||
#define INFO_PollEOCData 28 // CO specific
|
||||
#define INFO_CSNRMargin 29 // CO specific
|
||||
#define INFO_RCMsgs1 30
|
||||
#define INFO_RMsgs1 31
|
||||
#define INFO_RMsgRA 32
|
||||
#define INFO_RCMsgRA 33
|
||||
#define INFO_RMsg2 34
|
||||
#define INFO_RCMsg2 35
|
||||
#define INFO_BitLoadOK 36
|
||||
#define INFO_RCRates1 37
|
||||
#define INFO_RRates1Tab 38
|
||||
#define INFO_RMsgs1Tab 39
|
||||
#define INFO_RMsgRATab 40
|
||||
#define INFO_RRatesRA 41
|
||||
#define INFO_RCRatesRA 42
|
||||
#define INFO_RRates2 43
|
||||
#define INFO_RCRates2 44
|
||||
#define INFO_PackedRMsg2 45
|
||||
#define INFO_RxBitSwapFlag 46
|
||||
#define INFO_TxBitSwapFlag 47
|
||||
#define INFO_ShowtimeSNRUpdateCount 48
|
||||
#define INFO_ShowtimeFDQUpdateCount 49
|
||||
#define INFO_ShowtimeDECUpdateCount 50
|
||||
#define INFO_CopyRxBuffer 51
|
||||
#define INFO_RxToneBuf 52
|
||||
#define INFO_TxToneBuf 53
|
||||
#define INFO_Version 54
|
||||
#define INFO_TimeStamp 55
|
||||
#define INFO_feVendorID 56
|
||||
#define INFO_feSerialNum 57
|
||||
#define INFO_feVersionNum 58
|
||||
#define INFO_BulkMemory 59 //Points to start of bulk memory
|
||||
#define INFO_neVendorID 60
|
||||
#define INFO_neVersionNum 61
|
||||
#define INFO_neSerialNum 62
|
||||
|
||||
//==============================================================================
|
||||
// RATE register address field definitions
|
||||
//==============================================================================
|
||||
|
||||
#define RATE_UsRate 0
|
||||
#define RATE_DsRate 1
|
||||
|
||||
//==============================================================================
|
||||
// PLAM (Physical Layer Management) register address field definitions
|
||||
// (See G997.1 for reference)
|
||||
//==============================================================================
|
||||
|
||||
// ///
|
||||
// Failure Flags ///
|
||||
// ///
|
||||
|
||||
#define PLAM_NearEndFailureFlags 0
|
||||
#define PLAM_FarEndFailureFlags 1
|
||||
|
||||
// ///
|
||||
// Near End Failure Flags Bit Definitions ///
|
||||
// ///
|
||||
|
||||
// ADSL Failures ///
|
||||
#define PLAM_LOS_FailureBit 0x0001
|
||||
#define PLAM_LOF_FailureBit 0x0002
|
||||
#define PLAM_LPR_FailureBit 0x0004
|
||||
#define PLAM_RFI_FailureBit 0x0008
|
||||
|
||||
// ATM Failures ///
|
||||
#define PLAM_NCD_LP0_FailureBit 0x0010
|
||||
#define PLAM_NCD_LP1_FailureBit 0x0020
|
||||
#define PLAM_LCD_LP0_FailureBit 0x0040
|
||||
#define PLAM_LCD_LP1_FailureBit 0x0080
|
||||
|
||||
#define PLAM_NCD_BC0_FailureBit 0x0100
|
||||
#define PLAM_NCD_BC1_FailureBit 0x0200
|
||||
#define PLAM_LCD_BC0_FailureBit 0x0400
|
||||
#define PLAM_LCD_BC1_FailureBit 0x0800
|
||||
// ///
|
||||
// Performance Counts ///
|
||||
// ///
|
||||
|
||||
#define PLAM_NearEndCrcCnt 2
|
||||
#define PLAM_CorrectedRSErrors 3
|
||||
|
||||
#define PLAM_NearEndECSCnt 6
|
||||
#define PLAM_NearEndESCnt 7
|
||||
#define PLAM_NearEndSESCnt 8
|
||||
#define PLAM_NearEndLOSSCnt 9
|
||||
#define PLAM_NearEndUASLCnt 10
|
||||
|
||||
#define PLAM_NearEndHECErrCnt 11
|
||||
|
||||
#define PLAM_NearEndHECTotCnt 16
|
||||
#define PLAM_NearEndCellTotCnt 18
|
||||
#define PLAM_NearEndSfCntLSW 20
|
||||
#define PLAM_NearEndSfCntMSW 21
|
||||
|
||||
#define PLAM_FarEndFebeCnt 24
|
||||
|
||||
#define PLAM_FarEndFecCnt 28
|
||||
|
||||
#define PLAM_FarEndFECSCnt 32
|
||||
#define PLAM_FarEndESCnt 33
|
||||
#define PLAM_FarEndSESCnt 34
|
||||
#define PLAM_FarEndLOSSCnt 35
|
||||
#define PLAM_FarEndUASLCnt 36
|
||||
|
||||
#define PLAM_FarEndHECErrCnt 37
|
||||
|
||||
#define PLAM_FarEndHECTotCnt 41
|
||||
|
||||
#define PLAM_FarEndCellTotCnt 43
|
||||
|
||||
#define PLAM_SNRMargin_0_1db 45
|
||||
|
||||
#define PLAM_SNRMargin 46
|
||||
|
||||
//==============================================================================
|
||||
// CNTL register address and bit field definitions
|
||||
//==============================================================================
|
||||
|
||||
#define CNTL_ModemControl 0
|
||||
|
||||
#define CNTL_ModemReset 0x0
|
||||
#define CNTL_ModemStart 0x2
|
||||
|
||||
//==============================================================================
|
||||
// STAT register address and bit field definitions
|
||||
//==============================================================================
|
||||
|
||||
#define STAT_MacroState 0
|
||||
#define STAT_Mode 1
|
||||
#define STAT_DMTFramingMode 2
|
||||
#define STAT_SleepState 3
|
||||
#define STAT_Misc 4
|
||||
#define STAT_FailureState 5
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// STAT_OLRStatus provides status of OLR
|
||||
//16-bit STAT_OLRStatus_DS
|
||||
// [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
|
||||
// [3:2]: Reserved
|
||||
// [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA)
|
||||
// [7:6]: Reserved
|
||||
// [10:8]: >0=Request. 0=not. For DS, # of request transmissions/retransmissions (3 bits).
|
||||
// [11]: 1=Receive Response, 0=not
|
||||
// [15:12]: Reserved
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
///
|
||||
#define STAT_OLRStatus_DS 6
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// STAT_OLRStatus provides status of OLR
|
||||
// 16-bit STAT_OLRStatus_US CMV
|
||||
// [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
|
||||
// [3:2]: Reserved
|
||||
// [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA)
|
||||
// [7:6]: Reserved
|
||||
// [8]: 1=Request Received. 0=not.
|
||||
// [10:9]: Reserved
|
||||
// [11]: 1=Response Sent, 0=not
|
||||
// [15:12]: Reserved
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
///
|
||||
#define STAT_OLRStatus_US 7
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// STAT_PMStatus provides status of PM
|
||||
// 16-bit STAT_PMStatus CMV
|
||||
// [1:0] : PM Status 00=IDLE, 01=PM_IN_PROGRESS, 10=PM_Completed, 11=PM_Aborted
|
||||
// [2] : 0=ATU_R initiated PM; 1 = ATU_C initiated PM
|
||||
// [3]: Reserved
|
||||
// [5:4]: PM_Type (1:Simple Request; 2: L2 request; 3: L2 trim)
|
||||
// [7:6]: Reserved
|
||||
// [10:8]: >0=Request. 0=not. # of request transmissions/retransmissions (3 bits).
|
||||
// [11]: 1=Response, 0=not
|
||||
// [15:12]: Reserved
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
///
|
||||
#define STAT_PMStatus 8
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// 16-bit STAT_OLRError_DS, STAT_OLRError_US, STAT_PMError
|
||||
// [3:0]: OLR/PM response reason code
|
||||
// [7:4]: OLR/PM Internal error code
|
||||
// [15:8]: OLR/PM Reserved for future
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
///
|
||||
#define STAT_OLRError_DS 9
|
||||
#define STAT_OLRError_US 10
|
||||
#define STAT_PMError 11
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// STAT_MacroState
|
||||
// MacroState reflects the high level state of the modem
|
||||
|
||||
#define STAT_InitState 0x0000
|
||||
#define STAT_ReadyState 0x0001
|
||||
#define STAT_FailState 0x0002
|
||||
#define STAT_IdleState 0x0003
|
||||
#define STAT_QuietState 0x0004
|
||||
#define STAT_GhsState 0x0005
|
||||
#define STAT_FullInitState 0x0006
|
||||
#define STAT_ShowTimeState 0x0007
|
||||
#define STAT_FastRetrainState 0x0008
|
||||
#define STAT_LoopDiagMode 0x0009
|
||||
#define STAT_ShortInit 0x000A // Bis short initialization ///
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// STAT_Mode
|
||||
// ConfigurationMode indicates the mode of the current ADSL Link. In general, a modem may use
|
||||
// G.Hs or some other mechanism to negotiate the specific mode of operation.
|
||||
// The OPTN_modeControl CMV is used to select a set of desired modes.
|
||||
// The STAT_Mode CMV indicates which mode was actually selected.
|
||||
|
||||
#define STAT_ConfigMode_T1413 0x0001
|
||||
#define STAT_ConfigMode_G992_2_AB 0x0002
|
||||
#define STAT_ConfigMode_G992_1_A 0x0004
|
||||
#define STAT_ConfigMode_G992_1_B 0x0008
|
||||
#define STAT_ConfigMode_G992_1_C 0x0010
|
||||
#define STAT_ConfigMode_G992_2_C 0x0020
|
||||
|
||||
#define STAT_ConfigMode_G992_3_A 0x0100
|
||||
#define STAT_ConfigMode_G992_3_B 0x0200
|
||||
#define STAT_ConfigMode_G992_3_I 0x0400
|
||||
#define STAT_ConfigMode_G992_3_J 0x0800
|
||||
#define STAT_ConfigMode_G992_3_L 0x1000
|
||||
|
||||
#define STAT_ConfigMode_G992_4_A 0x2000
|
||||
#define STAT_ConfigMode_G992_4_I 0x4000
|
||||
|
||||
#define STAT_ConfigMode_G992_5 0x8000
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// STAT_DMTFramingMode
|
||||
// FramingMode indicates the DMT framing mde negotiated during initialization. The framing mode
|
||||
// status is not applicable in BIS mode and its value is undefined
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define STAT_FramingModeMask 0x0003
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// STAT_Misc
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define STAT_OverlappedSpectrum 0x0008
|
||||
#define STAT_TCM 0x0010
|
||||
#define STAT_TDQ_at_1104 0x0020
|
||||
#define STAT_T1413_Signal_Detected 0x0040
|
||||
#define STAT_AnnexL_US_Mask1_PSD 0x1000 //indicate we actually selected G992.3 AnnexL US PSD mask1
|
||||
#define STAT_AnnexL_US_Mask2_PSD 0x2000 //indicate we actually selected G992.3 AnnexL US PSD mask2
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// STAT_FailureState
|
||||
// when the MacroSTate indicates the fail state, FailureState provides a failure code
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define E_CODE_NO_ERROR 0
|
||||
#define E_CODE_BAT_TX 1 // TX BAT table is incorrect */
|
||||
#define E_CODE_BAT_RX 2 // RX BAT table is incorrect */
|
||||
#define E_CODE_PROFILE 3 // profile is not selected in fast retrain */
|
||||
#define E_CODE_TX_AOC_FIFO_OVERFLOW 4
|
||||
#define E_CODE_TRUNCATE_FR 5 //Fast Retrain truncated due to no stored profiles*/
|
||||
#define E_CODE_BITLOAD 6 // bit loading fails */
|
||||
#define E_CODE_ST_ERROR 7 // showtime CRC error */
|
||||
#define E_CODE_RESERVED 8 // using parameters reserved by the ITU-T */
|
||||
#define E_CODE_C_TONES 9 // detected C_TONES */
|
||||
#define E_CODE_CODESWAP_ERR 10 // codeswap not finished in time */
|
||||
#define E_CODE_FIFO_OVERFLOW 11 // we have run out of fifo space */
|
||||
#define E_CODE_C_BG_DECODE_ERR 12 // error in decoding C-BG message */
|
||||
#define E_CODE_C_RATES2_DECODE_ERR 13 // error in decoding C-MSGS2 and C-RATES2 */
|
||||
#define E_CODE_RCMedleyRx_C_SEGUE2_Failure 14 // Timeout after RCMedleyRx waiting for C_SEGUE2 */
|
||||
#define E_CODE_RReverbRATx_C_SEGUE2_Failure 15 // Timeout after RReverbRATx waiting for C_SEGUE2 */
|
||||
#define E_CODE_RReverb3Tx_C_SEGUE1_Failure 16 // Timeout after RReverb3Tx waiting for C_SEGUE1 */
|
||||
#define E_CODE_RCCRC2Rx_C_RATES1_DECOD_ERR 17 // Received CRC not equal to computed CRC */
|
||||
#define E_CODE_RCCRC1Rx_C_RATES1_DECOD_ERR 18 // Received CRC not equal to computed CRC */
|
||||
#define E_CODE_RReverb5Tx_C_SEGUE2_Failure 19 // Timeout after RReverb5Tx waiting for C_SEGUE2 */
|
||||
#define E_CODE_RReverb6Tx_C_SEGUE3_Failure 20 // Timeout after RReverb6Tx waiting for C_SEGUE3 */
|
||||
#define E_CODE_RSegue5Tx_C_SEGUE3_Failure 21 // Timeout after RSegue5Tx waiting for C_SEGUE3 */
|
||||
#define E_CODE_RCReverb5Rx_C_SEGUE_Failure 22 // Timeout after RCReverb5Rx waiting for C_SEGUE */
|
||||
#define E_CODE_RCReverbRARx_C_SEGUE2_Failure 23 // Timeout after RCReverbRARx waiting for C_SEGUE2 */
|
||||
#define E_CODE_RCCRC4Rx_CMSGS2_DECOD_ERR 24 // Received CRC not equal to computed CRC */
|
||||
#define E_CODE_RCCRC5Rx_C_BG_DECOD_ERR 25 // Received CRC not equal to computed CRC */
|
||||
#define E_CODE_RCCRC3Rx_DECOD_ERR 26 // Received CRC not equal to computed CRC */
|
||||
#define E_CODE_RCPilot3_DEC_PATH_DEL_TIMEOUT 27 // DEC Path Delay timeout */
|
||||
#define E_CODE_RCPilot3_DEC_TRAINING_TIMEOUT 28 // DEC Training timeout */
|
||||
#define E_CODE_RCReverb3Rx_C_SEGUE1_Failure 29 // Timeout after RCReverb3Rx waiting for C_SEGUE1 */
|
||||
#define E_CODE_RCReverb2Rx_SignalEnd_Failure 30 // Timeout waiting for the end of RCReverb2Rx signal */
|
||||
#define E_CODE_RQuiet2_SignalEnd_Failure 31 // Timeout waiting for the end of RQuiet2 signal */
|
||||
#define E_CODE_RCReverbFR1Rx_Failure 32 // Timeout waiting for the end of RCReverbFR1Rx signal */
|
||||
#define E_CODE_RCPilotFR1Rx_SignalEnd_Failure 33 // Timeout waiting for the end of RCPilotFR1Rx signal */
|
||||
#define E_CODE_RCReverbFR2Rx_C_Segue_Failure 34 // Timeout after RCReverbFR2Rx waiting for C_SEGUE */
|
||||
#define E_CODE_RCReverbFR5Rx_SignalEnd_TIMEOUT 35 // Timeout waiting for the end of RCReverbFR5Rx signal */
|
||||
#define E_CODE_RCReverbFR6Rx_C_SEGUE_Failure 36 // Timeout after RCReverbFR6Rx waiting for C_SEGUE */
|
||||
#define E_CODE_RCReverbFR8Rx_C_SEGUE_FR4_Failure 37 // Timeout after RCReverbFR8Rx waiting for C_SEGUE_FR4 */
|
||||
#define E_CODE_RCReverbFR8Rx_No_PROFILE 38 // Timeout since no profile was selected */
|
||||
#define E_CODE_RCReverbFR8Rx_SignalEnd_TIMEOUT 39 // Timeout waiting for the end of RCReverbFR8Rx signal */
|
||||
#define E_CODE_RCCRCFR1_DECOD_ERR 40 // Received CRC not equal to computed CRC */
|
||||
#define E_CODE_RCRecovRx_SingnalEnd_TIMEOUT 41 // Timeout waiting for the end of RCRecovRx signal */
|
||||
#define E_CODE_RSegueFR5Tx_TX_Not_Ready_TIMEOUT 42 // Timeout after RSegueFR5Tx waiting for C_SEGUE2 */
|
||||
#define E_CODE_RRecovTx_SignalEnd_TIMEOUT 43 // Timeout waiting for the end of RRecovTx signal */
|
||||
#define E_CODE_RCMedleyFRRx_C_SEGUE2_Failure 44 // Timeout after RCMedleyFRRx waiting for C_SEGUE2 */
|
||||
#define E_CODE_CONFIGURATION_PARAMETERS_ERROR 45 // one of the configuration parameters do not meet the standard */
|
||||
#define E_CODE_BAD_MEM_ACCESS 46
|
||||
#define E_CODE_BAD_INSTRUCTION_ACCESS 47
|
||||
#define E_CODE_TX_EOC_FIFO_OVERFLOW 48
|
||||
#define E_CODE_RX_EOC_FIFO_OVERFLOW 49
|
||||
#define E_CODE_GHS_CD_FLAG_TIME_OUT 50 // Timeout when transmitting Flag in handshake cleardown */
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//STAT_OLRStatus:
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define STAT_OLRPM_IDLE 0x0000
|
||||
#define STAT_OLRPM_IN_PROGRESS 0x0001
|
||||
#define STAT_OLRPM_COMPLETE 0x0002
|
||||
#define STAT_OLRPM_ABORTED 0x0003
|
||||
#define STAT_OLRPM_RESPONSE 0x0800
|
||||
|
||||
#define STAT_OLR_BITSWAP 0x0010
|
||||
#define STAT_OLR_DRR 0x0020
|
||||
#define STAT_OLR_SRA 0x0030
|
||||
|
||||
//STAT_PMStatus_US:
|
||||
#define STAT_PM_CO_REQ 0x0004
|
||||
#define STAT_PM_SIMPLE_REQ 0x0010
|
||||
#define STAT_PM_L2_REQ 0x0020
|
||||
#define STAT_PM_L2_TRIM_REQ 0x0030
|
||||
|
||||
// STAT_OLRError_DS, STAT_OLRError_US
|
||||
//4 bit response reason code:
|
||||
#define RESP_BUSY 0x01
|
||||
#define RESP_INVALID_PARAMETERS 0x02
|
||||
#define RESP_NOT_ENABLED 0x03
|
||||
#define RESP_NOT_SUPPORTED 0x04
|
||||
|
||||
//4 bit internal error code (common for OLR and PM)
|
||||
#define REQ_INVALID_BiGi 0x10
|
||||
#define REQ_INVALID_Lp 0x20
|
||||
#define REQ_INVALID_Bpn 0x30
|
||||
#define REQ_INVALID_FRAMING_CONSTRAINT 0x40
|
||||
#define REQ_NOT_IN_L0_STATE 0x50
|
||||
#define REQ_NOT_IN_L2_STATE 0x60
|
||||
#define REQ_INVALID_PCB 0x70
|
||||
#define REQ_VIOLATES_MARGIN 0x80
|
||||
|
||||
//STAT_PMError
|
||||
//4 bit response reason code:
|
||||
#define RESP_STATE_NOT_DESIRED 0x03
|
||||
#define RESP_INFEASIBLE_PARAMETERS 0x04
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// OPTN register address and bit field definitions
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define OPTN_ModeControl 0
|
||||
#define OPTN_DMTLnkCtl 1
|
||||
// Reserved 2
|
||||
#define OPTN_GhsControl 3
|
||||
// Reserved 4
|
||||
#define OPTN_PwrManControl 5
|
||||
#define OPTN_AnnexControl 6
|
||||
#define OPTN_ModeControl1 7
|
||||
// Reserved 8
|
||||
#define OPTN_StateMachineCtrl 9
|
||||
// Reserved 10
|
||||
// Reserved 11
|
||||
#define OPTN_BisLinkControl 12
|
||||
#define OPTN_ATMAddrConfig 13
|
||||
#define OPTN_ATMNumCellConfig 14
|
||||
|
||||
// Mode control defines the allowable operating modes of an ADSL link. In general, a modem may ///
|
||||
// use G.Hs or some other mechanism to negotiate the specific mode of operation. ///
|
||||
// The OPTN_ModeControl CMV is used to select a set of desired modes ///
|
||||
// The STAT_ModeControl CMV indicates which mode was actually selected ///
|
||||
|
||||
// OPTN_ModeControl
|
||||
#define OPTN_ConfigMode_T1413 0x0001
|
||||
#define OPTN_ConfigMode_G992_2_AB 0x0002
|
||||
#define OPTN_ConfigMode_G992_1_A 0x0004
|
||||
#define OPTN_ConfigMode_G992_1_B 0x0008
|
||||
#define OPTN_ConfigMode_G992_1_C 0x0010
|
||||
#define OPTN_ConfigMode_G992_2_C 0x0020
|
||||
|
||||
#define OPTN_ConfigMode_G992_3_A 0x0100
|
||||
#define OPTN_ConfigMode_G992_3_B 0x0200
|
||||
#define OPTN_ConfigMode_G992_3_I 0x0400
|
||||
#define OPTN_ConfigMode_G992_3_J 0x0800
|
||||
#define OPTN_ConfigMode_G992_3_L 0x1000
|
||||
|
||||
#define OPTN_ConfigMode_G992_4_A 0x2000
|
||||
#define OPTN_ConfigMode_G992_4_I 0x4000
|
||||
|
||||
#define OPTN_ConfigMode_G992_5 0x8000
|
||||
|
||||
// OPTN_PwrManControl
|
||||
#define OPTN_PwrManWakeUpGhs 0x1
|
||||
#define OPTN_PwrManWakeUpFR 0x2
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// OPTN_DMT Link Control
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
#define OPTN_DMT_DualLatency_Dis 0x200
|
||||
#define OPTN_DMT_S_Dis 0x100
|
||||
#define OPTN_DMT_FRAMINGMODE 0x1
|
||||
#define OPTN_DMT_FRAMINGMODE_MASK 0x7
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// OPTN_BIS Link Control
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
#define OPTN_BisLinkContrl_LineProbeDis 0x1
|
||||
#define OPTN_BisLinkContrl_DSBlackBitsEn 0x2
|
||||
#define OPTN_BisLinkContrl_DiagnosticModeEn 0x4
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// OPTN_GhsControl
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// for OPTN_GhsControl, we will assign 16bit word as follows
|
||||
// bit 0~3: set the control over which start(initial) message CPE will send:
|
||||
//
|
||||
// BIT: 2 1 0
|
||||
// 0 0 1 CLR
|
||||
// 0 1 0 MR
|
||||
// 0 1 1 MS
|
||||
// 1 0 0 MP
|
||||
//
|
||||
// // bit 4~6: set the control over which message will be sent when we get at lease one CL/CLR exchange
|
||||
// BIT: 5 4
|
||||
// 0 1 MS
|
||||
// 1 0 MR
|
||||
// 1 1 MP
|
||||
//
|
||||
// // bit 15: RT initiated G.hs sample sessions one through eight. Session one is default.
|
||||
// BIT: 15
|
||||
// 1 means session one
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define OPTN_GHS_ST_GHS 0x8000
|
||||
#define OPTN_GHS_INIT_MASK 0x000F
|
||||
#define OPTN_GHS_RESP_MASK 0x00F0
|
||||
|
||||
#define OPTN_RTInitTxMsg_CLR 0x0001
|
||||
#define OPTN_RTInitTxMsg_MR 0x0002
|
||||
#define OPTN_RTInitTxMsg_MS 0x0003
|
||||
#define OPTN_RTInitTxMsg_MP 0x0004
|
||||
|
||||
#define OPTN_RTRespTxMsg_MS 0x0010
|
||||
#define OPTN_RTRespTxMsg_MR 0x0020
|
||||
#define OPTN_RTRespTxMsg_MP 0x0030
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// OPTN_AnnexControl
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// G.992.3 Annex A/L1/L2 US PSD Mask preferred
|
||||
|
||||
#define OPTN_G992_3_AnnexA_PreferredModeMask 0x3000
|
||||
#define OPTN_G992_3_AnnexA_PreferredModeA 0x0000 // default AnnexA PSD mask ///
|
||||
#define OPTN_G992_3_AnnexA_PreferredModeL1 0x1000 // AnnexL wide spectrum upstream PSD mask ///
|
||||
#define OPTN_G992_3_AnnexA_PreferredModeL2 0x2000 // AnnexL narrow spectrum upstream PSD mask ///
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//OPTN_ATMAddrConfig
|
||||
// Bits 4:0 are Utopia address for BC1
|
||||
// Bits 9:5 are Utopia address for BC0
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define OPTN_UTPADDR_BC1 0x001F
|
||||
#define OPTN_UTPADDR_BC0 0x03E0
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//OPTN_ATMNumCellConfig
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define OPTN_BC1_NUM_CELL_PAGES 0x000F // Bits 0:3 ///
|
||||
#define OPTN_BC0_NUM_CELL_PAGES 0x00F0 // Bits 4:7 ///
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// CNFG register address field ///
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
///////////////////////////////////////////
|
||||
// these cmvs are used by bis handshake ///
|
||||
///////////////////////////////////////////
|
||||
|
||||
// Each of the CNFG_TPS entries points to a structure of type (TPS_TC_BearerChannel_t)
|
||||
#define CNFG_TPS_TC_DS0 0
|
||||
#define CNFG_TPS_TC_DS1 1
|
||||
#define CNFG_TPS_TC_US0 2
|
||||
#define CNFG_TPS_TC_US1 3
|
||||
|
||||
#define CNFG_HDLC_Overhead_Requirements 4
|
||||
|
||||
// Each of the CNFG_PMS entries points to a structure of type (PMS_TC_LatencyPath_t)
|
||||
#define CNFG_PMS_TC_DS0 5
|
||||
#define CNFG_PMS_TC_DS1 6
|
||||
#define CNFG_PMS_TC_US0 7
|
||||
#define CNFG_PMS_TC_US1 8
|
||||
|
||||
// CNFG_PMD_PARAMETERS points to a structure of type (PMD_params_t)
|
||||
#define CNFG_PMD_PARAMETERS 9
|
||||
|
||||
////////////////////////////////////////////////////////////
|
||||
// these cmvs are used by bis training and showtime code ///
|
||||
////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////
|
||||
// Tx Config ///
|
||||
////////////////
|
||||
#define CNFG_tx_Cnfg_Nbc 10
|
||||
#define CNFG_tx_Cnfg_Nlp 11
|
||||
#define CNFG_tx_Cnfg_Rp 12
|
||||
#define CNFG_tx_Cnfg_Mp 13
|
||||
#define CNFG_tx_Cnfg_Lp 14
|
||||
#define CNFG_tx_Cnfg_Tp 15
|
||||
#define CNFG_tx_Cnfg_Dp 16
|
||||
#define CNFG_tx_Cnfg_Bpn 17
|
||||
#define CNFG_tx_Cnfg_FramingMode 18
|
||||
#define CNFG_tx_Cnfg_MSGLp 19
|
||||
#define CNFG_tx_Cnfg_MSGc 20
|
||||
|
||||
////////////////
|
||||
// Rx Config ///
|
||||
////////////////
|
||||
#define CNFG_rx_Cnfg_Nbc 21
|
||||
#define CNFG_rx_Cnfg_Nlp 22
|
||||
#define CNFG_rx_Cnfg_Rp 23
|
||||
#define CNFG_rx_Cnfg_Mp 24
|
||||
#define CNFG_rx_Cnfg_Lp 25
|
||||
#define CNFG_rx_Cnfg_Tp 26
|
||||
#define CNFG_rx_Cnfg_Dp 27
|
||||
#define CNFG_rx_Cnfg_Bpn 28
|
||||
#define CNFG_rx_Cnfg_FramingMode 29
|
||||
#define CNFG_rx_Cnfg_MSGLp 30
|
||||
#define CNFG_rx_Cnfg_MSGc 31
|
||||
|
||||
#define CNFG_tx_Cnfg_BCnToLPp 32
|
||||
#define CNFG_rx_Cnfg_BCnToLPp 33
|
||||
|
||||
#endif
|
||||
@ -1,112 +0,0 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_mei_linux.h
|
||||
** PROJECT : Danube
|
||||
** MODULES : MEI
|
||||
**
|
||||
** DATE : 1 Jan 2006
|
||||
** AUTHOR : TC Chen
|
||||
** DESCRIPTION : MEI Driver
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Version $Date $Author $Comment
|
||||
*******************************************************************************/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <asm/semaphore.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
#undef CONFIG_DEVFS_FS //165204:henryhsu devfs will make mei open file fail.
|
||||
|
||||
#ifdef CONFIG_DEVFS_FS
|
||||
#include <linux/devfs_fs_kernel.h>
|
||||
#endif
|
||||
#ifdef CONFIG_PROC_FS
|
||||
#include <linux/proc_fs.h>
|
||||
#endif
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <linux/delay.h>
|
||||
#define __LINUX__
|
||||
|
||||
#ifdef CONFIG_PROC_FS
|
||||
#define PROC_ITEMS 8
|
||||
#define MEI_DIRNAME "mei"
|
||||
#endif
|
||||
|
||||
#include <asm/ifxmips/ifxmips.h>
|
||||
#include <asm/ifxmips/ifxmips_irq.h>
|
||||
#include <asm/ifxmips/ifxmips_mei.h>
|
||||
#include <asm/ifxmips/ifxmips_mei_app.h>
|
||||
#include <asm/ifxmips/ifxmips_mei_ioctl.h>
|
||||
#include <asm/ifxmips/ifxmips_mei_app_ioctl.h>
|
||||
#include <asm/ifxmips/ifxmips_gpio.h>
|
||||
#include <asm/ifxmips/ifxmips_led.h>
|
||||
#include <asm/ifxmips/ifxmips_irq.h>
|
||||
|
||||
#ifdef CONFIG_DEVFS_FS
|
||||
#define IFXMIPS_DEVNAME "ifxmips"
|
||||
#endif //ifdef CONFIG_DEVFS_FS
|
||||
|
||||
#define MEI_LOCKINT(var) \
|
||||
local_save_flags(var);\
|
||||
local_irq_disable()
|
||||
#define MEI_UNLOCKINT(var) \
|
||||
local_irq_restore(var)
|
||||
|
||||
#define MEI_MUTEX_INIT(id,flag) \
|
||||
sema_init(&id,flag)
|
||||
#define MEI_MUTEX_LOCK(id) \
|
||||
down_interruptible(&id)
|
||||
#define MEI_MUTEX_UNLOCK(id) \
|
||||
up(&id)
|
||||
|
||||
#define MEI_MASK_AND_ACK_IRQ \
|
||||
ifxmips_mask_and_ack_irq
|
||||
|
||||
#define MEI_DISABLE_IRQ \
|
||||
disable_irq
|
||||
#define MEI_ENABLE_IRQ \
|
||||
enable_irq
|
||||
|
||||
#define MEI_WAIT(ms) \
|
||||
{\
|
||||
set_current_state(TASK_INTERRUPTIBLE);\
|
||||
schedule_timeout(ms);\
|
||||
}
|
||||
|
||||
#define MEI_INIT_WAKELIST(name,queue) \
|
||||
init_waitqueue_head(&queue)
|
||||
|
||||
#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
|
||||
interruptible_sleep_on_timeout(&ev,timeout)
|
||||
|
||||
#define MEI_WAIT_EVENT(ev)\
|
||||
interruptible_sleep_on(&ev)
|
||||
#define MEI_WAKEUP_EVENT(ev)\
|
||||
wake_up_interruptible(&ev)
|
||||
|
||||
typedef unsigned long MEI_intstat_t;
|
||||
typedef struct semaphore MEI_mutex_t;
|
||||
typedef struct file MEI_file_t;
|
||||
typedef struct inode MEI_inode_t;
|
||||
|
||||
extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
|
||||
@ -181,7 +181,6 @@ pcibios_init(void)
|
||||
pci_probe_only = 0;
|
||||
printk("PCI: Probing PCI hardware on host bus 0.\n");
|
||||
ifxmips_pci_startup ();
|
||||
// IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
|
||||
ifxmips_pci_mapped_cfg = (u32)ioremap_nocache(0x17000000, 0x800 * 16);
|
||||
printk("IFXMips PCI mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_mapped_cfg);
|
||||
ifxmips_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
|
||||
|
||||
@ -1,507 +0,0 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* This driver was originally based on the INCA-IP driver, but due to
|
||||
* fundamental conceptual drawbacks there has been changed a lot.
|
||||
*
|
||||
* Based on INCA-IP driver Copyright(c) 2003 Gary Jennejohn <gj@denx.de>
|
||||
* Based on the VxWorks drivers Copyright(c) 2002, Infineon Technologies.
|
||||
*
|
||||
* Copyright(C) 2006 infineon
|
||||
* Copyright(C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
|
||||
#define IFAP_EEPROM_DRV_VERSION "0.0.1"
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/major.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/fcntl.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/version.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/ifxmips/ifxmips.h>
|
||||
#include <asm/ifxmips/ifxmips_irq.h>
|
||||
#include <asm/ifxmips/ifx_ssc_defines.h>
|
||||
#include <asm/ifxmips/ifx_ssc.h>
|
||||
|
||||
/* allow the user to set the major device number */
|
||||
static int ifxmips_eeprom_maj;
|
||||
|
||||
extern int ifx_ssc_init(void);
|
||||
extern int ifx_ssc_open(struct inode *inode, struct file *filp);
|
||||
extern int ifx_ssc_close(struct inode *inode, struct file *filp);
|
||||
extern void ifx_ssc_cleanup_module(void);
|
||||
extern int ifx_ssc_ioctl(struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long data);
|
||||
extern ssize_t ifx_ssc_kwrite(int port, const char *kbuf, size_t len);
|
||||
extern ssize_t ifx_ssc_kread(int port, char *kbuf, size_t len);
|
||||
|
||||
extern int ifx_ssc_cs_low(unsigned int pin);
|
||||
extern int ifx_ssc_cs_high(unsigned int pin);
|
||||
extern int ifx_ssc_txrx(char *tx_buf, unsigned int tx_len, char *rx_buf, unsigned int rx_len);
|
||||
extern int ifx_ssc_tx(char *tx_buf, unsigned int tx_len);
|
||||
extern int ifx_ssc_rx(char *rx_buf, unsigned int rx_len);
|
||||
|
||||
#define EEPROM_CS IFX_SSC_WHBGPOSTAT_OUT0_POS
|
||||
|
||||
/* commands for EEPROM, x25160, x25140 */
|
||||
#define EEPROM_WREN ((unsigned char)0x06)
|
||||
#define EEPROM_WRDI ((unsigned char)0x04)
|
||||
#define EEPROM_RDSR ((unsigned char)0x05)
|
||||
#define EEPROM_WRSR ((unsigned char)0x01)
|
||||
#define EEPROM_READ ((unsigned char)0x03)
|
||||
#define EEPROM_WRITE ((unsigned char)0x02)
|
||||
#define EEPROM_PAGE_SIZE 4
|
||||
#define EEPROM_SIZE 512
|
||||
|
||||
static int eeprom_rdsr(void)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned char cmd = EEPROM_RDSR;
|
||||
unsigned long flag;
|
||||
char status;
|
||||
|
||||
local_irq_save(flag);
|
||||
|
||||
if ((ret = ifx_ssc_cs_low(EEPROM_CS)) == 0)
|
||||
if ((ret = ifx_ssc_txrx(&cmd, 1, &status, 1)) >= 0)
|
||||
ret = status & 1;
|
||||
|
||||
ifx_ssc_cs_high(EEPROM_CS);
|
||||
local_irq_restore(flag);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void eeprom_wip_over(void)
|
||||
{
|
||||
while (eeprom_rdsr())
|
||||
printk(KERN_INFO "waiting for eeprom\n");
|
||||
}
|
||||
|
||||
static int eeprom_wren(void)
|
||||
{
|
||||
unsigned char cmd = EEPROM_WREN;
|
||||
int ret = 0;
|
||||
unsigned long flag;
|
||||
|
||||
local_irq_save(flag);
|
||||
if ((ret = ifx_ssc_cs_low(EEPROM_CS)) == 0)
|
||||
if ((ret = ifx_ssc_tx(&cmd, 1)) >= 0)
|
||||
ret = 0;
|
||||
|
||||
ifx_ssc_cs_high(EEPROM_CS);
|
||||
local_irq_restore(flag);
|
||||
|
||||
if (!ret)
|
||||
eeprom_wip_over();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int eeprom_wrsr(void)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned char cmd[2];
|
||||
unsigned long flag;
|
||||
|
||||
cmd[0] = EEPROM_WRSR;
|
||||
cmd[1] = 0;
|
||||
|
||||
if ((ret = eeprom_wren())) {
|
||||
printk(KERN_ERR "eeprom_wren fails\n");
|
||||
goto out1;
|
||||
}
|
||||
|
||||
local_irq_save(flag);
|
||||
|
||||
if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
|
||||
goto out;
|
||||
|
||||
if ((ret = ifx_ssc_tx(cmd, 2)) < 0) {
|
||||
ifx_ssc_cs_high(EEPROM_CS);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
|
||||
goto out;
|
||||
|
||||
local_irq_restore(flag);
|
||||
eeprom_wip_over();
|
||||
|
||||
return ret;
|
||||
|
||||
out:
|
||||
local_irq_restore(flag);
|
||||
eeprom_wip_over();
|
||||
|
||||
out1:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int eeprom_read(unsigned int addr, unsigned char *buf, unsigned int len)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned char write_buf[2];
|
||||
unsigned int eff = 0;
|
||||
unsigned long flag;
|
||||
|
||||
while (1) {
|
||||
eeprom_wip_over();
|
||||
eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE);
|
||||
eff = (eff < len) ? eff : len;
|
||||
local_irq_save(flag);
|
||||
|
||||
if ((ret = ifx_ssc_cs_low(EEPROM_CS)) < 0)
|
||||
goto out;
|
||||
|
||||
write_buf[0] = EEPROM_READ | ((unsigned char)((addr & 0x100) >> 5));
|
||||
write_buf[1] = (addr & 0xff);
|
||||
|
||||
ret = ifx_ssc_txrx(write_buf, 2, buf, eff);
|
||||
if (ret != eff) {
|
||||
printk(KERN_ERR "ssc_txrx fails %d\n", ret);
|
||||
ifx_ssc_cs_high(EEPROM_CS);
|
||||
goto out;
|
||||
}
|
||||
|
||||
buf += ret;
|
||||
len -= ret;
|
||||
addr += ret;
|
||||
|
||||
ret = ifx_ssc_cs_high(EEPROM_CS);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
local_irq_restore(flag);
|
||||
|
||||
if (len <= 0)
|
||||
goto out2;
|
||||
}
|
||||
|
||||
out:
|
||||
local_irq_restore(flag);
|
||||
out2:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int eeprom_write(unsigned int addr, unsigned char *buf, unsigned int len)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned int eff = 0;
|
||||
unsigned char write_buf[2];
|
||||
int i;
|
||||
unsigned char rx_buf[EEPROM_PAGE_SIZE];
|
||||
|
||||
while (1) {
|
||||
eeprom_wip_over();
|
||||
|
||||
if ((ret = eeprom_wren())) {
|
||||
printk(KERN_ERR "eeprom_wren fails\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
write_buf[0] = EEPROM_WRITE | ((unsigned char)((addr & 0x100) >> 5));
|
||||
write_buf[1] = (addr & 0xff);
|
||||
|
||||
eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE);
|
||||
eff = (eff < len) ? eff : len;
|
||||
|
||||
printk(KERN_INFO "EEPROM Write:\n");
|
||||
for (i = 0; i < eff; i++) {
|
||||
printk("%2x ", buf[i]);
|
||||
if ((i % 16) == 15)
|
||||
printk("\n");
|
||||
}
|
||||
printk("\n");
|
||||
|
||||
if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
|
||||
goto out;
|
||||
|
||||
if ((ret = ifx_ssc_tx(write_buf, 2)) < 0) {
|
||||
printk(KERN_ERR "ssc_tx fails %d\n", ret);
|
||||
ifx_ssc_cs_high(EEPROM_CS);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if ((ret = ifx_ssc_tx(buf, eff)) != eff) {
|
||||
printk(KERN_ERR "ssc_tx fails %d\n", ret);
|
||||
ifx_ssc_cs_high(EEPROM_CS);
|
||||
goto out;
|
||||
}
|
||||
|
||||
buf += ret;
|
||||
len -= ret;
|
||||
addr += ret;
|
||||
|
||||
if ((ret = ifx_ssc_cs_high(EEPROM_CS)))
|
||||
goto out;
|
||||
|
||||
printk(KERN_INFO "<==");
|
||||
eeprom_read((addr - eff), rx_buf, eff);
|
||||
for (i = 0; i < eff; i++)
|
||||
printk("[%x]", rx_buf[i]);
|
||||
printk("\n");
|
||||
|
||||
if (len <= 0)
|
||||
break;
|
||||
}
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ifxmips_eeprom_open(struct inode *inode, struct file *filp)
|
||||
{
|
||||
filp->f_pos = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ifxmips_eeprom_close(struct inode *inode, struct file *filp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ifxmips_eeprom_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
ssize_t ifxmips_eeprom_read(char *buf, size_t len, unsigned int addr)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned int data;
|
||||
|
||||
printk(KERN_INFO "addr:=%d\n", addr);
|
||||
printk(KERN_INFO "len:=%d\n", len);
|
||||
|
||||
if ((addr + len) > EEPROM_SIZE) {
|
||||
printk(KERN_ERR "invalid len\n");
|
||||
addr = 0;
|
||||
len = EEPROM_SIZE / 2;
|
||||
}
|
||||
|
||||
if ((ret = ifx_ssc_open((struct inode *)0, NULL))) {
|
||||
printk(KERN_ERR "ifxmips_ssc_open fails\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
data = (unsigned int)IFX_SSC_MODE_RXTX;
|
||||
|
||||
if ((ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data))) {
|
||||
printk(KERN_ERR "set RXTX mode fails\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
if ((ret = eeprom_wrsr())) {
|
||||
printk(KERN_ERR "EEPROM reset fails\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
if ((ret = eeprom_read(addr, buf, len))) {
|
||||
printk(KERN_ERR "eeprom read fails\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
if (ifx_ssc_close((struct inode *)0, NULL))
|
||||
printk(KERN_ERR "ifxmips_ssc_close fails\n");
|
||||
|
||||
return len;
|
||||
}
|
||||
EXPORT_SYMBOL(ifxmips_eeprom_read);
|
||||
|
||||
static ssize_t ifxmips_eeprom_fops_read(struct file *filp, char *ubuf, size_t len, loff_t *off)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned char ssc_rx_buf[EEPROM_SIZE];
|
||||
unsigned long flag;
|
||||
|
||||
if (*off >= EEPROM_SIZE)
|
||||
return 0;
|
||||
|
||||
if (*off + len > EEPROM_SIZE)
|
||||
len = EEPROM_SIZE - *off;
|
||||
|
||||
if (len == 0)
|
||||
return 0;
|
||||
|
||||
local_irq_save(flag);
|
||||
|
||||
if ((ret = ifxmips_eeprom_read(ssc_rx_buf, len, *off)) < 0) {
|
||||
printk(KERN_ERR "read fails, err=%x\n", ret);
|
||||
local_irq_restore(flag);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (copy_to_user((void *)ubuf, ssc_rx_buf, ret) != 0) {
|
||||
local_irq_restore(flag);
|
||||
ret = -EFAULT;
|
||||
}
|
||||
|
||||
local_irq_restore(flag);
|
||||
*off += len;
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
ssize_t ifxmips_eeprom_write(char *buf, size_t len, unsigned int addr)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned int data;
|
||||
|
||||
if ((ret = ifx_ssc_open((struct inode *)0, NULL))) {
|
||||
printk(KERN_ERR "ifxmips_ssc_open fails\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
data = (unsigned int) IFX_SSC_MODE_RXTX;
|
||||
|
||||
if ((ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data))) {
|
||||
printk(KERN_ERR "set RXTX mode fails\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
if ((ret = eeprom_wrsr())) {
|
||||
printk(KERN_ERR "EEPROM reset fails\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
if ((ret = eeprom_write(addr, buf, len))) {
|
||||
printk(KERN_ERR "eeprom write fails\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
if (ifx_ssc_close((struct inode *)0, NULL))
|
||||
printk(KERN_ERR "ifxmips_ssc_close fails\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(ifxmips_eeprom_write);
|
||||
|
||||
static ssize_t ifxmips_eeprom_fops_write(struct file *filp, const char *ubuf, size_t len, loff_t *off)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned char ssc_tx_buf[EEPROM_SIZE];
|
||||
|
||||
if (*off >= EEPROM_SIZE)
|
||||
return 0;
|
||||
|
||||
if (len + *off > EEPROM_SIZE)
|
||||
len = EEPROM_SIZE - *off;
|
||||
|
||||
if ((ret = copy_from_user(ssc_tx_buf, ubuf, len)))
|
||||
return EFAULT;
|
||||
|
||||
ret = ifxmips_eeprom_write(ssc_tx_buf, len, *off);
|
||||
|
||||
if (ret > 0)
|
||||
*off = ret;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
loff_t ifxmips_eeprom_llseek(struct file *filp, loff_t off, int whence)
|
||||
{
|
||||
loff_t newpos;
|
||||
switch (whence) {
|
||||
case SEEK_SET:
|
||||
newpos = off;
|
||||
break;
|
||||
|
||||
case SEEK_CUR:
|
||||
newpos = filp->f_pos + off;
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (newpos < 0)
|
||||
return -EINVAL;
|
||||
|
||||
filp->f_pos = newpos;
|
||||
|
||||
return newpos;
|
||||
}
|
||||
|
||||
static struct file_operations ifxmips_eeprom_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.llseek = ifxmips_eeprom_llseek,
|
||||
.read = ifxmips_eeprom_fops_read,
|
||||
.write = ifxmips_eeprom_fops_write,
|
||||
.ioctl = ifxmips_eeprom_ioctl,
|
||||
.open = ifxmips_eeprom_open,
|
||||
.release = ifxmips_eeprom_close,
|
||||
};
|
||||
|
||||
int __init ifxmips_eeprom_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
ifxmips_eeprom_maj = register_chrdev(0, "eeprom", &ifxmips_eeprom_fops);
|
||||
|
||||
if (ifxmips_eeprom_maj < 0) {
|
||||
printk(KERN_ERR "failed to register eeprom device\n");
|
||||
ret = -EINVAL;
|
||||
|
||||
goto out;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "ifxmips_eeprom : /dev/eeprom mayor %d\n", ifxmips_eeprom_maj);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
void __exit ifxmips_eeprom_cleanup_module(void)
|
||||
{
|
||||
/*if (unregister_chrdev(ifxmips_eeprom_maj, "eeprom")) {
|
||||
printk(KERN_ERR "Unable to unregister major %d for the EEPROM\n",
|
||||
maj);
|
||||
}*/
|
||||
}
|
||||
|
||||
module_exit(ifxmips_eeprom_cleanup_module);
|
||||
module_init(ifxmips_eeprom_init);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Peng Liu");
|
||||
MODULE_DESCRIPTION("IFAP EEPROM driver");
|
||||
MODULE_SUPPORTED_DEVICE("ifxmips_eeprom");
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -37,6 +37,7 @@
|
||||
|
||||
#define DRVNAME "ifxmips_led"
|
||||
|
||||
/* might need to be changed depending on shift register used on the pcb */
|
||||
#if 1
|
||||
#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_FALLING
|
||||
#else
|
||||
@ -98,7 +99,8 @@ void ifxmips_led_setup_gpio(void)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
/* we need to setup pins SH,D,ST (4,5,6) */
|
||||
/* leds are controlled via a shift register
|
||||
we need to setup pins SH,D,ST (4,5,6) to make it work */
|
||||
for (i = 4; i < 7; i++) {
|
||||
ifxmips_port_set_altsel0(IFXMIPS_LED_GPIO_PORT, i);
|
||||
ifxmips_port_clear_altsel1(IFXMIPS_LED_GPIO_PORT, i);
|
||||
|
||||
@ -383,5 +383,5 @@ module_exit(ifxmips_mii_cleanup);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
|
||||
MODULE_DESCRIPTION("ethernet map driver for IFXMIPS boards");
|
||||
MODULE_DESCRIPTION("ethernet driver for IFXMIPS boards");
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user