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ar71xx: ag71xx: fix switch port setup for AR934X
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29554 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -206,6 +206,26 @@
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#define AR934X_REG_OPER_MODE1 0x08
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#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
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#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
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#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
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#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
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#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
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#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
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#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
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#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
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#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
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#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
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#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
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#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
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#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
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#define AR934X_PORT_VLAN2_8021Q_MODE_S 30
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#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
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#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
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#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
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#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
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#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
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struct ar7240sw {
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@ -495,7 +515,7 @@ static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
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{
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struct mii_bus *mii = as->mii_bus;
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u32 ctrl;
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u32 vlan;
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u32 vid, mode;
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ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
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AR7240_PORT_CTRL_SINGLE_VLAN;
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@ -515,13 +535,11 @@ static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
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/* Set the default VID for this port */
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if (as->vlan) {
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vlan = as->vlan_id[as->pvid[port]];
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vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
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AR7240_PORT_VLAN_MODE_S;
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vid = as->vlan_id[as->pvid[port]];
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mode = AR7240_PORT_VLAN_MODE_SECURE;
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} else {
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vlan = port;
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vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
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AR7240_PORT_VLAN_MODE_S;
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vid = port;
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mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
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}
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if (as->vlan && (as->vlan_tagged & BIT(port))) {
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@ -544,11 +562,23 @@ static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
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* port that they came from */
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portmask &= ar7240sw_port_mask_but(as, port);
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/* set default VID and and destination ports for this VLAN */
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vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
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ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
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ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
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if (sw_is_ar934x(as)) {
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u32 vlan1, vlan2;
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vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
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vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
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(mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
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ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
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ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
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} else {
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u32 vlan;
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vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
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(portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
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ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
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}
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}
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static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
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