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git://projects.qi-hardware.com/openwrt-xburst.git
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adds pci support for rt288x
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17855 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -0,0 +1,19 @@
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#ifdef CONFIG_PCI
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#define RT2880_PCI_SLOT1_BASE 0x20000000
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#define RALINK_PCI_BASE 0xA0440000
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#define RT2880_PCI_PCICFG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0000))
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#define RT2880_PCI_ARBCTL ((unsigned long*)(RALINK_PCI_BASE + 0x0080))
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#define RT2880_PCI_BAR0SETUP_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0010))
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#define RT2880_PCI_CONFIG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0020))
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#define RT2880_PCI_CONFIG_DATA ((unsigned long*)(RALINK_PCI_BASE + 0x0024))
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#define RT2880_PCI_MEMBASE ((unsigned long*)(RALINK_PCI_BASE + 0x0028))
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#define RT2880_PCI_IOBASE ((unsigned long*)(RALINK_PCI_BASE + 0x002C))
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#define RT2880_PCI_IMBASEBAR0_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0018))
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#define RT2880_PCI_ID ((unsigned long*)(RALINK_PCI_BASE + 0x0030))
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#define RT2880_PCI_CLASS ((unsigned long*)(RALINK_PCI_BASE + 0x0034))
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#define RT2880_PCI_SUBID ((unsigned long*)(RALINK_PCI_BASE + 0x0038))
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#define RT2880_PCI_PCIMSK_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x000C))
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#endif
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70
target/linux/ramips/files/arch/mips/pci/ops-rt288x.c
Normal file
70
target/linux/ramips/files/arch/mips/pci/ops-rt288x.c
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/version.h>
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#include <asm/pci.h>
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#include <asm/io.h>
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#include <linux/init.h>
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#include <linux/mod_devicetable.h>
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#include <asm/mach-rt288x/rt288x.h>
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#include <asm/mach-rt288x/rt288x_pci.h>
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#ifdef CONFIG_PCI
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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static int config_access(unsigned char access_type, struct pci_bus *bus,
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unsigned int devfn, unsigned char where, u32 * data)
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{
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unsigned int slot = PCI_SLOT(devfn);
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unsigned int address;
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u8 func = PCI_FUNC(devfn);
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address = (bus->number << 16) | (slot << 11) | (func << 8) | (where& 0xfc) | 0x80000000;
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writel(address, RT2880_PCI_CONFIG_ADDR);
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if (access_type == PCI_ACCESS_WRITE)
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writel(*data, RT2880_PCI_CONFIG_DATA);
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else
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*data = readl(RT2880_PCI_CONFIG_DATA);
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return 0;
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}
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int
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pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
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{
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u32 data = 0;
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if(config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if(size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if(size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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int
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pci_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data = 0;
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if(size == 4)
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{
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data = val;
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} else {
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if(config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if(size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if(size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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}
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if(config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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#endif
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134
target/linux/ramips/files/arch/mips/pci/pci-rt288x.c
Normal file
134
target/linux/ramips/files/arch/mips/pci/pci-rt288x.c
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@ -0,0 +1,134 @@
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/version.h>
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#include <asm/pci.h>
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#include <asm/io.h>
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#include <asm/mach-rt288x/rt288x.h>
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#include <asm/mach-rt288x/rt288x_pci.h>
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#include <linux/init.h>
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#include <linux/mod_devicetable.h>
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#ifdef CONFIG_PCI
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extern int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
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extern int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
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struct pci_ops rt2880_pci_ops = {
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.read = pci_config_read,
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.write = pci_config_write,
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};
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static struct resource pci_io_resource = {
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.name = "pci MEM space",
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.start = 0x20000000,
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.end = 0x2FFFFFFF,
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.flags = IORESOURCE_MEM,
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};
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static struct resource pci_mem_resource = {
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.name = "pci IO space",
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.start = 0x00460000,
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.end = 0x0046FFFF,
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.flags = IORESOURCE_IO,
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};
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struct pci_controller rt2880_controller = {
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.pci_ops = &rt2880_pci_ops,
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.mem_resource = &pci_io_resource,
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.io_resource = &pci_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_offset = 0x00000000UL,
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};
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void inline
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read_config(unsigned long bus, unsigned long dev, unsigned long func,
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unsigned long reg, unsigned long *val)
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{
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unsigned long address =
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(bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
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writel(address, RT2880_PCI_CONFIG_ADDR);
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*val = readl(RT2880_PCI_CONFIG_DATA);
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}
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void inline
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write_config(unsigned long bus, unsigned long dev, unsigned long func,
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unsigned long reg, unsigned long val)
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{
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unsigned long address =
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(bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
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writel(address, RT2880_PCI_CONFIG_ADDR);
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writel(val, RT2880_PCI_CONFIG_DATA);
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}
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int __init
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pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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u16 cmd;
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unsigned long val;
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int irq = -1;
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if (dev->bus->number != 0)
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return 0;
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switch(PCI_SLOT(dev->devfn))
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{
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case 0x00:
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write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
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read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
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break;
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case 0x11:
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irq = RT288X_CPU_IRQ_PCI;
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break;
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default:
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printk("%s:%s[%d] trying to alloc unknown pci irq\n", __FILE__, __func__, __LINE__);
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BUG();
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break;
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}
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pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
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pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
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pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
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cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK | PCI_COMMAND_SERR |
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PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
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pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
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pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE, dev->irq);
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return irq;
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}
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int
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init_rt2880pci(void)
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{
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unsigned long val = 0;
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int i;
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writel(0, RT2880_PCI_PCICFG_ADDR);
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for(i = 0; i < 0xfffff; i++) {}
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writel(0x79, RT2880_PCI_ARBCTL);
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writel(0x07FF0001, RT2880_PCI_BAR0SETUP_ADDR);
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writel(RT2880_PCI_SLOT1_BASE, RT2880_PCI_MEMBASE);
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writel(0x00460000, RT2880_PCI_IOBASE);
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writel(0x08000000, RT2880_PCI_IMBASEBAR0_ADDR);
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writel(0x08021814, RT2880_PCI_ID);
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writel(0x00800001, RT2880_PCI_CLASS);
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writel(0x28801814, RT2880_PCI_SUBID);
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writel(0x000c0000, RT2880_PCI_PCIMSK_ADDR);
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write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
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read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
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register_pci_controller(&rt2880_controller);
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return 0;
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}
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int
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pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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struct pci_fixup pcibios_fixups[] = {
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{0}
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};
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arch_initcall(init_rt2880pci);
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#endif
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@ -108,6 +108,8 @@ CONFIG_MTD_PHYSMAP=y
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# CONFIG_NXP_STB220 is not set
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# CONFIG_NXP_STB225 is not set
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PCI=y
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CONFIG_PCI_DOMAINS=y
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# CONFIG_PCSPKR_PLATFORM is not set
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CONFIG_PHYLIB=y
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# CONFIG_PMC_MSP is not set
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