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git://projects.qi-hardware.com/openwrt-xburst.git
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clean up atheros pci code
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12337 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -30,7 +30,6 @@
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#define AR531X_MEM_BASE 0x80800000UL
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#define AR531X_MEM_SIZE 0x00ffffffUL
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#define AR531X_IO_SIZE 0x00007fffUL
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#define IDSEL_SHIFT 13
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static spinlock_t ar531x_pci_lock = SPIN_LOCK_UNLOCKED;
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@ -42,25 +41,24 @@ static int config_access(int busno, int dev, int func, int where, int size, u32
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u32 reg;
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unsigned long flags;
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int ret = -1;
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if ((busno != 0) || (dev > 3) || (func > 2))
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if ((busno != 0) || ((dev != 0) && (dev != 3)) || (func > 2))
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return ret;
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spin_lock_irqsave(&ar531x_pci_lock, flags);
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/* Select Configuration access */
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reg = sysRegRead(AR5315_PCI_MISC_CONFIG);
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reg |= AR5315_PCIMISC_CFG_SEL;
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sysRegWrite(AR5315_PCI_MISC_CONFIG, reg);
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(void)sysRegRead(AR5315_PCI_MISC_CONFIG);
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address = (u32)cfgaddr + (1 << (IDSEL_SHIFT + dev)) + (func << 8) + where;
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address = (u32)cfgaddr + (1 << (IDSEL_SHIFT + dev)) + (func << 8) + where;
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if (size == 1)
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address ^= 0x3;
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else if (size == 2)
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address ^= 0x2;
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if (write) {
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if (size == 1)
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ret = put_dbe(ptr, (u8 *) address);
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@ -82,9 +80,9 @@ static int config_access(int busno, int dev, int func, int where, int size, u32
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reg &= ~AR5315_PCIMISC_CFG_SEL;
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sysRegWrite(AR5315_PCI_MISC_CONFIG, reg);
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(void)sysRegRead(AR5315_PCI_MISC_CONFIG);
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spin_unlock_irqrestore(&ar531x_pci_lock, flags);
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if (ret) {
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*((u32 *)ptr) = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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@ -111,21 +109,23 @@ struct pci_ops ar531x_pci_ops = {
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static struct resource ar531x_mem_resource = {
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.name = "AR531x PCI MEM",
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.start = AR531X_MEM_BASE,
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.end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1,
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.end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000,
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.flags = IORESOURCE_MEM,
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};
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static struct resource ar531x_io_resource = {
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.name = "AR531x PCI I/O",
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.start = 0,
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.end = AR531X_IO_SIZE,
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.start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE,
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.end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1,
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.flags = IORESOURCE_IO,
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};
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struct pci_controller ar531x_pci_controller = {
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.pci_ops = &ar531x_pci_ops,
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.pci_ops = &ar531x_pci_ops,
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.mem_resource = &ar531x_mem_resource,
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.io_resource = &ar531x_io_resource,
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.mem_offset = 0x00000000UL,
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.io_offset = 0x00000000UL,
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};
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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@ -145,18 +145,18 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
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reg = sysRegRead(AR5315_PCI_INTEN_REG);
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reg &= ~AR5315_PCI_INT_ENABLE;
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sysRegWrite(AR5315_PCI_INTEN_REG, reg);
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reg = sysRegRead(AR5315_PCI_INT_STATUS);
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reg |= (AR5315_PCI_ABORT_INT | AR5315_PCI_EXT_INT);
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sysRegWrite(AR5315_PCI_INT_STATUS, reg);
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reg = sysRegRead(AR5315_PCI_INT_MASK);
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reg |= (AR5315_PCI_EXT_INT | AR5315_PCI_ABORT_INT);
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sysRegWrite(AR5315_PCI_INT_MASK, reg);
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reg = sysRegRead(AR5315_PCI_INTEN_REG);
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reg |= AR5315_PCI_INT_ENABLE;
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sysRegWrite(AR5315_PCI_INTEN_REG, reg);
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sysRegWrite(AR5315_PCI_INTEN_REG, reg);
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return 0;
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}
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@ -167,7 +167,7 @@ static void ar5315_pci_fixup(struct pci_dev *dev)
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if ((PCI_SLOT(dev->devfn) != 3) || (PCI_FUNC(dev->devfn) != 0) || (bus->number != 0))
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return;
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#define _DEV bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)
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printk("PCI: fixing up device %d,%d,%d\n", _DEV);
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/* fix up mbars */
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@ -177,7 +177,7 @@ static void ar5315_pci_fixup(struct pci_dev *dev)
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config_access(_DEV, PCI_COMMAND, 4,
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PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_SPECIAL|
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PCI_COMMAND_INVALIDATE|PCI_COMMAND_PARITY|PCI_COMMAND_SERR|
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PCI_COMMAND_FAST_BACK, 1);
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PCI_COMMAND_FAST_BACK, 1);
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#undef _DEV
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar5315_pci_fixup);
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@ -189,13 +189,15 @@ int __init ar5315_pci_init(void)
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printk("AR531x PCI init... \n");
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cfgaddr = (u32) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */
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set_io_port_base((unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_IO_SIZE - 1, AR531X_IO_SIZE)); /* PCI I/O space */
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ar531x_pci_controller.io_map_base =
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(unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE);
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set_io_port_base(ar531x_pci_controller.io_map_base); /* PCI I/O space */
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reg = sysRegRead(AR5315_RESET);
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sysRegWrite(AR5315_RESET, reg | AR5315_RESET_PCIDMA);
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udelay(10*1000);
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sysRegWrite(AR5315_RESET, reg & ~AR5315_RESET_PCIDMA);
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sysRegRead(AR5315_RESET); /* read after */
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@ -219,13 +221,13 @@ int __init ar5315_pci_init(void)
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reg |= (IF_PCI | IF_PCI_HOST | IF_PCI_INTR | (IF_PCI_CLK_OUTPUT_CLK << IF_PCI_CLK_SHIFT));
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sysRegWrite(AR5315_IF_CTL, reg);
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/* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
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reg = sysRegRead(AR5315_PCI_MISC_CONFIG);
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reg &= ~(AR5315_PCIMISC_RST_MODE);
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reg |= AR5315_PCIRST_LOW;
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sysRegWrite(AR5315_PCI_MISC_CONFIG, reg);
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/* wait for 100 ms */
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udelay(100*1000);
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@ -244,6 +246,12 @@ int __init ar5315_pci_init(void)
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udelay(500*1000);
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/* dirty hack - anyone with a datasheet that knows the memory map ? */
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ioport_resource.start = 0x10000000;
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ioport_resource.end = 0xffffffff;
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iomem_resource.start = 0x10000000;
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iomem_resource.end = 0xffffffff;
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register_pci_controller(&ar531x_pci_controller);
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printk("done\n");
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