mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-23 20:00:39 +02:00
[lantiq] move ltq-adsl
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34693 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
parent
cec4e04bcc
commit
a16192382c
54
package/platform/lantiq/ltq-adsl-fw/Makefile
Normal file
54
package/platform/lantiq/ltq-adsl-fw/Makefile
Normal file
@ -0,0 +1,54 @@
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#
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# Copyright (C) 2011 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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PKG_NAME:=ltq-adsl-fw
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PKG_VERSION:=0.1
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PKG_RELEASE:=1
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PKG_BUILD_DIR:=$(BUILD_DIR)/ltq-dsl-fw-$(PKG_VERSION)
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PKG_SOURCE:=ltq-dsl-fw-$(PKG_VERSION).tar.bz2
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PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/
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PKG_MD5SUM:=4700a36b66b955b4c5544227267356f4
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PKG_MAINTAINER:=John Crispin <blogic@openwrt.org>
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include $(INCLUDE_DIR)/package.mk
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define Package/kmod-ltq-adsl-fw-template
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TITLE+=Firmware Annex-$(1) $(2)
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SECTION:=sys
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SUBMENU:=Network Devices
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VARIANT:= $(2)-fw-$(1)
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SOC:=$(2)
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ANNEX:=$(1)
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URL:=http://www.lantiq.com/
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DEPENDS:=@TARGET_lantiq_$(3) +kmod-ltq-adsl-$(2)
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endef
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Package/kmod-ltq-adsl-danube-fw-a=$(call Package/kmod-ltq-adsl-fw-template,a,danube,xway)
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Package/kmod-ltq-adsl-danube-fw-b=$(call Package/kmod-ltq-adsl-fw-template,b,danube,xway)
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Package/kmod-ltq-adsl-ar9-fw-a=$(call Package/kmod-ltq-adsl-fw-template,a,ar9,xway)
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Package/kmod-ltq-adsl-ar9-fw-b=$(call Package/kmod-ltq-adsl-fw-template,b,ar9,xway)
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Package/kmod-ltq-adsl-ase-fw-a=$(call Package/kmod-ltq-adsl-fw-template,a,ase,ase)
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Package/kmod-ltq-adsl-ase-fw-b=$(call Package/kmod-ltq-adsl-fw-template,b,ase,ase)
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define Build/Compile
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endef
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define Package/kmod-ltq-adsl-$(BUILD_VARIANT)/install
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$(INSTALL_DIR) $(1)/lib/firmware/
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$(CP) $(PKG_BUILD_DIR)/$(FW_NAME)/ltq-dsl-fw-$(ANNEX)-$(SOC).bin $(1)/lib/firmware/
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#ln -s /lib/firmware/$(FW_NAME)/ltq-dsl-fw-$(BUILD_VARIANT).bin $(1)/lib/firmware/adsl.bin
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endef
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$(eval $(call BuildPackage,kmod-ltq-adsl-danube-fw-a))
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$(eval $(call BuildPackage,kmod-ltq-adsl-danube-fw-b))
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$(eval $(call BuildPackage,kmod-ltq-adsl-ase-fw-a))
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$(eval $(call BuildPackage,kmod-ltq-adsl-ase-fw-b))
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$(eval $(call BuildPackage,kmod-ltq-adsl-ar9-fw-a))
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$(eval $(call BuildPackage,kmod-ltq-adsl-ar9-fw-b))
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49
package/platform/lantiq/ltq-adsl-mei/Makefile
Normal file
49
package/platform/lantiq/ltq-adsl-mei/Makefile
Normal file
@ -0,0 +1,49 @@
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# Copyright (C) 2012 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_NAME:=ltq-adsl-mei
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PKG_RELEASE:=1
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PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/ltq-adsl-mei-$(BUILD_VARIANT)/
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PKG_MAINTAINER:=John Crispin <blogic@openwrt.org>
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include $(INCLUDE_DIR)/package.mk
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define KernelPackage/ltq-adsl-mei-template
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SECTION:=sys
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CATEGORY:=Kernel modules
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SUBMENU:=Network Devices
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TITLE:=mei driver for $(1)
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URL:=http://www.lantiq.com/
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VARIANT:=$(1)
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DEPENDS:=@TARGET_lantiq_$(2)
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FILES:=$(PKG_BUILD_DIR)/ltq_mei_$(1).ko
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AUTOLOAD:=$(call AutoLoad,50,ltq_mei_$(1))
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endef
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KernelPackage/ltq-adsl-danube-mei=$(call KernelPackage/ltq-adsl-mei-template,danube,xway)
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KernelPackage/ltq-adsl-ar9-mei=$(call KernelPackage/ltq-adsl-mei-template,ar9,xway)
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KernelPackage/ltq-adsl-ase-mei=$(call KernelPackage/ltq-adsl-mei-template,ase,ase)
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define Build/Prepare
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$(INSTALL_DIR) $(PKG_BUILD_DIR)/
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$(CP) ./src/* $(PKG_BUILD_DIR)/
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endef
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define Build/Configure
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endef
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define Build/Compile
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cd $(LINUX_DIR); \
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ARCH=mips CROSS_COMPILE="$(KERNEL_CROSS)" \
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$(MAKE) BUILD_VARIANT=$(BUILD_VARIANT) M=$(PKG_BUILD_DIR)/ V=1 modules
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endef
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$(eval $(call KernelPackage,ltq-adsl-danube-mei))
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$(eval $(call KernelPackage,ltq-adsl-ase-mei))
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$(eval $(call KernelPackage,ltq-adsl-ar9-mei))
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17
package/platform/lantiq/ltq-adsl-mei/src/Makefile
Normal file
17
package/platform/lantiq/ltq-adsl-mei/src/Makefile
Normal file
@ -0,0 +1,17 @@
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ifeq ($(BUILD_VARIANT),danube)
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CFLAGS_MODULE = -DCONFIG_DANUBE -DCONFIG_IFXMIPS_DSL_CPE_MEI
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obj-m = ltq_mei_danube.o
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ltq_mei_danube-objs = lantiq_mei.o
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endif
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ifeq ($(BUILD_VARIANT),ase)
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CFLAGS_MODULE = -DCONFIG_AMAZON_SE -DCONFIG_IFXMIPS_DSL_CPE_MEI
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obj-m = ltq_mei_ase.o
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ltq_mei_ase-objs = lantiq_mei.o
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endif
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ifeq ($(BUILD_VARIANT),ar9)
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CFLAGS_MODULE = -DCONFIG_AR9 -DCONFIG_IFXMIPS_DSL_CPE_MEI
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obj-m = ltq_mei_ar9.o
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ltq_mei_ar9-objs = lantiq_mei.o
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endif
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@ -29,11 +29,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/version.h>
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))
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#include <linux/utsrelease.h>
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#else
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#include <generated/utsrelease.h>
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#endif
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#include <linux/types.h>
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#include <linux/fs.h>
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#include <linux/mm.h>
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@ -47,11 +43,13 @@
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/sched.h>
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#include <linux/platform_device.h>
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#include <asm/uaccess.h>
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#include <asm/hardirq.h>
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#include "lantiq_atm.h"
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#include <lantiq_soc.h>
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#include "ifxmips_atm.h"
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//#include "ifxmips_atm.h"
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#define IFX_MEI_BSP
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#include "ifxmips_mei_interface.h"
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@ -144,6 +142,7 @@ DSL_DEV_HwVersion_t bsp_chip_info;
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#define IFX_MEI_DEVNAME "ifx_mei"
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#define BSP_MAX_DEVICES 1
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#define MEI_DIRNAME "ifxmips_mei"
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DSL_DEV_MeiError_t DSL_BSP_FWDownload (DSL_DEV_Device_t *, const char *, unsigned long, long *, long *);
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DSL_DEV_MeiError_t DSL_BSP_Showtime (DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
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@ -164,32 +163,12 @@ static int IFX_MEI_GetPage (DSL_DEV_Device_t *, u32, u32, u32, u32 *, u32 *);
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static int IFX_MEI_BarUpdate (DSL_DEV_Device_t *, int);
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static ssize_t IFX_MEI_Write (DSL_DRV_file_t *, const char *, size_t, loff_t *);
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
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static int IFX_MEI_UserIoctls (DSL_DRV_inode_t *, DSL_DRV_file_t *, unsigned int, unsigned long);
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#else
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static int IFX_MEI_UserIoctls (DSL_DRV_file_t *, unsigned int, unsigned long);
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#endif
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static long IFX_MEI_UserIoctls (DSL_DRV_file_t *, unsigned int, unsigned long);
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static int IFX_MEI_Open (DSL_DRV_inode_t *, DSL_DRV_file_t *);
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static int IFX_MEI_Release (DSL_DRV_inode_t *, DSL_DRV_file_t *);
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void AMAZON_SE_MEI_ARC_MUX_Test(void);
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#ifdef CONFIG_PROC_FS
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static int IFX_MEI_ProcRead (struct file *, char *, size_t, loff_t *);
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static ssize_t IFX_MEI_ProcWrite (struct file *, const char *, size_t, loff_t *);
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#define PROC_ITEMS 11
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#define MEI_DIRNAME "ifxmips_mei"
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static struct proc_dir_entry *meidir;
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static struct file_operations IFX_MEI_ProcOperations = {
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read:IFX_MEI_ProcRead,
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write:IFX_MEI_ProcWrite,
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};
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static reg_entry_t regs[BSP_MAX_DEVICES][PROC_ITEMS]; //total items to be monitored by /proc/mei
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#define NUM_OF_REG_ENTRY (sizeof(regs[0])/sizeof(reg_entry_t))
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#endif //CONFIG_PROC_FS
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void IFX_MEI_ARC_MUX_Test(void);
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static int adsl_dummy_ledcallback(void);
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@ -208,18 +187,13 @@ static void *g_xdata_addr = NULL;
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static u32 *mei_arc_swap_buff = NULL; // holding swap pages
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39))
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extern void ltq_mask_and_ack_irq(unsigned int irq_nr);
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#define MEI_MASK_AND_ACK_IRQ ltq_mask_and_ack_irq
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#else
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extern void ltq_mask_and_ack_irq(struct irq_data *d);
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static void inline MEI_MASK_AND_ACK_IRQ(int x)
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{
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struct irq_data d;
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d.irq = x;
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d.hwirq = x;
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ltq_mask_and_ack_irq(&d);
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}
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#endif
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#define MEI_MAJOR 105
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static int dev_major = MEI_MAJOR;
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@ -228,11 +202,7 @@ static struct file_operations bsp_mei_operations = {
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open:IFX_MEI_Open,
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release:IFX_MEI_Release,
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write:IFX_MEI_Write,
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
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ioctl:IFX_MEI_UserIoctls,
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#else
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unlocked_ioctl:IFX_MEI_UserIoctls,
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#endif
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};
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static DSL_DEV_Device_t dsl_devices[BSP_MAX_DEVICES];
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@ -1763,7 +1733,7 @@ int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *p)
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* \param regs Pointer to the structure of danube mips registers
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* \ingroup Internal
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*/
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static irqreturn_t IFX_MEI_Dying_Gasp_IrqHandle (int int1, void *void0)
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/*static irqreturn_t IFX_MEI_Dying_Gasp_IrqHandle (int int1, void *void0)
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{
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DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) void0;
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DSL_BSP_CB_Type_t event;
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@ -1785,11 +1755,11 @@ static irqreturn_t IFX_MEI_Dying_Gasp_IrqHandle (int int1, void *void0)
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IFX_MEI_EMSG("Dying Gasp! Shutting Down... (Work around for Amazon-S Venus emulator)\n");
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#else
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IFX_MEI_EMSG("Dying Gasp! Shutting Down...\n");
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// kill_proc (1, SIGINT, 1); /* Ask init to reboot us */
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// kill_proc (1, SIGINT, 1);
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#endif
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return IRQ_HANDLED;
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}
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*/
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extern void ifx_usb_enable_afe_oc(void);
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/**
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@ -2462,14 +2432,14 @@ IFX_MEI_IoctlCopyTo (int from_kernel, char *dest, char *from, int size)
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return ret;
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}
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static int
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int
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IFX_MEI_Ioctls (DSL_DEV_Device_t * pDev, int from_kernel, unsigned int command, unsigned long lon)
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{
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int i = 0;
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int meierr = DSL_DEV_MEI_ERR_SUCCESS;
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u32 base_address = LTQ_MEI_BASE_ADDR;
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DSL_DEV_WinHost_Message_t winhost_msg, m;
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DSL_DEV_MeiDebug_t debugrdwr;
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// DSL_DEV_MeiDebug_t debugrdwr;
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DSL_DEV_MeiReg_t regrdwr;
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switch (command) {
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@ -2561,7 +2531,7 @@ IFX_MEI_Ioctls (DSL_DEV_Device_t * pDev, int from_kernel, unsigned int command,
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}
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break;
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case DSL_FIO_BSP_DEBUG_READ:
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/* case DSL_FIO_BSP_DEBUG_READ:
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case DSL_FIO_BSP_DEBUG_WRITE:
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IFX_MEI_IoctlCopyFrom (from_kernel,
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(char *) (&debugrdwr),
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@ -2588,7 +2558,7 @@ IFX_MEI_Ioctls (DSL_DEV_Device_t * pDev, int from_kernel, unsigned int command,
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iCount);
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IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&debugrdwr), sizeof (debugrdwr));
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break;
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break;*/
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case DSL_FIO_BSP_GET_VERSION:
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IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&bsp_mei_version), sizeof (DSL_DEV_Version_t));
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break;
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@ -2694,28 +2664,14 @@ DSL_BSP_KernelIoctls (DSL_DEV_Device_t * pDev, unsigned int command,
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return error;
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}
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
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static int
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IFX_MEI_UserIoctls (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil,
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unsigned int command, unsigned long lon)
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#else
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static int
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static long
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IFX_MEI_UserIoctls (DSL_DRV_file_t * fil,
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unsigned int command, unsigned long lon)
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#endif
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{
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int error = 0;
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
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int maj = MAJOR (ino->i_rdev);
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int num = MINOR (ino->i_rdev);
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#endif
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DSL_DEV_Device_t *pDev;
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
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pDev = IFX_BSP_HandleGet (maj, num);
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#else
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pDev = IFX_BSP_HandleGet (0, 0);
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#endif
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if (pDev == NULL)
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return -EIO;
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@ -2723,207 +2679,6 @@ IFX_MEI_UserIoctls (DSL_DRV_file_t * fil,
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return error;
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}
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#ifdef CONFIG_PROC_FS
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/*
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* Register a callback function for linux proc filesystem
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*/
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static int
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IFX_MEI_InitProcFS (int num)
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{
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struct proc_dir_entry *entry;
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int i ;
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DSL_DEV_Device_t *pDev;
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reg_entry_t regs_temp[PROC_ITEMS] = {
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/* flag, name, description } */
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{NULL, "arcmsgav", "arc to mei message ", 0},
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{NULL, "cmv_reply", "cmv needs reply", 0},
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{NULL, "cmv_waiting", "waiting for cmv reply from arc", 0},
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{NULL, "modem_ready_cnt", "ARC to MEI indicator count", 0},
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{NULL, "cmv_count", "MEI to ARC CMVs", 0},
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{NULL, "reply_count", "ARC to MEI Reply", 0},
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{NULL, "Recent_indicator", "most recent indicator", 0},
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{NULL, "fw_version", "Firmware Version", 0},
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{NULL, "fw_date", "Firmware Date", 0},
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{NULL, "meminfo", "Memory Allocation Information", 0},
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{NULL, "version", "MEI version information", 0},
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};
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pDev = &dsl_devices[num];
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if (pDev == NULL)
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return -ENOMEM;
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regs_temp[0].flag = &(DSL_DEV_PRIVATE(pDev)->arcmsgav);
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regs_temp[1].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_reply);
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regs_temp[2].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_waiting);
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regs_temp[3].flag = &(DSL_DEV_PRIVATE(pDev)->modem_ready_cnt);
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regs_temp[4].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_count);
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regs_temp[5].flag = &(DSL_DEV_PRIVATE(pDev)->reply_count);
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regs_temp[6].flag = (int *) &(DSL_DEV_PRIVATE(pDev)->Recent_indicator);
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memcpy ((char *) regs[num], (char *) regs_temp, sizeof (regs_temp));
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// procfs
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meidir = proc_mkdir (MEI_DIRNAME, NULL);
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if (meidir == NULL) {
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IFX_MEI_EMSG ("Failed to create /proc/%s\n", MEI_DIRNAME);
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return (-ENOMEM);
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}
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for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
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entry = create_proc_entry (regs[num][i].name,
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S_IWUSR | S_IRUSR | S_IRGRP |
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S_IROTH, meidir);
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if (entry) {
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regs[num][i].low_ino = entry->low_ino;
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entry->proc_fops = &IFX_MEI_ProcOperations;
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}
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else {
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IFX_MEI_EMSG ("Failed to create /proc/%s/%s\n", MEI_DIRNAME, regs[num][i].name);
|
||||
return (-ENOMEM);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reading function for linux proc filesystem
|
||||
*/
|
||||
static int
|
||||
IFX_MEI_ProcRead (struct file *file, char *buf, size_t nbytes, loff_t * ppos)
|
||||
{
|
||||
int i_ino = (file->f_dentry->d_inode)->i_ino;
|
||||
char *p = buf;
|
||||
int i;
|
||||
int num;
|
||||
reg_entry_t *entry = NULL;
|
||||
DSL_DEV_Device_t *pDev = NULL;
|
||||
DSL_DEV_WinHost_Message_t m;
|
||||
|
||||
for (num = 0; num < BSP_MAX_DEVICES; num++) {
|
||||
for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
|
||||
if (regs[num][i].low_ino == (unsigned short)i_ino) {
|
||||
entry = ®s[num][i];
|
||||
pDev = &dsl_devices[num];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (entry == NULL)
|
||||
return -EINVAL;
|
||||
else if (strcmp(entry->name, "meminfo") == 0) {
|
||||
if (*ppos > 0) /* Assume reading completed in previous read */
|
||||
return 0;
|
||||
p += sprintf (p, "No Address Size\n");
|
||||
for (i = 0; i < MAX_BAR_REGISTERS; i++) {
|
||||
p += sprintf (p, "BAR[%02d] Addr:0x%08X Size:%lu\n",
|
||||
i, (u32) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[i].address,
|
||||
DSL_DEV_PRIVATE(pDev)-> adsl_mem_info[i].size);
|
||||
//printk( "BAR[%02d] Addr:0x%08X Size:%d\n",i,adsl_mem_info[i].address,adsl_mem_info[i].size);
|
||||
}
|
||||
*ppos += (p - buf);
|
||||
} else if (strcmp(entry->name, "fw_version") == 0) {
|
||||
if (*ppos > 0) /* Assume reading completed in previous read */
|
||||
return 0;
|
||||
if (DSL_DEV_PRIVATE(pDev)->modem_ready_cnt < 1)
|
||||
return -EAGAIN;
|
||||
//major:bits 0-7
|
||||
//minor:bits 8-15
|
||||
makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 54, 0, 1, NULL, m.msg.TxMessage);
|
||||
if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
|
||||
return -EIO;
|
||||
p += sprintf(p, "FW Version: %d.%d.", m.msg.RxMessage[4] & 0xFF, (m.msg.RxMessage[4] >> 8) & 0xFF);
|
||||
//sub_version:bits 4-7
|
||||
//int_version:bits 0-3
|
||||
//spl_appl:bits 8-13
|
||||
//rel_state:bits 14-15
|
||||
makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 54, 1, 1, NULL, m.msg.TxMessage);
|
||||
if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
|
||||
return -EIO;
|
||||
p += sprintf(p, "%d.%d.%d.%d\n",
|
||||
(m.msg.RxMessage[4] >> 4) & 0xF, m.msg.RxMessage[4] & 0xF,
|
||||
(m.msg.RxMessage[4] >> 14) & 3, (m.msg.RxMessage[4] >> 8) & 0x3F);
|
||||
*ppos += (p - buf);
|
||||
} else if (strcmp(entry->name, "fw_date") == 0) {
|
||||
if (*ppos > 0) /* Assume reading completed in previous read */
|
||||
return 0;
|
||||
if (DSL_DEV_PRIVATE(pDev)->modem_ready_cnt < 1)
|
||||
return -EAGAIN;
|
||||
|
||||
makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 0, 1, NULL, m.msg.TxMessage);
|
||||
if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
|
||||
return -EIO;
|
||||
/* Day/Month */
|
||||
p += sprintf(p, "FW Date: %d.%d.", m.msg.RxMessage[4] & 0xFF, (m.msg.RxMessage[4] >> 8) & 0xFF);
|
||||
|
||||
makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 2, 1, NULL, m.msg.TxMessage);
|
||||
if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
|
||||
return -EIO;
|
||||
/* Year */
|
||||
p += sprintf(p, "%d ", m.msg.RxMessage[4]);
|
||||
|
||||
makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 1, 1, NULL, m.msg.TxMessage);
|
||||
if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
|
||||
return -EIO;
|
||||
/* Hour:Minute */
|
||||
p += sprintf(p, "%d:%d\n", (m.msg.RxMessage[4] >> 8) & 0xFF, m.msg.RxMessage[4] & 0xFF);
|
||||
|
||||
*ppos += (p - buf);
|
||||
} else if (strcmp(entry->name, "version") == 0) {
|
||||
if (*ppos > 0) /* Assume reading completed in previous read */
|
||||
return 0;
|
||||
p += sprintf (p, "IFX MEI V%ld.%ld.%ld\n", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
|
||||
|
||||
*ppos += (p - buf);
|
||||
} else if (entry->flag != (int *) DSL_DEV_PRIVATE(pDev)->Recent_indicator) {
|
||||
if (*ppos > 0) /* Assume reading completed in previous read */
|
||||
return 0; // indicates end of file
|
||||
p += sprintf (p, "0x%08X\n\n", *(entry->flag));
|
||||
*ppos += (p - buf);
|
||||
if ((p - buf) > nbytes) /* Assume output can be read at one time */
|
||||
return -EINVAL;
|
||||
} else {
|
||||
if ((int) (*ppos) / ((int) 7) == 16)
|
||||
return 0; // indicate end of the message
|
||||
p += sprintf (p, "0x%04X\n\n", *(((u16 *) (entry->flag)) + (int) (*ppos) / ((int) 7)));
|
||||
*ppos += (p - buf);
|
||||
}
|
||||
return p - buf;
|
||||
}
|
||||
|
||||
/*
|
||||
* Writing function for linux proc filesystem
|
||||
*/
|
||||
static ssize_t
|
||||
IFX_MEI_ProcWrite (struct file *file, const char *buffer, size_t count, loff_t * ppos)
|
||||
{
|
||||
int i_ino = (file->f_dentry->d_inode)->i_ino;
|
||||
reg_entry_t *current_reg = NULL;
|
||||
int i = 0;
|
||||
int num = 0;
|
||||
unsigned long newRegValue = 0;
|
||||
char *endp = NULL;
|
||||
DSL_DEV_Device_t *pDev = NULL;
|
||||
|
||||
for (num = 0; num < BSP_MAX_DEVICES; num++) {
|
||||
for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
|
||||
if (regs[num][i].low_ino == i_ino) {
|
||||
current_reg = ®s[num][i];
|
||||
pDev = &dsl_devices[num];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if ((current_reg == NULL)
|
||||
|| (current_reg->flag ==
|
||||
(int *) DSL_DEV_PRIVATE(pDev)->
|
||||
Recent_indicator))
|
||||
return -EINVAL;
|
||||
|
||||
newRegValue = simple_strtoul (buffer, &endp, 0);
|
||||
*(current_reg->flag) = (int) newRegValue;
|
||||
return (count + endp - buffer);
|
||||
}
|
||||
#endif //CONFIG_PROC_FS
|
||||
|
||||
static int adsl_dummy_ledcallback(void)
|
||||
{
|
||||
return 0;
|
||||
@ -2962,13 +2717,12 @@ EXPORT_SYMBOL(ifx_mei_atm_showtime_check);
|
||||
/*
|
||||
* Writing function for linux proc filesystem
|
||||
*/
|
||||
int __init
|
||||
IFX_MEI_ModuleInit (void)
|
||||
static int __devinit ltq_mei_probe(struct platform_device *pdev)
|
||||
{
|
||||
int i = 0;
|
||||
static struct class *dsl_class;
|
||||
|
||||
pr_info("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
|
||||
pr_info("IFX MEI Version %ld.%02ld.%02ld\n", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
|
||||
|
||||
for (i = 0; i < BSP_MAX_DEVICES; i++) {
|
||||
if (IFX_MEI_InitDevice (i) != 0) {
|
||||
@ -2976,9 +2730,6 @@ IFX_MEI_ModuleInit (void)
|
||||
return -EIO;
|
||||
}
|
||||
IFX_MEI_InitDevNode (i);
|
||||
#ifdef CONFIG_PROC_FS
|
||||
IFX_MEI_InitProcFS (i);
|
||||
#endif
|
||||
}
|
||||
for (i = 0; i <= DSL_BSP_CB_LAST ; i++)
|
||||
dsl_bsp_event_callback[i].function = NULL;
|
||||
@ -2992,29 +2743,40 @@ IFX_MEI_ModuleInit (void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __exit
|
||||
IFX_MEI_ModuleExit (void)
|
||||
static int __devexit ltq_mei_remove(struct platform_device *pdev)
|
||||
{
|
||||
int i = 0;
|
||||
int num;
|
||||
|
||||
for (num = 0; num < BSP_MAX_DEVICES; num++) {
|
||||
IFX_MEI_CleanUpDevNode (num);
|
||||
#ifdef CONFIG_PROC_FS
|
||||
for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
|
||||
remove_proc_entry (regs[num][i].name, meidir);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
remove_proc_entry (MEI_DIRNAME, NULL);
|
||||
for (i = 0; i < BSP_MAX_DEVICES; i++) {
|
||||
for (i = 0; i < BSP_MAX_DEVICES; i++) {
|
||||
IFX_MEI_ExitDevice (i);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id ltq_mei_match[] = {
|
||||
{ .compatible = "lantiq,mei-xway"},
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver ltq_mei_driver = {
|
||||
.probe = ltq_mei_probe,
|
||||
.remove = __devexit_p(ltq_mei_remove),
|
||||
.driver = {
|
||||
.name = "lantiq,mei-xway",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = ltq_mei_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(ltq_mei_driver);
|
||||
|
||||
/* export function for DSL Driver */
|
||||
|
||||
/* The functions of MEI_DriverHandleGet and MEI_DriverHandleDelete are
|
||||
@ -3040,7 +2802,4 @@ EXPORT_SYMBOL (DSL_BSP_SendCMV);
|
||||
EXPORT_SYMBOL (DSL_BSP_EventCBRegister);
|
||||
EXPORT_SYMBOL (DSL_BSP_EventCBUnregister);
|
||||
|
||||
module_init (IFX_MEI_ModuleInit);
|
||||
module_exit (IFX_MEI_ModuleExit);
|
||||
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
@ -8,9 +8,9 @@
|
||||
include $(TOPDIR)/rules.mk
|
||||
include $(INCLUDE_DIR)/kernel.mk
|
||||
|
||||
PKG_NAME:=ltq-dsl
|
||||
PKG_NAME:=ltq-adsl
|
||||
PKG_VERSION:=3.24.4.4
|
||||
PKG_RELEASE:=4
|
||||
PKG_RELEASE:=1
|
||||
PKG_SOURCE:=drv_dsl_cpe_api_danube-$(PKG_VERSION).tar.gz
|
||||
PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/ltq-dsl-$(BUILD_VARIANT)/drv_dsl_cpe_api-$(PKG_VERSION)
|
||||
PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/
|
||||
@ -19,23 +19,21 @@ PKG_MAINTAINER:=John Crispin <blogic@openwrt.org>
|
||||
|
||||
include $(INCLUDE_DIR)/package.mk
|
||||
|
||||
define KernelPackage/ltq-dsl-template
|
||||
define KernelPackage/ltq-adsl-template
|
||||
SECTION:=sys
|
||||
CATEGORY:=Kernel modules
|
||||
SUBMENU:=Network Devices
|
||||
TITLE:=Lantiq dsl driver for $(1)
|
||||
TITLE:=adsl driver for $(1)
|
||||
URL:=http://www.lantiq.com/
|
||||
VARIANT:=$(1)
|
||||
DEPENDS:=@(TARGET_lantiq_$(1)||TARGET_lantiq_$(2)) +kmod-atm
|
||||
FILES:=$(PKG_BUILD_DIR)/src/mei/lantiq_mei.ko \
|
||||
$(PKG_BUILD_DIR)/src/drv_dsl_cpe_api.ko \
|
||||
$(PKG_BUILD_DIR)/src/mei/lantiq_atm.ko
|
||||
AUTOLOAD:=$(call AutoLoad,50,lantiq_mei drv_dsl_cpe_api lantiq_atm)
|
||||
DEPENDS:=@TARGET_lantiq_$(2) +kmod-ltq-adsl-$(1)-mei
|
||||
FILES:=$(PKG_BUILD_DIR)/src/drv_dsl_cpe_api.ko
|
||||
AUTOLOAD:=$(call AutoLoad,51,drv_dsl_cpe_api)
|
||||
endef
|
||||
|
||||
KernelPackage/ltq-dsl-danube=$(call KernelPackage/ltq-dsl-template,danube,xway)
|
||||
KernelPackage/ltq-dsl-ar9=$(call KernelPackage/ltq-dsl-template,ar9,xway)
|
||||
KernelPackage/ltq-dsl-ase=$(call KernelPackage/ltq-dsl-template,ase,ase)
|
||||
KernelPackage/ltq-adsl-danube=$(call KernelPackage/ltq-adsl-template,danube,xway)
|
||||
KernelPackage/ltq-adsl-ar9=$(call KernelPackage/ltq-adsl-template,ar9,xway)
|
||||
KernelPackage/ltq-adsl-ase=$(call KernelPackage/ltq-adsl-template,ase,ase)
|
||||
|
||||
define KernelPackage/ltq-dsl/config
|
||||
source "$(SOURCE)/Config.in"
|
||||
@ -83,39 +81,16 @@ endif
|
||||
|
||||
EXTRA_CFLAGS = -fno-pic -mno-abicalls -mlong-calls -G 0
|
||||
|
||||
define Build/Prepare
|
||||
$(PKG_UNPACK)
|
||||
$(Build/Patch)
|
||||
$(INSTALL_DIR) $(PKG_BUILD_DIR)/src/mei/
|
||||
$(CP) ./src/* $(PKG_BUILD_DIR)/src/mei/
|
||||
endef
|
||||
|
||||
define Build/Configure
|
||||
(cd $(PKG_BUILD_DIR); aclocal && autoconf && automake)
|
||||
$(call Build/Configure/Default)
|
||||
endef
|
||||
|
||||
define Build/Compile
|
||||
cd $(LINUX_DIR); \
|
||||
ARCH=mips CROSS_COMPILE="$(KERNEL_CROSS)" \
|
||||
$(MAKE) BUILD_VARIANT=$(BUILD_VARIANT) M=$(PKG_BUILD_DIR)/src/mei/ V=1 modules
|
||||
$(call Build/Compile/Default)
|
||||
endef
|
||||
|
||||
define Build/InstallDev
|
||||
$(INSTALL_DIR) $(1)/usr/include
|
||||
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api.h $(1)/usr/include
|
||||
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_ioctl.h $(1)/usr/include
|
||||
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_adslmib.h $(1)/usr/include
|
||||
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_adslmib_ioctl.h $(1)/usr/include
|
||||
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_g997.h $(1)/usr/include
|
||||
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_types.h $(1)/usr/include
|
||||
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_pm.h $(1)/usr/include
|
||||
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_error.h $(1)/usr/include
|
||||
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_danube_ctx.h $(1)/usr/include
|
||||
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_cmv_danube.h $(1)/usr/include
|
||||
$(INSTALL_DIR) $(1)/usr/include/adsl
|
||||
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_*.h $(1)/usr/include/adsl/
|
||||
endef
|
||||
|
||||
$(eval $(call KernelPackage,ltq-dsl-danube))
|
||||
$(eval $(call KernelPackage,ltq-dsl-ase))
|
||||
$(eval $(call KernelPackage,ltq-dsl-ar9))
|
||||
$(eval $(call KernelPackage,ltq-adsl-danube))
|
||||
$(eval $(call KernelPackage,ltq-adsl-ase))
|
||||
$(eval $(call KernelPackage,ltq-adsl-ar9))
|
||||
1065
package/platform/lantiq/ltq-adsl/patches/100-dsl_compat.patch
Normal file
1065
package/platform/lantiq/ltq-adsl/patches/100-dsl_compat.patch
Normal file
File diff suppressed because it is too large
Load Diff
72
package/platform/lantiq/ltq-adsl/patches/120-platform.patch
Normal file
72
package/platform/lantiq/ltq-adsl/patches/120-platform.patch
Normal file
@ -0,0 +1,72 @@
|
||||
Index: drv_dsl_cpe_api-3.24.4.4/src/common/drv_dsl_cpe_os_linux.c
|
||||
===================================================================
|
||||
--- drv_dsl_cpe_api-3.24.4.4.orig/src/common/drv_dsl_cpe_os_linux.c 2012-12-07 21:22:58.020256076 +0100
|
||||
+++ drv_dsl_cpe_api-3.24.4.4/src/common/drv_dsl_cpe_os_linux.c 2012-12-07 21:31:13.156268489 +0100
|
||||
@@ -12,6 +12,7 @@
|
||||
|
||||
#define DSL_INTERN
|
||||
#include <linux/device.h>
|
||||
+#include <linux/platform_device.h>
|
||||
|
||||
#include "drv_dsl_cpe_api.h"
|
||||
#include "drv_dsl_cpe_api_ioctl.h"
|
||||
@@ -1063,7 +1064,7 @@
|
||||
#endif
|
||||
|
||||
/* Entry point of driver */
|
||||
-int __init DSL_ModuleInit(void)
|
||||
+static int __devinit ltq_adsl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct class *dsl_class;
|
||||
DSL_int_t i;
|
||||
@@ -1117,7 +1118,7 @@
|
||||
return 0;
|
||||
}
|
||||
|
||||
-void __exit DSL_ModuleCleanup(void)
|
||||
+static int __devexit ltq_adsl_remove(struct platform_device *pdev)
|
||||
{
|
||||
printk("Module will be unloaded"DSL_DRV_CRLF);
|
||||
|
||||
@@ -1132,7 +1133,7 @@
|
||||
(DSL_uint8_t**)&g_BndFpgaBase);
|
||||
#endif /* defined(INCLUDE_DSL_CPE_API_VINAX) && defined(INCLUDE_DSL_BONDING)*/
|
||||
|
||||
- return;
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
#ifndef _lint
|
||||
@@ -1148,8 +1149,30 @@
|
||||
MODULE_PARM_DESC(debug_level, "set to get more (1) or fewer (4) debug outputs");
|
||||
#endif /* #ifndef DSL_DEBUG_DISABLE*/
|
||||
|
||||
-module_init(DSL_ModuleInit);
|
||||
-module_exit(DSL_ModuleCleanup);
|
||||
+static const struct of_device_id ltq_adsl_match[] = {
|
||||
+#ifdef CONFIG_DANUBE
|
||||
+ { .compatible = "lantiq,adsl-danube"},
|
||||
+#elif defined CONFIG_AMAZON_SE
|
||||
+ { .compatible = "lantiq,adsl-ase"},
|
||||
+#elif defined CONFIG_AR9
|
||||
+ { .compatible = "lantiq,adsl-arx100"},
|
||||
+#endif
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, ltq_adsl_match);
|
||||
+
|
||||
+static struct platform_driver ltq_adsl_driver = {
|
||||
+ .probe = ltq_adsl_probe,
|
||||
+ .remove = __devexit_p(ltq_adsl_remove),
|
||||
+ .driver = {
|
||||
+ .name = "adsl",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = ltq_adsl_match,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(ltq_adsl_driver);
|
||||
+
|
||||
#endif /* #ifndef _lint*/
|
||||
|
||||
//EXPORT_SYMBOL(DSL_ModuleInit);
|
||||
51
package/platform/lantiq/ltq-atm/Makefile
Normal file
51
package/platform/lantiq/ltq-atm/Makefile
Normal file
@ -0,0 +1,51 @@
|
||||
# Copyright (C) 2012 OpenWrt.org
|
||||
#
|
||||
# This is free software, licensed under the GNU General Public License v2.
|
||||
# See /LICENSE for more information.
|
||||
|
||||
include $(TOPDIR)/rules.mk
|
||||
include $(INCLUDE_DIR)/kernel.mk
|
||||
|
||||
PKG_NAME:=ltq-atm
|
||||
PKG_RELEASE:=1
|
||||
PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/ltq-atm-$(BUILD_VARIANT)
|
||||
|
||||
PKG_MAINTAINER:=John Crispin <blogic@openwrt.org>
|
||||
|
||||
include $(INCLUDE_DIR)/package.mk
|
||||
|
||||
define KernelPackage/ltq-atm-template
|
||||
SECTION:=sys
|
||||
CATEGORY:=Kernel modules
|
||||
SUBMENU:=Network Devices
|
||||
TITLE:=atm driver for $(1)
|
||||
URL:=http://www.lantiq.com/
|
||||
VARIANT:=$(1)
|
||||
DEPENDS:=@TARGET_lantiq_$(2) +kmod-atm +br2684ctl
|
||||
FILES:=$(PKG_BUILD_DIR)/ltq_atm_$(1).ko
|
||||
AUTOLOAD:=$(call AutoLoad,52,ltq_atm_$(1))
|
||||
endef
|
||||
|
||||
KernelPackage/ltq-atm-danube=$(call KernelPackage/ltq-atm-template,danube,xway)
|
||||
KernelPackage/ltq-atm-ar9=$(call KernelPackage/ltq-atm-template,ar9,xway)
|
||||
KernelPackage/ltq-atm-ase=$(call KernelPackage/ltq-atm-template,ase,ase)
|
||||
KernelPackage/ltq-atm-vr9=$(call KernelPackage/ltq-atm-template,vr9,xway)
|
||||
|
||||
define Build/Prepare
|
||||
$(INSTALL_DIR) $(PKG_BUILD_DIR)
|
||||
$(CP) ./src/* $(PKG_BUILD_DIR)
|
||||
endef
|
||||
|
||||
define Build/Configure
|
||||
endef
|
||||
|
||||
define Build/Compile
|
||||
cd $(LINUX_DIR); \
|
||||
ARCH=mips CROSS_COMPILE="$(KERNEL_CROSS)" \
|
||||
$(MAKE) BUILD_VARIANT=$(BUILD_VARIANT) M=$(PKG_BUILD_DIR) V=1 modules
|
||||
endef
|
||||
|
||||
$(eval $(call KernelPackage,ltq-atm-danube))
|
||||
$(eval $(call KernelPackage,ltq-atm-ase))
|
||||
$(eval $(call KernelPackage,ltq-atm-ar9))
|
||||
$(eval $(call KernelPackage,ltq-atm-vr9))
|
||||
23
package/platform/lantiq/ltq-atm/src/Makefile
Normal file
23
package/platform/lantiq/ltq-atm/src/Makefile
Normal file
@ -0,0 +1,23 @@
|
||||
ifeq ($(BUILD_VARIANT),danube)
|
||||
CFLAGS_MODULE = -DCONFIG_DANUBE
|
||||
obj-m = ltq_atm_danube.o
|
||||
ltq_atm_danube-objs = ltq_atm.o ifxmips_atm_danube.o
|
||||
endif
|
||||
|
||||
ifeq ($(BUILD_VARIANT),ase)
|
||||
CFLAGS_MODULE = -DCONFIG_AMAZON_SE
|
||||
obj-m = ltq_atm_ase.o
|
||||
ltq_atm_ase-objs = ltq_atm.o ifxmips_atm_amazon_se.o
|
||||
endif
|
||||
|
||||
ifeq ($(BUILD_VARIANT),ar9)
|
||||
CFLAGS_MODULE = -DCONFIG_AR9
|
||||
obj-m = ltq_atm_ar9.o
|
||||
ltq_atm_ar9-objs = ltq_atm.o ifxmips_atm_ar9.o
|
||||
endif
|
||||
|
||||
ifeq ($(BUILD_VARIANT),vr9)
|
||||
CFLAGS_MODULE = -DCONFIG_VR9
|
||||
obj-m = ltq_atm_vr9.o
|
||||
ltq_atm_vr9-objs = ltq_atm.o ifxmips_atm_vr9.o
|
||||
endif
|
||||
@ -40,17 +40,23 @@
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioctl.h>
|
||||
#include <linux/clk.h>
|
||||
#include <asm/delay.h>
|
||||
|
||||
/*
|
||||
* Chip Specific Head File
|
||||
*/
|
||||
#include <lantiq_soc.h>
|
||||
#include "ifxmips_compat.h"
|
||||
#include "ifxmips_atm_core.h"
|
||||
#include "ifxmips_atm_fw_amazon_se.h"
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
||||
#define EMA_CMD_BUF_LEN 0x0040
|
||||
#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
|
||||
#define EMA_DATA_BUF_LEN 0x0100
|
||||
#define EMA_DATA_BASE_ADDR (0x00001900 << 2)
|
||||
#define EMA_WRITE_BURST 0x2
|
||||
#define EMA_READ_BURST 0x2
|
||||
|
||||
|
||||
|
||||
/*
|
||||
@ -103,6 +109,12 @@ static inline void clear_share_buffer(void);
|
||||
* Local Function
|
||||
* ####################################
|
||||
*/
|
||||
#define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
|
||||
#define IFX_PMU_MODULE_PPE_TC BIT(21)
|
||||
#define IFX_PMU_MODULE_PPE_EMA BIT(22)
|
||||
#define IFX_PMU_MODULE_PPE_QSB BIT(18)
|
||||
#define IFX_PMU_MODULE_TPE BIT(13)
|
||||
#define IFX_PMU_MODULE_DSL_DFE BIT(9)
|
||||
|
||||
static inline void init_pmu(void)
|
||||
{
|
||||
@ -114,27 +126,28 @@ static inline void init_pmu(void)
|
||||
//PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
|
||||
struct clk *clk = clk_get_sys("ltq_dsl", NULL);
|
||||
clk_enable(clk);
|
||||
ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
|
||||
IFX_PMU_MODULE_PPE_TC |
|
||||
IFX_PMU_MODULE_PPE_EMA |
|
||||
IFX_PMU_MODULE_TPE |
|
||||
IFX_PMU_MODULE_DSL_DFE);
|
||||
}
|
||||
|
||||
static inline void uninit_pmu(void)
|
||||
{
|
||||
/* PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
/*PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
//PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
//PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);*/
|
||||
struct clk *clk = clk_get_sys("ltq_dsl", NULL);
|
||||
clk_disable(clk);
|
||||
}
|
||||
|
||||
static inline void reset_ppe(void)
|
||||
{
|
||||
#ifdef MODULE
|
||||
/* unsigned int etop_cfg;
|
||||
#if 0 //MODULE
|
||||
unsigned int etop_cfg;
|
||||
unsigned int etop_mdio_cfg;
|
||||
unsigned int etop_ig_plen_ctrl;
|
||||
unsigned int enet_mac_cfg;
|
||||
@ -152,7 +165,7 @@ static inline void reset_ppe(void)
|
||||
*IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
|
||||
*IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
|
||||
*IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
|
||||
*IFX_PP32_ETOP_CFG = etop_cfg;*/
|
||||
*IFX_PP32_ETOP_CFG = etop_cfg;
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -211,7 +224,7 @@ static inline void clear_share_buffer(void)
|
||||
* src --- u32 *, binary code buffer
|
||||
* dword_len --- unsigned int, binary code length in DWORD (32-bit)
|
||||
* Output:
|
||||
* int --- IFX_SUCCESS: Success
|
||||
* int --- 0: Success
|
||||
* else: Error Code
|
||||
*/
|
||||
static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
|
||||
@ -220,7 +233,7 @@ static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len,
|
||||
|
||||
if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
|
||||
|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
|
||||
return IFX_ERROR;
|
||||
return -1;
|
||||
|
||||
if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
|
||||
IFX_REG_W32(0x00, CDM_CFG);
|
||||
@ -237,7 +250,7 @@ static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len,
|
||||
while ( data_dword_len-- > 0 )
|
||||
IFX_REG_W32(*data_src++, dest++);
|
||||
|
||||
return IFX_SUCCESS;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -248,21 +261,16 @@ static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len,
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
|
||||
extern void ase_fw_ver(unsigned int *major, unsigned int *minor)
|
||||
{
|
||||
ASSERT(major != NULL, "pointer is NULL");
|
||||
ASSERT(minor != NULL, "pointer is NULL");
|
||||
|
||||
#ifdef VER_IN_FIRMWARE
|
||||
*major = FW_VER_ID->major;
|
||||
*minor = FW_VER_ID->minor;
|
||||
#else
|
||||
*major = ATM_FW_VER_MAJOR;
|
||||
*minor = ATM_FW_VER_MINOR;
|
||||
#endif
|
||||
}
|
||||
|
||||
void ifx_atm_init_chip(void)
|
||||
void ase_init(void)
|
||||
{
|
||||
init_pmu();
|
||||
|
||||
@ -277,7 +285,7 @@ void ifx_atm_init_chip(void)
|
||||
clear_share_buffer();
|
||||
}
|
||||
|
||||
void ifx_atm_uninit_chip(void)
|
||||
void ase_shutdown(void)
|
||||
{
|
||||
uninit_pmu();
|
||||
}
|
||||
@ -288,16 +296,16 @@ void ifx_atm_uninit_chip(void)
|
||||
* Input:
|
||||
* none
|
||||
* Output:
|
||||
* int --- IFX_SUCCESS: Success
|
||||
* int --- 0: Success
|
||||
* else: Error Code
|
||||
*/
|
||||
int ifx_pp32_start(int pp32)
|
||||
int ase_start(int pp32)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* download firmware */
|
||||
ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
|
||||
if ( ret != IFX_SUCCESS )
|
||||
if ( ret != 0 )
|
||||
return ret;
|
||||
|
||||
/* run PP32 */
|
||||
@ -306,7 +314,7 @@ int ifx_pp32_start(int pp32)
|
||||
/* idle for a while to let PP32 init itself */
|
||||
udelay(10);
|
||||
|
||||
return IFX_SUCCESS;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -317,8 +325,17 @@ int ifx_pp32_start(int pp32)
|
||||
* Output:
|
||||
* none
|
||||
*/
|
||||
void ifx_pp32_stop(int pp32)
|
||||
void ase_stop(int pp32)
|
||||
{
|
||||
/* halt PP32 */
|
||||
IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL);
|
||||
}
|
||||
|
||||
struct ltq_atm_ops ase_ops = {
|
||||
.init = ase_init,
|
||||
.shutdown = ase_shutdown,
|
||||
.start = ase_start,
|
||||
.stop = ase_stop,
|
||||
.fw_ver = ase_fw_ver,
|
||||
};
|
||||
|
||||
@ -40,23 +40,17 @@
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioctl.h>
|
||||
#include <linux/clk.h>
|
||||
#include <asm/delay.h>
|
||||
|
||||
/*
|
||||
* Chip Specific Head File
|
||||
*/
|
||||
#include <lantiq_soc.h>
|
||||
#include "ifxmips_compat.h"
|
||||
#define IFX_MEI_BSP 1
|
||||
#include "ifxmips_mei_interface.h"
|
||||
#include "ifxmips_atm_core.h"
|
||||
#include "ifxmips_atm_ppe_common.h"
|
||||
#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
|
||||
#include "ifxmips_atm_fw_ar9_retx.h"
|
||||
#else
|
||||
#include "ifxmips_atm_fw_ar9.h"
|
||||
#endif
|
||||
|
||||
#include "ifxmips_atm_fw_ar9.h"
|
||||
#include "ifxmips_atm_fw_regs_ar9.h"
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
||||
|
||||
|
||||
@ -92,7 +86,6 @@ static inline void uninit_pmu(void);
|
||||
static inline void reset_ppe(void);
|
||||
static inline void init_ema(void);
|
||||
static inline void init_mailbox(void);
|
||||
static inline void init_atm_tc(void);
|
||||
static inline void clear_share_buffer(void);
|
||||
|
||||
|
||||
@ -111,38 +104,32 @@ static inline void clear_share_buffer(void);
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
#define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
|
||||
#define IFX_PMU_MODULE_PPE_TC BIT(21)
|
||||
#define IFX_PMU_MODULE_PPE_EMA BIT(22)
|
||||
#define IFX_PMU_MODULE_PPE_QSB BIT(18)
|
||||
#define IFX_PMU_MODULE_TPE BIT(13)
|
||||
#define IFX_PMU_MODULE_DSL_DFE BIT(9)
|
||||
|
||||
static inline void init_pmu(void)
|
||||
{
|
||||
//*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
|
||||
//PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
/* PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
|
||||
struct clk *clk = clk_get_sys("ltq_dsl", NULL);
|
||||
clk_enable(clk);
|
||||
ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
|
||||
IFX_PMU_MODULE_PPE_TC |
|
||||
IFX_PMU_MODULE_PPE_EMA |
|
||||
IFX_PMU_MODULE_PPE_QSB |
|
||||
IFX_PMU_MODULE_TPE |
|
||||
IFX_PMU_MODULE_DSL_DFE);
|
||||
}
|
||||
|
||||
static inline void uninit_pmu(void)
|
||||
{
|
||||
/* PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);*/
|
||||
//PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
struct clk *clk = clk_get_sys("ltq_dsl", NULL);
|
||||
clk_disable(clk);
|
||||
}
|
||||
|
||||
static inline void reset_ppe(void)
|
||||
{
|
||||
#ifdef MODULE
|
||||
// reset PPE
|
||||
//ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
|
||||
// ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -162,10 +149,6 @@ static inline void init_mailbox(void)
|
||||
IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
|
||||
}
|
||||
|
||||
static inline void init_atm_tc(void)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void clear_share_buffer(void)
|
||||
{
|
||||
volatile u32 *p = SB_RAM0_ADDR(0);
|
||||
@ -175,23 +158,13 @@ static inline void clear_share_buffer(void)
|
||||
IFX_REG_W32(0, p++);
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Download PPE firmware binary code.
|
||||
* Input:
|
||||
* src --- u32 *, binary code buffer
|
||||
* dword_len --- unsigned int, binary code length in DWORD (32-bit)
|
||||
* Output:
|
||||
* int --- IFX_SUCCESS: Success
|
||||
* else: Error Code
|
||||
*/
|
||||
static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
|
||||
{
|
||||
volatile u32 *dest;
|
||||
|
||||
if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
|
||||
|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
|
||||
return IFX_ERROR;
|
||||
return -1;
|
||||
|
||||
if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
|
||||
IFX_REG_W32(0x00, CDM_CFG);
|
||||
@ -208,88 +181,64 @@ static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len,
|
||||
while ( data_dword_len-- > 0 )
|
||||
IFX_REG_W32(*data_src++, dest++);
|
||||
|
||||
return IFX_SUCCESS;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Global Function
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
|
||||
void ar9_fw_ver(unsigned int *major, unsigned int *minor)
|
||||
{
|
||||
ASSERT(major != NULL, "pointer is NULL");
|
||||
ASSERT(minor != NULL, "pointer is NULL");
|
||||
|
||||
#if (defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX) || defined(VER_IN_FIRMWARE)
|
||||
*major = FW_VER_ID->major;
|
||||
*minor = FW_VER_ID->minor;
|
||||
#else
|
||||
*major = ATM_FW_VER_MAJOR;
|
||||
*minor = ATM_FW_VER_MINOR;
|
||||
#endif
|
||||
}
|
||||
|
||||
void ifx_atm_init_chip(void)
|
||||
void ar9_init(void)
|
||||
{
|
||||
init_pmu();
|
||||
|
||||
reset_ppe();
|
||||
|
||||
init_ema();
|
||||
|
||||
init_mailbox();
|
||||
|
||||
init_atm_tc();
|
||||
|
||||
clear_share_buffer();
|
||||
init_pmu();
|
||||
reset_ppe();
|
||||
init_ema();
|
||||
init_mailbox();
|
||||
clear_share_buffer();
|
||||
}
|
||||
|
||||
void ifx_atm_uninit_chip(void)
|
||||
void ar9_shutdown(void)
|
||||
{
|
||||
uninit_pmu();
|
||||
ltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01 |
|
||||
IFX_PMU_MODULE_PPE_TC |
|
||||
IFX_PMU_MODULE_PPE_EMA |
|
||||
IFX_PMU_MODULE_PPE_QSB |
|
||||
IFX_PMU_MODULE_TPE |
|
||||
IFX_PMU_MODULE_DSL_DFE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Initialize and start up PP32.
|
||||
* Input:
|
||||
* none
|
||||
* Output:
|
||||
* int --- IFX_SUCCESS: Success
|
||||
* else: Error Code
|
||||
*/
|
||||
int ifx_pp32_start(int pp32)
|
||||
int ar9_start(int pp32)
|
||||
{
|
||||
int ret;
|
||||
int ret;
|
||||
|
||||
/* download firmware */
|
||||
ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
|
||||
if ( ret != IFX_SUCCESS )
|
||||
return ret;
|
||||
ret = pp32_download_code(ar9_fw_bin, sizeof(ar9_fw_bin) / sizeof(*ar9_fw_bin),
|
||||
ar9_fw_data, sizeof(ar9_fw_data) / sizeof(*ar9_fw_data));
|
||||
if ( ret != 0 )
|
||||
return ret;
|
||||
|
||||
/* run PP32 */
|
||||
IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));
|
||||
IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));
|
||||
|
||||
/* idle for a while to let PP32 init itself */
|
||||
udelay(10);
|
||||
udelay(10);
|
||||
|
||||
return IFX_SUCCESS;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Halt PP32.
|
||||
* Input:
|
||||
* none
|
||||
* Output:
|
||||
* none
|
||||
*/
|
||||
void ifx_pp32_stop(int pp32)
|
||||
void ar9_stop(int pp32)
|
||||
{
|
||||
/* halt PP32 */
|
||||
IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));
|
||||
IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));
|
||||
}
|
||||
|
||||
struct ltq_atm_ops ar9_ops = {
|
||||
.init = ar9_init,
|
||||
.shutdown = ar9_shutdown,
|
||||
.start = ar9_start,
|
||||
.stop = ar9_stop,
|
||||
.fw_ver = ar9_fw_ver,
|
||||
};
|
||||
|
||||
|
||||
@ -25,12 +25,25 @@
|
||||
#define IFXMIPS_ATM_CORE_H
|
||||
|
||||
|
||||
#include "ifxmips_compat.h"
|
||||
#include "ifx_atm.h"
|
||||
#include "ifxmips_atm_ppe_common.h"
|
||||
#include "ifxmips_atm_fw_regs_common.h"
|
||||
#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24)
|
||||
#define INT_NUM_IM2_IRL13 (INT_NUM_IM2_IRL0 + 13)
|
||||
#define CONFIG_IFXMIPS_DSL_CPE_MEI
|
||||
#define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r))
|
||||
#define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r))
|
||||
#define IFX_REG_W32_MASK(_clr, _set, _r) IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r))
|
||||
#define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
|
||||
|
||||
struct ltq_atm_ops {
|
||||
void (*init)(void);
|
||||
void (*shutdown)(void);
|
||||
|
||||
int (*start)(int pp32);
|
||||
void (*stop)(int pp32);
|
||||
|
||||
void (*fw_ver)(unsigned int *major, unsigned int *minor);
|
||||
};
|
||||
|
||||
#include <lantiq_atm.h>
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
@ -74,6 +87,8 @@
|
||||
* Debug/Assert/Error Message
|
||||
*/
|
||||
|
||||
#define ifx_atm_dbg_enable 1
|
||||
|
||||
#define DBG_ENABLE_MASK_ERR (1 << 0)
|
||||
#define DBG_ENABLE_MASK_DEBUG_PRINT (1 << 1)
|
||||
#define DBG_ENABLE_MASK_ASSERT (1 << 2)
|
||||
@ -84,17 +99,6 @@
|
||||
#define DBG_ENABLE_MASK_MAC_SWAP (1 << 12)
|
||||
#define DBG_ENABLE_MASK_ALL (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT | DBG_ENABLE_MASK_MAC_SWAP)
|
||||
|
||||
#define err(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
|
||||
|
||||
#if defined(ENABLE_DEBUG) && ENABLE_DEBUG
|
||||
#undef dbg
|
||||
#define dbg(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ) printk(KERN_WARNING __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
|
||||
#else
|
||||
#if !defined(dbg)
|
||||
#define dbg(format, arg...)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(ENABLE_ASSERT) && ENABLE_ASSERT
|
||||
#define ASSERT(cond, format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
|
||||
#else
|
||||
@ -129,7 +133,7 @@
|
||||
#define RX_DMA_CH_AAL 1
|
||||
#define RX_DMA_CH_TOTAL 2
|
||||
#define RX_DMA_CH_OAM_DESC_LEN 32
|
||||
#define RX_DMA_CH_OAM_BUF_SIZE (CELL_SIZE & ~15)
|
||||
#define RX_DMA_CH_OAM_BUF_SIZE ((CELL_SIZE + 14) & ~15)
|
||||
#define RX_DMA_CH_AAL_BUF_SIZE (2048 - 48)
|
||||
|
||||
/*
|
||||
@ -164,14 +168,8 @@
|
||||
#define TX_INBAND_HEADER_LENGTH 8
|
||||
#define MAX_TX_FRAME_EXTRA_BYTES (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES)
|
||||
|
||||
/*
|
||||
* Cell Constant
|
||||
*/
|
||||
#define CELL_SIZE ATM_AAL0_SDU
|
||||
|
||||
/*
|
||||
* ReTX Constant
|
||||
*/
|
||||
#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
|
||||
#define RETX_PLAYOUT_BUFFER_ORDER 6
|
||||
#define RETX_PLAYOUT_BUFFER_SIZE (PAGE_SIZE * (1 << RETX_PLAYOUT_BUFFER_ORDER))
|
||||
@ -179,93 +177,69 @@
|
||||
#define RETX_POLLING_INTERVAL (HZ / 100 > 0 ? HZ / 100 : 1)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Data Type
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
unsigned int h;
|
||||
unsigned int l;
|
||||
unsigned int h;
|
||||
unsigned int l;
|
||||
} ppe_u64_t;
|
||||
|
||||
struct port {
|
||||
unsigned int tx_max_cell_rate;
|
||||
unsigned int tx_current_cell_rate;
|
||||
unsigned int tx_max_cell_rate;
|
||||
unsigned int tx_current_cell_rate;
|
||||
|
||||
struct atm_dev *dev;
|
||||
struct atm_dev *dev;
|
||||
};
|
||||
|
||||
struct connection {
|
||||
struct atm_vcc *vcc;
|
||||
struct atm_vcc *vcc;
|
||||
|
||||
volatile struct tx_descriptor
|
||||
*tx_desc;
|
||||
unsigned int tx_desc_pos;
|
||||
struct sk_buff **tx_skb;
|
||||
volatile struct tx_descriptor *tx_desc;
|
||||
unsigned int tx_desc_pos;
|
||||
struct sk_buff **tx_skb;
|
||||
|
||||
unsigned int aal5_vcc_crc_err; /* number of packets with CRC error */
|
||||
unsigned int aal5_vcc_oversize_sdu; /* number of packets with oversize error */
|
||||
unsigned int aal5_vcc_crc_err; /* number of packets with CRC error */
|
||||
unsigned int aal5_vcc_oversize_sdu; /* number of packets with oversize error */
|
||||
|
||||
unsigned int port;
|
||||
unsigned int port;
|
||||
};
|
||||
|
||||
struct atm_priv_data {
|
||||
unsigned long conn_table;
|
||||
struct connection conn[MAX_PVC_NUMBER];
|
||||
unsigned long conn_table;
|
||||
struct connection conn[MAX_PVC_NUMBER];
|
||||
|
||||
volatile struct rx_descriptor
|
||||
*aal_desc;
|
||||
unsigned int aal_desc_pos;
|
||||
volatile struct rx_descriptor *aal_desc;
|
||||
unsigned int aal_desc_pos;
|
||||
|
||||
volatile struct rx_descriptor
|
||||
*oam_desc;
|
||||
unsigned char *oam_buf;
|
||||
unsigned int oam_desc_pos;
|
||||
volatile struct rx_descriptor *oam_desc;
|
||||
unsigned char *oam_buf;
|
||||
unsigned int oam_desc_pos;
|
||||
|
||||
struct port port[ATM_PORT_NUMBER];
|
||||
struct port port[ATM_PORT_NUMBER];
|
||||
|
||||
unsigned int wrx_pdu; /* successfully received AAL5 packet */
|
||||
unsigned int wrx_drop_pdu; /* AAL5 packet dropped by driver on RX */
|
||||
unsigned int wtx_pdu; /* successfully tranmitted AAL5 packet */
|
||||
unsigned int wtx_err_pdu; /* error AAL5 packet */
|
||||
unsigned int wtx_drop_pdu; /* AAL5 packet dropped by driver on TX */
|
||||
unsigned int wrx_pdu; /* successfully received AAL5 packet */
|
||||
unsigned int wrx_drop_pdu; /* AAL5 packet dropped by driver on RX */
|
||||
unsigned int wtx_pdu; /* successfully transmitted AAL5 packet */
|
||||
unsigned int wtx_err_pdu; /* error AAL5 packet */
|
||||
unsigned int wtx_drop_pdu; /* AAL5 packet dropped by driver on TX */
|
||||
|
||||
ppe_u64_t wrx_total_byte;
|
||||
ppe_u64_t wtx_total_byte;
|
||||
unsigned int prev_wrx_total_byte;
|
||||
unsigned int prev_wtx_total_byte;
|
||||
unsigned int wrx_oam; /* successfully received OAM cell */
|
||||
unsigned int wrx_drop_oam; /* OAM cell dropped by driver on RX */
|
||||
unsigned int wtx_oam; /* successfully transmitted OAM cell */
|
||||
unsigned int wtx_err_oam; /* error during transmiting OAM cell */
|
||||
unsigned int wtx_drop_oam; /* OAM cell dropped by driver on TX */
|
||||
|
||||
void *aal_desc_base;
|
||||
void *oam_desc_base;
|
||||
void *oam_buf_base;
|
||||
void *tx_desc_base;
|
||||
void *tx_skb_base;
|
||||
ppe_u64_t wrx_total_byte;
|
||||
ppe_u64_t wtx_total_byte;
|
||||
unsigned int prev_wrx_total_byte;
|
||||
unsigned int prev_wtx_total_byte;
|
||||
|
||||
void *aal_desc_base;
|
||||
void *oam_desc_base;
|
||||
void *oam_buf_base;
|
||||
void *tx_desc_base;
|
||||
void *tx_skb_base;
|
||||
};
|
||||
|
||||
#include "ifxmips_atm_ppe_common.h"
|
||||
#include "ifxmips_atm_fw_regs_common.h"
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Declaration
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
extern unsigned int ifx_atm_dbg_enable;
|
||||
|
||||
extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor);
|
||||
|
||||
extern void ifx_atm_init_chip(void);
|
||||
extern void ifx_atm_uninit_chip(void);
|
||||
|
||||
extern int ifx_pp32_start(int pp32);
|
||||
extern void ifx_pp32_stop(int pp32);
|
||||
|
||||
extern void ifx_reset_ppe(void);
|
||||
|
||||
|
||||
|
||||
#endif // IFXMIPS_ATM_CORE_H
|
||||
#endif
|
||||
231
package/platform/lantiq/ltq-atm/src/ifxmips_atm_danube.c
Normal file
231
package/platform/lantiq/ltq-atm/src/ifxmips_atm_danube.c
Normal file
@ -0,0 +1,231 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_danube.c
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM
|
||||
**
|
||||
** DATE : 7 Jul 2009
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM driver common source file (core functions)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 07 JUL 2009 Xu Liang Init Version
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Head File
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* Common Head File
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioctl.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
/*
|
||||
* Chip Specific Head File
|
||||
*/
|
||||
#include "ifxmips_atm_core.h"
|
||||
|
||||
#ifdef CONFIG_DANUBE
|
||||
|
||||
#include "ifxmips_atm_fw_danube.h"
|
||||
#include "ifxmips_atm_fw_regs_danube.h"
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
||||
#define EMA_CMD_BUF_LEN 0x0040
|
||||
#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
|
||||
#define EMA_DATA_BUF_LEN 0x0100
|
||||
#define EMA_DATA_BASE_ADDR (0x00001900 << 2)
|
||||
#define EMA_WRITE_BURST 0x2
|
||||
#define EMA_READ_BURST 0x2
|
||||
|
||||
static inline void reset_ppe(void);
|
||||
|
||||
#define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
|
||||
#define IFX_PMU_MODULE_PPE_TC BIT(21)
|
||||
#define IFX_PMU_MODULE_PPE_EMA BIT(22)
|
||||
#define IFX_PMU_MODULE_PPE_QSB BIT(18)
|
||||
#define IFX_PMU_MODULE_TPE BIT(13)
|
||||
#define IFX_PMU_MODULE_DSL_DFE BIT(9)
|
||||
|
||||
static inline void reset_ppe(void)
|
||||
{
|
||||
/*#ifdef MODULE
|
||||
unsigned int etop_cfg;
|
||||
unsigned int etop_mdio_cfg;
|
||||
unsigned int etop_ig_plen_ctrl;
|
||||
unsigned int enet_mac_cfg;
|
||||
|
||||
etop_cfg = *IFX_PP32_ETOP_CFG;
|
||||
etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
|
||||
etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
|
||||
enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
|
||||
|
||||
*IFX_PP32_ETOP_CFG &= ~0x03C0;
|
||||
|
||||
// reset PPE
|
||||
ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
|
||||
|
||||
*IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
|
||||
*IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
|
||||
*IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
|
||||
*IFX_PP32_ETOP_CFG = etop_cfg;
|
||||
#endif*/
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Download PPE firmware binary code.
|
||||
* Input:
|
||||
* src --- u32 *, binary code buffer
|
||||
* dword_len --- unsigned int, binary code length in DWORD (32-bit)
|
||||
* Output:
|
||||
* int --- 0: Success
|
||||
* else: Error Code
|
||||
*/
|
||||
static inline int danube_pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
|
||||
{
|
||||
volatile u32 *dest;
|
||||
|
||||
if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
|
||||
|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
|
||||
return -1;
|
||||
|
||||
if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
|
||||
IFX_REG_W32(0x00, CDM_CFG);
|
||||
else
|
||||
IFX_REG_W32(0x04, CDM_CFG);
|
||||
|
||||
/* copy code */
|
||||
dest = CDM_CODE_MEMORY(0, 0);
|
||||
while ( code_dword_len-- > 0 )
|
||||
IFX_REG_W32(*code_src++, dest++);
|
||||
|
||||
/* copy data */
|
||||
dest = CDM_DATA_MEMORY(0, 0);
|
||||
while ( data_dword_len-- > 0 )
|
||||
IFX_REG_W32(*data_src++, dest++);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void danube_fw_ver(unsigned int *major, unsigned int *minor)
|
||||
{
|
||||
ASSERT(major != NULL, "pointer is NULL");
|
||||
ASSERT(minor != NULL, "pointer is NULL");
|
||||
|
||||
*major = FW_VER_ID->major;
|
||||
*minor = FW_VER_ID->minor;
|
||||
}
|
||||
|
||||
static void danube_init(void)
|
||||
{
|
||||
volatile u32 *p = SB_RAM0_ADDR(0);
|
||||
unsigned int i;
|
||||
|
||||
ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
|
||||
IFX_PMU_MODULE_PPE_TC |
|
||||
IFX_PMU_MODULE_PPE_EMA |
|
||||
IFX_PMU_MODULE_PPE_QSB |
|
||||
IFX_PMU_MODULE_TPE |
|
||||
IFX_PMU_MODULE_DSL_DFE);
|
||||
|
||||
reset_ppe();
|
||||
|
||||
/* init ema */
|
||||
IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
|
||||
IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
|
||||
IFX_REG_W32(0x000000FF, EMA_IER);
|
||||
IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
|
||||
|
||||
/* init mailbox */
|
||||
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
|
||||
IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
|
||||
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
|
||||
IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
|
||||
|
||||
/* init atm tc */
|
||||
IFX_REG_W32(0x0000, DREG_AT_CTRL);
|
||||
IFX_REG_W32(0x0000, DREG_AR_CTRL);
|
||||
IFX_REG_W32(0x0, DREG_AT_IDLE0);
|
||||
IFX_REG_W32(0x0, DREG_AT_IDLE1);
|
||||
IFX_REG_W32(0x0, DREG_AR_IDLE0);
|
||||
IFX_REG_W32(0x0, DREG_AR_IDLE1);
|
||||
IFX_REG_W32(0x40, RFBI_CFG);
|
||||
IFX_REG_W32(0x1600, SFSM_DBA0);
|
||||
IFX_REG_W32(0x1718, SFSM_DBA1);
|
||||
IFX_REG_W32(0x1830, SFSM_CBA0);
|
||||
IFX_REG_W32(0x1844, SFSM_CBA1);
|
||||
IFX_REG_W32(0x14014, SFSM_CFG0);
|
||||
IFX_REG_W32(0x14014, SFSM_CFG1);
|
||||
IFX_REG_W32(0x1858, FFSM_DBA0);
|
||||
IFX_REG_W32(0x18AC, FFSM_DBA1);
|
||||
IFX_REG_W32(0x10006, FFSM_CFG0);
|
||||
IFX_REG_W32(0x10006, FFSM_CFG1);
|
||||
IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
|
||||
IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
|
||||
|
||||
for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
|
||||
IFX_REG_W32(0, p++);
|
||||
}
|
||||
|
||||
static void danube_shutdown(void)
|
||||
{
|
||||
}
|
||||
|
||||
int danube_start(int pp32)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* download firmware */
|
||||
ret = danube_pp32_download_code(
|
||||
danube_fw_bin, sizeof(danube_fw_bin) / sizeof(*danube_fw_bin),
|
||||
danube_fw_data, sizeof(danube_fw_data) / sizeof(*danube_fw_data));
|
||||
if ( ret != 0 )
|
||||
return ret;
|
||||
|
||||
/* run PP32 */
|
||||
IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
|
||||
|
||||
/* idle for a while to let PP32 init itself */
|
||||
udelay(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void danube_stop(int pp32)
|
||||
{
|
||||
IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
|
||||
}
|
||||
|
||||
struct ltq_atm_ops danube_ops = {
|
||||
.init = danube_init,
|
||||
.shutdown = danube_shutdown,
|
||||
.start = danube_start,
|
||||
.stop = danube_stop,
|
||||
.fw_ver = danube_fw_ver,
|
||||
};
|
||||
|
||||
#endif
|
||||
457
package/platform/lantiq/ltq-atm/src/ifxmips_atm_fw_amazon_se.h
Normal file
457
package/platform/lantiq/ltq-atm/src/ifxmips_atm_fw_amazon_se.h
Normal file
@ -0,0 +1,457 @@
|
||||
#ifndef IFXMIPS_ATM_FW_AMAZON_SE_H
|
||||
#define IFXMIPS_ATM_FW_AMAZON_SE_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_fw_amazon_se.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM (ADSL)
|
||||
**
|
||||
** DATE : 1 AUG 2005
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM Driver (PP32 Firmware)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 4 AUG 2005 Xu Liang Initiate Version
|
||||
** 23 OCT 2006 Xu Liang Add GPL header.
|
||||
** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#define VER_IN_FIRMWARE 1
|
||||
|
||||
#define ATM_FW_VER_MAJOR 0
|
||||
#define ATM_FW_VER_MINOR 16
|
||||
|
||||
|
||||
static unsigned int firmware_binary_code[] = {
|
||||
0x800004b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000ffe0, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xc1000002, 0xd90c00f8, 0xc2000002, 0xda0800f9, 0x80004cc8, 0xc2000000, 0xda0800f9, 0x80004330,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x800042e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x800055a8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x800041e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xc0400000, 0xc0004840, 0xc88400f8, 0x80004988, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xc0400002, 0xc0004840, 0xc88400f8, 0x80004908, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xc3c00004, 0xdbc800f9, 0xc10c0002, 0xd90c00f8, 0x8000fee0, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xc10e0002, 0xd90c00f8, 0xc0004808, 0xc84000f8, 0x80004938, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xc3e1fffe, 0x597dfffe, 0x593dfe14, 0x900004d9, 0x00000000, 0x00000000, 0x00000000, 0x90cc0481,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xc3c00000, 0xdbc800f9, 0xc1400008, 0xc1900000, 0x71588000,
|
||||
0x14100100, 0xc140000a, 0xc1900002, 0x71588000, 0x14100100, 0xc140000c, 0xc1900004, 0x71588000,
|
||||
0x14100100, 0xc1400004, 0xc1900006, 0x71588000, 0x14100100, 0xc1400006, 0xc1900008, 0x71588000,
|
||||
0x14100100, 0xc140000e, 0xc190000a, 0x71588000, 0x14100100, 0xc1400000, 0xc190000c, 0x71588000,
|
||||
0x14100100, 0xc1400002, 0xc190000e, 0x71588000, 0x14100100, 0xc0400000, 0xc11c0000, 0xc000082c,
|
||||
0xcd05ce00, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0400002, 0xc11c0000, 0xc000082c, 0xcd05ce00,
|
||||
0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0000824, 0x00000000, 0xcbc000f9, 0xcb8000f9, 0xcb4000f9,
|
||||
0xcb0000f8, 0xc0004878, 0x5bfc4000, 0xcfc000f9, 0x5bb84000, 0xcf8000f9, 0x5b744000, 0xcf4000f9,
|
||||
0x5b304000, 0xcf0000f8, 0xc0000a10, 0x00000000, 0xcbc000f9, 0xcb8000f8, 0xc0004874, 0x5bfc4000,
|
||||
0xcfc000f9, 0x5bb84000, 0xcf8000f8, 0xc30001fe, 0xc000140a, 0xcf0000f8, 0xc3000000, 0x7f018000,
|
||||
0xc000042e, 0xcf0000f8, 0xc000040e, 0xcf0000f8, 0xc3c1fffe, 0xc000490e, 0xcfc00078, 0xc000492c,
|
||||
0xcfc00078, 0xc0004924, 0xcfc00038, 0xc0004912, 0xcfc00038, 0xc0004966, 0xcfc00038, 0xc0004968,
|
||||
0xcfc00078, 0xc000496a, 0xcfc00078, 0xc3c1fffe, 0xc00049a0, 0xcfc000f8, 0xc3c00000, 0xc2800020,
|
||||
0xc3000000, 0x7f018000, 0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb84a00, 0x5838000a, 0xcf0000f8,
|
||||
0x5bfc0002, 0xb7e8ffc8, 0x00000000, 0xc3c00000, 0xc2800010, 0x6ff86000, 0x47bdc000, 0x5bb84c80,
|
||||
0xc3400000, 0x58380004, 0xcb420078, 0x00000000, 0x58380008, 0xcf400078, 0x5bfc0002, 0xb7e8ffb0,
|
||||
0x00000000, 0xc3c00000, 0xc2800020, 0xc348001e, 0xc3000000, 0x7f018000, 0x6ff8a000, 0x6fd44000,
|
||||
0x4795c000, 0x47bdc000, 0x5bb85e00, 0x58380008, 0xcf408418, 0x5838000a, 0xcf0000f8, 0x5bfc0002,
|
||||
0xb7e8ffb0, 0x00000000, 0x00000000, 0xc3e06242, 0x5bfc0020, 0xc0004802, 0xcfc000f8, 0xc161fffe,
|
||||
0x5955fffe, 0x14140000, 0x00000000, 0xc1000000, 0xd91c00f8, 0xc3e01002, 0x5bfd88c0, 0xc3a00f88,
|
||||
0x5bb839a2, 0x99005fa8, 0xdbd800f8, 0xdb9800f9, 0x00000000, 0xc3c00000, 0xdf7f0038, 0xa7ccfff0,
|
||||
0xc3800000, 0xc00048c0, 0xcb818078, 0xc0001408, 0xcfc000f8, 0xc10e0002, 0xd90c00f8, 0x5d3802a6,
|
||||
0xc1000002, 0xd91c1f02, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0xa9fe0270, 0xc3c00000,
|
||||
0xddfc00f0, 0x5d3c0000, 0x84000100, 0xc0000c04, 0xcb8000f8, 0xc11c0002, 0x00000000, 0x7391c000,
|
||||
0xcf8000f8, 0xc3800000, 0xc3400080, 0xdf780038, 0xb7b4ffea, 0xc3203002, 0x5b3188c4, 0xc2e00f88,
|
||||
0x5aec100e, 0x99005fa8, 0xdb1800f8, 0xdad800f9, 0x00000000, 0xc3800000, 0xc3400080, 0xdf780038,
|
||||
0xb7b4ffea, 0xc3205002, 0x5b3188c8, 0xc2e00f90, 0x5aec180c, 0x99005fa8, 0xdb1800f8, 0xdad800f9,
|
||||
0x00000000, 0x80000128, 0xc00048cc, 0xca8000f8, 0x00000000, 0xc1000006, 0x76914000, 0x840000fa,
|
||||
0x00000000, 0xa6800070, 0xc3800000, 0xc3400080, 0xdf780038, 0xb7b4ffea, 0xc3202002, 0x5b31c8c6,
|
||||
0xc2e00f88, 0x5aec100e, 0x99005fa8, 0xdb1800f8, 0xdad800f9, 0x00000000, 0xa6820068, 0xc3800000,
|
||||
0xc3400080, 0xdf780038, 0xb7b4ffea, 0xc3204002, 0x5b31c8ca, 0xc2e00f90, 0x5aec180c, 0x99005fa8,
|
||||
0xdb1800f8, 0xdad800f9, 0x00000000, 0xc00048cc, 0xc2800000, 0xce8000f8, 0xc3a00140, 0x5bfc0002,
|
||||
0x47bc8000, 0xc1000000, 0xc53c00fe, 0xdbdc00f0, 0x80000530, 0x00000000, 0x80002130, 0x00000000,
|
||||
0x8000fd70, 0xc0004958, 0xc84000f8, 0x00000000, 0xc3c00002, 0x787c2000, 0xcc4000f8, 0xc0004848,
|
||||
0xcb8400f8, 0xc000495c, 0xcac400f8, 0xc0004844, 0xc88400f8, 0x47ad0000, 0x8400ff82, 0xc000487c,
|
||||
0xc80400f8, 0x00000000, 0x00000000, 0x40080000, 0xca0000f8, 0xc0001624, 0xcb0400f8, 0xa63c007a,
|
||||
0x00000000, 0x00000000, 0xa71eff22, 0x00000000, 0xc0000824, 0xca8400f8, 0x6ca08000, 0x6ca42000,
|
||||
0x46250000, 0x42290000, 0xc35e0002, 0xc6340060, 0xc0001624, 0xcf440078, 0xc2000000, 0xc161fffe,
|
||||
0x5955fffe, 0x14140000, 0x00000000, 0xc0004844, 0xc88400f8, 0xc000082c, 0xca040038, 0x00000000,
|
||||
0x00000000, 0x58880002, 0xb6080018, 0x00000000, 0xc0800000, 0xc0004844, 0xcc840038, 0x5aec0002,
|
||||
0xc000495c, 0xcec400f8, 0x5e6c0006, 0x84000060, 0xc0004848, 0xcb8400f8, 0xc0000838, 0xc2500002,
|
||||
0xce450800, 0x5fb80002, 0xc0004848, 0xcf8400f8, 0x5eec0002, 0xc000495c, 0xcec400f8, 0x00000000,
|
||||
0xc121fffe, 0x5911fe14, 0x14100000, 0x8000fd98, 0xc000495a, 0xc84000f8, 0x00000000, 0xc3c00002,
|
||||
0x787c2000, 0xcc4000f8, 0xc0004960, 0xcac400f8, 0x00000000, 0x00000000, 0x5eec0000, 0x8400010a,
|
||||
0x00000000, 0xb6fc0050, 0xc0001600, 0xca0400f8, 0x00000000, 0x00000000, 0xa61e00d2, 0x6fe90000,
|
||||
0xc0000a28, 0xce850800, 0xc2c00000, 0xc2800004, 0xb6e800a0, 0xc0001604, 0xca8400f8, 0xc0004960,
|
||||
0xcec400f8, 0xa69efcc2, 0x00000000, 0x6fe90000, 0xc0000a28, 0xce850800, 0xc2c00002, 0xc0001600,
|
||||
0xca0400f8, 0x00000000, 0x00000000, 0xa61e002a, 0x6fe90000, 0xc0000a28, 0xce850800, 0xc2c00000,
|
||||
0xc0001604, 0xca8400f8, 0xc0004960, 0xcec400f8, 0xa69efc2a, 0xc2400000, 0xc0000a14, 0xca440028,
|
||||
0x00000000, 0x00000000, 0x466d2000, 0xa4400020, 0xc2800000, 0xdfeb0029, 0x80000010, 0xdfea0029,
|
||||
0xb668f932, 0x00000000, 0xc00048a0, 0xcb0400f8, 0xc0000a10, 0xca8400f8, 0x6f208000, 0x6f242000,
|
||||
0x46250000, 0x42a10000, 0xc2400000, 0xc0000a14, 0xca440028, 0xc35e0002, 0xc6340060, 0xc0001604,
|
||||
0xcf440078, 0x5b300002, 0xb6700018, 0x5aec0002, 0xc3000000, 0xc00048a0, 0xcf0400f8, 0xc0004960,
|
||||
0xcec400f8, 0x8000f868, 0xc0004918, 0xd28000f8, 0xc2000000, 0xdf600038, 0x5e600080, 0x84000272,
|
||||
0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000480a, 0xca0000f8, 0xc0004912,
|
||||
0xca4000f8, 0xc0004924, 0xca8000f8, 0xc0004966, 0xcac000f8, 0x00000000, 0xc121fffe, 0x5911fe14,
|
||||
0x14100000, 0x76250000, 0x76290000, 0x762d0000, 0x840001ca, 0xc0004918, 0xca4000f8, 0xc28001fe,
|
||||
0x76290000, 0x5a640002, 0x6a254010, 0x5ee80000, 0x8400001a, 0x6aa54000, 0x80000010, 0xc62800f8,
|
||||
0x62818008, 0xc0004918, 0xcf0000f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0004966,
|
||||
0xca4000f8, 0xc2000002, 0x6a310000, 0x7e010000, 0x76612000, 0xce4000f8, 0x00000000, 0xc121fffe,
|
||||
0x5911fe14, 0x14100000, 0x6f346000, 0x4771a000, 0x5b744c80, 0xc2800000, 0x58340006, 0xca800078,
|
||||
0xc2c00000, 0x58340000, 0xcac000d8, 0xc2400000, 0x5834000a, 0xca420078, 0x6ea82000, 0x42e9e000,
|
||||
0x6f2ca000, 0x42e56000, 0x5aec1400, 0xc3990040, 0xc7381c18, 0xc6f80060, 0x99005fa8, 0xdb9800f8,
|
||||
0xdbd800f9, 0x00000000, 0xdea000f8, 0x46310000, 0x8400fd80, 0xc0004958, 0xc84000f8, 0x00000000,
|
||||
0xc3c00002, 0x787c2000, 0xcc4000f8, 0xc0004848, 0xcb8400f8, 0xc0004844, 0xc88400f8, 0x5fb80000,
|
||||
0x8400f7f2, 0xc0001a1c, 0xca0000f8, 0xc2400002, 0x6a452000, 0x76250000, 0x8400f7c2, 0xc000487c,
|
||||
0xc80400f8, 0x00000000, 0x00000000, 0x40080000, 0xca0000f8, 0xc42400f8, 0x00000000, 0xa63c17da,
|
||||
0x00000000, 0xc0004878, 0xc80400f8, 0x6c908000, 0x45088000, 0x45088000, 0x40100000, 0xca0000f8,
|
||||
0xc42400f8, 0x00000000, 0xc0004934, 0xce0000f8, 0xc2800002, 0xc4681c08, 0xc62821d0, 0xc2600010,
|
||||
0x5a652440, 0xc0004800, 0xcb4000f8, 0xc2200400, 0x5a202400, 0xc7601040, 0xc0001220, 0xce8000f8,
|
||||
0xc0001200, 0xce4000f8, 0xc0001202, 0xce0000f8, 0xc0001240, 0xcb4000f8, 0x00000000, 0x00000000,
|
||||
0xa754ffe0, 0xc2000000, 0xc7600040, 0xa7520042, 0x00000000, 0x00000000, 0x99006720, 0xc0004822,
|
||||
0xc94000f8, 0xc1800002, 0x80001680, 0x58206480, 0xc2000000, 0xca000018, 0xc2400000, 0xca414000,
|
||||
0xc2800000, 0xca812000, 0xc2c00000, 0xcac20018, 0xc0004938, 0xce0000f8, 0xc0004920, 0xce4000f8,
|
||||
0xc0004916, 0xce8000f8, 0xc0004922, 0xcec000f8, 0xa6400540, 0x00000000, 0xc0004938, 0xcbc000f8,
|
||||
0x00000000, 0xc3800000, 0x6ff48000, 0x6fd44000, 0x4355a000, 0x5b744a00, 0x58340000, 0xcb802010,
|
||||
0x00000000, 0xc2000000, 0x6fb46000, 0x4779a000, 0x5b744c80, 0x5834000c, 0xca000020, 0xc000491a,
|
||||
0xcf8000f8, 0x5e200000, 0x8400046a, 0xc2000000, 0xdf610048, 0x5e6001e8, 0x8800ffe8, 0xc2000002,
|
||||
0xc2400466, 0xc2a00000, 0x5aa80000, 0xc0001006, 0xce0000f8, 0xc0001008, 0xce4000f8, 0xc000100a,
|
||||
0xce8000f8, 0x990059e8, 0xc1a0fffe, 0xc0000824, 0xc9840060, 0xc0004934, 0xca4000f8, 0xc2000000,
|
||||
0xc2800002, 0x99005a28, 0xda9800f8, 0xc61400f8, 0xc65800f8, 0xc161fffe, 0x5955fffe, 0x14140000,
|
||||
0x00000000, 0x99005b10, 0xc000491a, 0xc94000f8, 0x00000000, 0x00000000, 0xc121fffe, 0x5911fe14,
|
||||
0x14100000, 0xc0004922, 0xca001118, 0xc3c00000, 0xc3800000, 0xc0004930, 0xce023118, 0xc0004932,
|
||||
0xcbc000d8, 0xc2800000, 0xc000491e, 0xcfc000f8, 0xc0004862, 0xca800060, 0xc3a0001a, 0x5bb94000,
|
||||
0xc6b80060, 0xc000491c, 0xcf8000f8, 0x99005d80, 0xc000491c, 0xc1400000, 0xc9420048, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xa8e2ffe8, 0xc2000000, 0xc1220002, 0xd90c00f8, 0xdf600038, 0x5e600080,
|
||||
0x8400fff2, 0xc000491c, 0xca0000f8, 0xc000491e, 0xca4000f8, 0x00000000, 0x00000000, 0x99005fa8,
|
||||
0xda1800f8, 0xda5800f9, 0x00000000, 0xc2000000, 0xdf610048, 0x5e6001fe, 0x8800ffe8, 0xc0004916,
|
||||
0xca8000f8, 0xc2c00000, 0xdfec0048, 0xc2400000, 0x466d2000, 0x8400004a, 0x5ea80000, 0x8400003a,
|
||||
0xc2600002, 0x99006720, 0xc000482e, 0xc94000f8, 0xc1800002, 0x80000030, 0xc2600000, 0x99006720,
|
||||
0xc000482c, 0xc94000f8, 0xc1800002, 0xc2000068, 0xc6240078, 0xc0004930, 0xce400080, 0xc000491a,
|
||||
0xc98000f8, 0xc0004862, 0xc94000f8, 0x6d9c6000, 0x45d8e000, 0x59dc4c80, 0x99005e08, 0xd95800f8,
|
||||
0xd99800f9, 0xd9d400f8, 0x99005d80, 0xc000491c, 0xc1400000, 0xc9420048, 0xc2000000, 0xdf600038,
|
||||
0x5e600080, 0x8400ffea, 0x00000000, 0xc000491c, 0xca0000f8, 0xc000491e, 0xca4000f8, 0x00000000,
|
||||
0x00000000, 0x99005fa8, 0xda1800f8, 0xda5800f9, 0x00000000, 0x800010e8, 0x00000000, 0x99006720,
|
||||
0xc000482a, 0xc94000f8, 0xc1800002, 0x800010b8, 0xc0004938, 0xcbc000f8, 0x00000000, 0x00000000,
|
||||
0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb84a00, 0x58380008, 0xca0000f8, 0x00000000, 0x00000000,
|
||||
0xa6000382, 0x00000000, 0xc0004938, 0xcbc000f8, 0xc3000000, 0x00000000, 0x6ff88000, 0x6fd44000,
|
||||
0x4395c000, 0x5bb84a00, 0x58380000, 0xcb002010, 0xc2000000, 0x58380008, 0xca020078, 0x5838000c,
|
||||
0xcac000f8, 0x5838000e, 0xca4000f8, 0xc000491a, 0xcf0000f8, 0xc0004930, 0xcec000f8, 0xc000493c,
|
||||
0xce0000f8, 0xc0004932, 0xce4000f8, 0x5e200000, 0x84000120, 0xc2800000, 0xa6fe00ba, 0x6f206000,
|
||||
0x46310000, 0x5a204c80, 0x5820000c, 0xca800020, 0x00000000, 0x00000000, 0x5ea80000, 0x840001f2,
|
||||
0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x99005b10, 0xc000491a, 0xc94000f8,
|
||||
0x00000000, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0xc0004930, 0xcac000f8, 0xc0004932,
|
||||
0xca4000f8, 0xc7ec1118, 0xc0004930, 0xcec000f8, 0x5838000c, 0xcec000f8, 0x58000002, 0xce4000f8,
|
||||
0xc0004934, 0xca0000f8, 0xc2400002, 0x6e642000, 0x6e642000, 0x76612000, 0x8400002a, 0xc2400002,
|
||||
0x6e684000, 0x58380008, 0xce804200, 0xa6000020, 0x6e682000, 0x58380008, 0xce802100, 0xc2400002,
|
||||
0x6e642000, 0x76612000, 0x840000ea, 0x58380008, 0xca0000f8, 0xc2800000, 0xc2400000, 0xa60200c0,
|
||||
0xdba800f8, 0x6f386000, 0x47b1c000, 0x5bb84c80, 0x58380004, 0xca400078, 0x58380002, 0xca800078,
|
||||
0x00000000, 0xdeb800f8, 0x46a54000, 0x88000060, 0x00000000, 0xc0004824, 0xca0000f8, 0xc2400002,
|
||||
0x6e640000, 0x5a200002, 0xce0000f8, 0x58380008, 0xce400000, 0x80000018, 0x00000000, 0x80000048,
|
||||
0xc0004934, 0xca0000f8, 0x00000000, 0x00000000, 0xa6020c6a, 0x00000000, 0x00000000, 0x80000c98,
|
||||
0xc2800000, 0xc2000200, 0xc240001a, 0xdf690048, 0x46294000, 0x46a54000, 0x8800ffd2, 0xc2000006,
|
||||
0xc2600982, 0x5a643b6e, 0x5838000a, 0xca8000f8, 0xc0001006, 0xce0000f8, 0xc0001008, 0xce4000f8,
|
||||
0xc000100a, 0xce8000f8, 0x990059e8, 0xc1a0fffe, 0xc0000824, 0xc9840060, 0xc2000000, 0xc0004930,
|
||||
0xca02e008, 0x58380026, 0xca4000f8, 0x00000000, 0xc2800000, 0x99005a28, 0xda9800f8, 0xc61400f8,
|
||||
0xc65800f8, 0xc0004934, 0xca0000f8, 0x00000000, 0x00000000, 0xa6020022, 0x00000000, 0x00000000,
|
||||
0x80000318, 0xc0004938, 0xcbc000f8, 0xc0004878, 0xc80400f8, 0x6c908000, 0x45088000, 0x45088000,
|
||||
0x40100000, 0xca0000f8, 0xc42400f8, 0x00000000, 0x58240018, 0xca0000f8, 0x6ff88000, 0x6fd44000,
|
||||
0x4395c000, 0x5bb84a00, 0xc3000000, 0xc3400002, 0xc2c00000, 0xc62c0078, 0xc6270038, 0xc0004940,
|
||||
0xce400038, 0xc6260038, 0xc0004942, 0xce400038, 0xc000493c, 0xca0000f8, 0x5eec0000, 0x8400018a,
|
||||
0x5a6c0010, 0x46254000, 0x88000190, 0x5a600052, 0x46e54000, 0x88000178, 0x58380006, 0xca8000f8,
|
||||
0xc0004940, 0xca0000f8, 0xc2400000, 0xc6a70038, 0x7e412000, 0x76612000, 0xc2000000, 0xc6a10038,
|
||||
0x46250000, 0x84000138, 0xc0004942, 0xca0000f8, 0xc2400000, 0xc6a60038, 0x7e412000, 0x76612000,
|
||||
0xc2000000, 0xc6a00038, 0x58380002, 0xca8000f8, 0x46250000, 0x840000e8, 0xc2400000, 0xc6a60078,
|
||||
0x466d0000, 0x880000da, 0xc2400000, 0xc6a40078, 0x58380008, 0xca8000f8, 0x46e50000, 0x880000ba,
|
||||
0x00000000, 0xa6820018, 0x00000000, 0xc7700b00, 0xa6840098, 0x00000000, 0xc7700a00, 0x80000080,
|
||||
0xc7700200, 0xc000493c, 0xcac000f8, 0x80000060, 0xc7700300, 0xc000493c, 0xcac000f8, 0x80000040,
|
||||
0xc7700900, 0x80000030, 0xc7700800, 0x80000020, 0xc7700700, 0x80000010, 0xc7700500, 0xc0004944,
|
||||
0xcf0000f8, 0xc000493e, 0xcec000f8, 0xc0004938, 0xca4000f8, 0xc000493c, 0xcb8000f8, 0xc000493e,
|
||||
0xcb4000f8, 0xc3000000, 0x6e608000, 0x6e544000, 0x42150000, 0x5a204a00, 0x5aa00008, 0x58200004,
|
||||
0xcb000078, 0xc0004934, 0xca0000f8, 0xc2400000, 0xc0004930, 0xca42e008, 0xc3c00018, 0xa6020098,
|
||||
0x00000000, 0x43656000, 0x47ad0000, 0x88000050, 0x46f96000, 0x6ee04010, 0x5be00004, 0xc2000000,
|
||||
0xc6e00008, 0x5e200000, 0x84000042, 0x5bfc0002, 0x80000030, 0xc3c00004, 0x5a2c0008, 0x47a10000,
|
||||
0x88000012, 0x5fb80008, 0x6fe04000, 0x42390000, 0x47212000, 0x88000068, 0xc2400000, 0xc0004930,
|
||||
0xca42e008, 0xc2060002, 0xc68000f8, 0xce006300, 0x6fe04000, 0x4721c000, 0x5f700010, 0x4765a000,
|
||||
0xc2000000, 0xc6340008, 0xc25a000a, 0xc000491a, 0xca401c18, 0xc2800000, 0xc0004932, 0xca8000d8,
|
||||
0xc0004862, 0xca400060, 0x6fa04010, 0x42290000, 0xc000491e, 0xce0000f8, 0xc7e41048, 0xc000491c,
|
||||
0xce4000f8, 0x6fe04000, 0x43a1c000, 0xc000493c, 0xcf8000f8, 0xc000493e, 0xcf4000f8, 0xc000493a,
|
||||
0xcfc000f8, 0x80000008, 0x00000000, 0x00000000, 0x00000000, 0xc2000000, 0xdce000f8, 0xa622ffd8,
|
||||
0xc1220002, 0xd90c00f8, 0xc0004938, 0xcbc000f8, 0xc0004944, 0xcb4000f8, 0xc0004862, 0xcb0000f8,
|
||||
0xc0004934, 0xca0000f8, 0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb84a00, 0xa6020268, 0xc2400000,
|
||||
0x58380008, 0xca406000, 0xdfe800f8, 0xc2218e08, 0x5a21baf6, 0x46a14000, 0x84000022, 0xc2080002,
|
||||
0x7361a000, 0x80000058, 0x5e640000, 0x84000022, 0xc20c0002, 0x7361a000, 0x80000030, 0xc2000000,
|
||||
0xc760e710, 0xc7604218, 0x5e200000, 0x84000272, 0xc2200002, 0xc0004930, 0xce021000, 0x99006720,
|
||||
0xc0004828, 0xc94000f8, 0xc1800002, 0x58380000, 0xca0000f8, 0x00000000, 0x00000000, 0xa6000132,
|
||||
0xc0004940, 0xca8000f8, 0xc0004942, 0xca4000f8, 0xc7600078, 0xc6a01838, 0xc6601038, 0xc000493a,
|
||||
0xca4000f8, 0xc0004934, 0xca8000f8, 0xc0005600, 0x40300000, 0x40240000, 0x5c000004, 0x5ec05800,
|
||||
0x88000012, 0x5c000200, 0xce0000f8, 0x58000002, 0x5ec05800, 0x88000012, 0x5c000200, 0xce8000f8,
|
||||
0xc000493e, 0xca0000f8, 0xc2400000, 0x5838000c, 0xce4000f8, 0x99006720, 0xc0004830, 0xc94000f8,
|
||||
0xc61800f8, 0xc0004930, 0xc6100078, 0xcd000078, 0x800000a8, 0xc2400002, 0x58380008, 0xce400000,
|
||||
0xc0004944, 0xcf4000f8, 0x80000278, 0xc000493c, 0xca4000f8, 0xdfe800f8, 0x5a300018, 0xc0005600,
|
||||
0x40200000, 0xca0000f8, 0x58380008, 0xc6501078, 0xcd021078, 0x5838000a, 0xce8000f8, 0x58380026,
|
||||
0xce0000f8, 0xc0004944, 0xcf4000f8, 0x99005d80, 0xc000491c, 0xc1400000, 0xc9420048, 0x80000038,
|
||||
0x00000000, 0x99006720, 0xc0004826, 0xc94000f8, 0xc1800002, 0x8000fdd8, 0xc2000000, 0xc2400080,
|
||||
0xdf600038, 0xb624ffea, 0xc000491c, 0xca4000f8, 0xc000491e, 0xca8000f8, 0x99005fa8, 0xda5800f8,
|
||||
0xda9800f9, 0x00000000, 0xc0004934, 0xca0000f8, 0x00000000, 0xc2800000, 0xa6020160, 0xc2400004,
|
||||
0xc2000200, 0xdf690048, 0x46294000, 0x46a54000, 0x8800ffda, 0x00000000, 0xc000491a, 0xc98000f8,
|
||||
0xc0004862, 0xc94000f8, 0x6d9c6000, 0x45d8e000, 0x59dc4c80, 0x99005e08, 0xd95800f8, 0xd99800f9,
|
||||
0xd9d400f8, 0x99005d80, 0xc000491c, 0xc1400000, 0xc9420048, 0xc2000000, 0xc2400080, 0xdf600038,
|
||||
0xb624ffea, 0xc000491c, 0xca4000f8, 0xc000491e, 0xca8000f8, 0x99005fa8, 0xda5800f8, 0xda9800f9,
|
||||
0x00000000, 0x58380008, 0xca4000f8, 0xc2000000, 0xce000018, 0xc2a1fffe, 0x5aa9fffe, 0xce021078,
|
||||
0x5838000a, 0xce8000f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0000838, 0xc2500002,
|
||||
0xce450800, 0xc0004848, 0xcb8400f8, 0xc2000000, 0xc000082c, 0xca040028, 0x5fb80002, 0xc0004848,
|
||||
0xcf8400f8, 0x58880002, 0xb6080018, 0x00000000, 0xc0800000, 0xc0004844, 0xcc8400f8, 0x00000000,
|
||||
0xc121fffe, 0x5911fe14, 0x14100000, 0x8000ded8, 0xc2000000, 0xdf600038, 0x5e200080, 0x8400026a,
|
||||
0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000480c, 0xca0000f8, 0xc0004910,
|
||||
0xca4000f8, 0xc000492c, 0xca8000f8, 0xc0004968, 0xcac000f8, 0x00000000, 0xc121fffe, 0x5911fe14,
|
||||
0x14100000, 0x76250000, 0x76290000, 0x76e16000, 0x840001c2, 0xc0004926, 0xca4000f8, 0xc201fffe,
|
||||
0x76e16000, 0x5a640002, 0x6ae50010, 0x5f200000, 0x8400001a, 0x6a250000, 0x80000010, 0xc6e000f8,
|
||||
0x62014008, 0xc0004926, 0xce8000f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0004968,
|
||||
0xca4000f8, 0xc2000002, 0x6a290000, 0x7e010000, 0x76612000, 0xce4000f8, 0x00000000, 0xc121fffe,
|
||||
0x5911fe14, 0x14100000, 0x6eb4a000, 0x6e944000, 0x4755a000, 0x4769a000, 0x5b745e00, 0x58340002,
|
||||
0xc2000000, 0xca0000d8, 0x5834002e, 0xc2400000, 0xca400078, 0x6eb0a000, 0x6ebc4000, 0x473d8000,
|
||||
0x47298000, 0x5b301e2e, 0x5b300004, 0x6e642000, 0x4225e000, 0xc39a8024, 0xc7380060, 0xc6b81c18,
|
||||
0x99005fa8, 0xdb9800f8, 0xdbd800f9, 0x00000000, 0xc2000000, 0xdf600038, 0x5e200080, 0x84000352,
|
||||
0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000490e, 0xca0000f8, 0xc00049a0,
|
||||
0xca8000f8, 0xc000492a, 0xca4000f8, 0xc000496a, 0xcb0000f8, 0xc0004956, 0xcac000f8, 0x00000000,
|
||||
0xc121fffe, 0x5911fe14, 0x14100000, 0x77218000, 0x77258000, 0x77298000, 0x8400029a, 0xc201fffe,
|
||||
0x77218000, 0x5aec0002, 0x6b2d0010, 0x5ea00000, 0x8400001a, 0x6a2d0000, 0x80000010, 0xc72000f8,
|
||||
0x62016008, 0xc0004956, 0xcec000f8, 0x6ef4a000, 0x6ed44000, 0x4755a000, 0x476da000, 0x5b745e00,
|
||||
0x58340000, 0xc9c000f8, 0xc00049a0, 0xca0000f8, 0xc3000000, 0xc5f04018, 0xc2400000, 0xc5e50038,
|
||||
0x7e412000, 0x76250000, 0xce0000f8, 0xc0004980, 0x40300000, 0xcec000f8, 0xc161fffe, 0x5955fffe,
|
||||
0x14140000, 0x00000000, 0xc000496a, 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x7e010000, 0x76612000,
|
||||
0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x6ef4a000, 0x6ed44000, 0x4755a000,
|
||||
0x476da000, 0x5b745e00, 0x5834000e, 0xc2000000, 0xca0000d8, 0x58340008, 0xc2400000, 0xca420078,
|
||||
0x5834000c, 0xc2800000, 0xca832010, 0x6e644010, 0x42250000, 0x4229e000, 0xc39a8008, 0x58340008,
|
||||
0xcb809018, 0x58340008, 0xc2800000, 0xca810010, 0x6ee0a000, 0x6ee44000, 0x46250000, 0x462d0000,
|
||||
0x5a200008, 0x5a201e08, 0x42290000, 0xc6380060, 0xc6f81c18, 0x99005fa8, 0xdb9800f8, 0xdbd800f9,
|
||||
0x00000000, 0xc000495a, 0xc84000f8, 0x00000000, 0xc3c00002, 0x787c2000, 0xcc4000f8, 0xc0001a1c,
|
||||
0xca0000f8, 0xc2400008, 0x6a452000, 0x76250000, 0x84000ec2, 0xc0000a28, 0xc3800000, 0xcb840028,
|
||||
0xc0000a14, 0xc3400000, 0xcb440028, 0xc0004880, 0xcb0400f8, 0xb7b40072, 0x58041802, 0xcac000f8,
|
||||
0xa7000078, 0x00000000, 0x00000000, 0xa6c8d598, 0xc1000000, 0xc6d00018, 0xc0004980, 0x40100000,
|
||||
0xca8000f8, 0x80000070, 0x00000000, 0x00000000, 0x00000000, 0x8000d548, 0x00000000, 0xc2800000,
|
||||
0xc7282018, 0xc000490e, 0xca4000f8, 0x6be9e000, 0x00000000, 0x767d2000, 0x8400d500, 0x6ea0a000,
|
||||
0x6e944000, 0x46150000, 0x46290000, 0x5a205e00, 0x5820000c, 0xca0000f8, 0xc0004946, 0xce8000f8,
|
||||
0xa62203a8, 0x00000000, 0xc2200060, 0xc0004948, 0xce000008, 0xce021038, 0xc240000a, 0xc000494a,
|
||||
0xce4000f8, 0xc2b60002, 0xc0004964, 0xce837b00, 0x99006278, 0xc00048a0, 0xc88400f8, 0x00000000,
|
||||
0xc0004946, 0xcbc000f8, 0x00000000, 0x00000000, 0x6ff8a000, 0x6fd44000, 0x4795c000, 0x47bdc000,
|
||||
0x5bb85e00, 0x99006038, 0xdbd800f8, 0xdb9800f9, 0x00000000, 0x99005d80, 0xc000491c, 0xc1400000,
|
||||
0xc9420048, 0xc000491c, 0x99006230, 0xc94000f9, 0xc98000f8, 0x00000000, 0x99005fa8, 0xd95800f8,
|
||||
0xd99800f9, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x99005c70, 0xdbd800f8,
|
||||
0xdb9800f9, 0xc7d800f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x6ff8a000, 0x6fd44000,
|
||||
0x4795c000, 0x47bdc000, 0x5bb85e00, 0x58380010, 0xca0000f8, 0xc0004874, 0xc80400f8, 0x6c908000,
|
||||
0x45088000, 0x45088000, 0x40100000, 0xca4000f8, 0xc43400f8, 0x00000000, 0xc74000f8, 0xce0000f8,
|
||||
0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000490e, 0xca4000f8, 0xc2800002, 0x6abd4000,
|
||||
0x72692000, 0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x99006720, 0xc0004836,
|
||||
0xc94000f8, 0xc1800002, 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000, 0x58380000,
|
||||
0xc90000f8, 0xc00049a0, 0xca0000f8, 0xc2800000, 0xc5290038, 0x72290000, 0xce0000f8, 0xc1220002,
|
||||
0xd90c00f8, 0xc2000000, 0xc0000a14, 0xca040028, 0xc0000a28, 0xc2500002, 0xce450800, 0x58880002,
|
||||
0xb6080018, 0xc00048a0, 0xc0800000, 0xcc8400f8, 0x8000d110, 0xc0004946, 0xcbc000f8, 0xc161fffe,
|
||||
0x5955fffe, 0x14140000, 0x00000000, 0xc000490e, 0xca4000f8, 0xc2800002, 0x6abd4000, 0x72692000,
|
||||
0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x6ff8a000, 0x6fd44000, 0x4795c000,
|
||||
0x47bdc000, 0x5bb85e00, 0x58380008, 0xca0000f8, 0x5838000c, 0xca4000f8, 0xc3400000, 0xc6340000,
|
||||
0xc000494e, 0xcf4000f8, 0xc2800000, 0xc62a0078, 0xc3000000, 0xc6308018, 0x6f304000, 0x43298000,
|
||||
0xc000493c, 0xcf0000f8, 0xc2c00000, 0xc66c0078, 0xc0004950, 0xcec000f8, 0xc2800000, 0xc66ae020,
|
||||
0xc0004954, 0xce8000f8, 0x5f740000, 0x840001a0, 0x5e300028, 0x46e12000, 0x8400016a, 0x46e12000,
|
||||
0x88000132, 0x5e300018, 0x46e12000, 0x8800002a, 0x46e12000, 0x84000042, 0x00000000, 0x800000c0,
|
||||
0x00000000, 0x990063b8, 0xdbd800f8, 0xdb9800f9, 0xc78000f8, 0xc3400002, 0xc000494e, 0xcf4000f8,
|
||||
0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000490e, 0xca4000f8, 0xc2800002, 0x6abd4000,
|
||||
0x7e814000, 0x76692000, 0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0xc2200060,
|
||||
0xc0004948, 0xce021038, 0xc2000000, 0xc000494c, 0xce0000f8, 0x80000080, 0x00000000, 0x990063b8,
|
||||
0xdbd800f8, 0xdb9800f9, 0xc78000f8, 0x990065b8, 0xdbd800f8, 0xdb9800f9, 0xc78000f8, 0xc2200058,
|
||||
0xc0004948, 0xce021038, 0xc2000002, 0xc000494c, 0xce0000f8, 0xc2000006, 0xc0001006, 0xce0000f8,
|
||||
0x5838000a, 0xca4000f8, 0xc2200982, 0x5a203b6e, 0xc0001008, 0xce0000f8, 0xc000100a, 0xce4000f8,
|
||||
0xc0004954, 0xca8000f8, 0xc200000c, 0xc000494a, 0xce0000f8, 0xc0004948, 0xce800008, 0xc2b60000,
|
||||
0xc0004964, 0xce8000f8, 0x99006278, 0xc00048a0, 0xc88400f8, 0x00000000, 0xc0004946, 0xcbc000f8,
|
||||
0xc000494c, 0xca0000f8, 0x6ff8a000, 0x6fd44000, 0x4795c000, 0x47bdc000, 0x5bb85e00, 0x5e200000,
|
||||
0x840000fa, 0x00000000, 0x99006038, 0xdbd800f8, 0xdb9800f9, 0x00000000, 0x99005d80, 0xc000491c,
|
||||
0xc1400000, 0xc9420048, 0xc000491c, 0x99006230, 0xc94000f9, 0xc98000f8, 0x00000000, 0x99005fa8,
|
||||
0xd95800f8, 0xd99800f9, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x99005c70,
|
||||
0xdbd800f8, 0xdb9800f9, 0xc7d800f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0xc000493c,
|
||||
0xca8000f8, 0xc000494e, 0xcac000f8, 0xc3000018, 0xc3400006, 0x5e200000, 0x8400002a, 0xc2800000,
|
||||
0xc2c00000, 0xc300001e, 0xc3400000, 0xc6ac1078, 0xc72c0418, 0xc76c0810, 0x58380010, 0xca8000f8,
|
||||
0x58380008, 0xcec000f8, 0xc6280100, 0xc0004874, 0xc80400f8, 0x6c908000, 0x45088000, 0x45088000,
|
||||
0x40100000, 0xcb0000f8, 0xc43400f8, 0x00000000, 0xc74000f8, 0xce8000f8, 0xc0004952, 0xce8000f8,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000, 0xc000494c, 0xca0000f8, 0xc0004950,
|
||||
0xcac000f8, 0x5e200000, 0x8400006a, 0xdfe800f8, 0x7e814000, 0x5834001a, 0xce8000f8, 0x99006720,
|
||||
0xc0004834, 0xc94000f8, 0xc1800002, 0x99006720, 0xc0004838, 0xc94000f8, 0xc6d800f8, 0xc1220002,
|
||||
0xd90c00f8, 0x5e200000, 0x84000040, 0x5838002c, 0xcb0000f8, 0xdfe800f8, 0x00000000, 0x58380014,
|
||||
0xcf0000f8, 0x80000058, 0xc2a1fffe, 0x5aa9fffe, 0x58380000, 0xc90000f8, 0xc00049a0, 0xcb0000f8,
|
||||
0xc2c00000, 0xc52d0038, 0x732d8000, 0xcf0000f8, 0x5838000a, 0xce8000f8, 0xc3000000, 0xc0000a14,
|
||||
0xcb040028, 0xc2d00002, 0xc0000a28, 0xcec50800, 0xc000494e, 0xca8000f8, 0x58880002, 0xb4b00018,
|
||||
0xc00048a0, 0xc0800000, 0xcc8400f8, 0x5ea80000, 0x8400017a, 0x5e200000, 0x84000168, 0xc000493c,
|
||||
0xca8000f8, 0x00000000, 0x00000000, 0x5aa80060, 0xce8000f8, 0x990063b8, 0xdbd800f8, 0xdb9800f9,
|
||||
0xc78000f8, 0x990065b8, 0xdbd800f8, 0xdb9800f9, 0xc78000f8, 0x58380000, 0xcac000f8, 0x00000000,
|
||||
0xc2000000, 0xc6e04018, 0xc0004952, 0xcac000f8, 0x58380000, 0xca8000f8, 0xc30c0002, 0xc6300018,
|
||||
0xa6800098, 0x00000000, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0001800,
|
||||
0xca0000f8, 0x00000000, 0x00000000, 0xa60cffea, 0xc6f00500, 0xc6b0c400, 0xcf0000f8, 0x00000000,
|
||||
0xc121fffe, 0x5911fe14, 0x14100000, 0x8000c758, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x8000c6f0, 0xdcbc00f9, 0x5ffc0000, 0x84000052, 0xc3800002, 0xdb8800f9, 0x5ffc0004, 0x8400bf4a,
|
||||
0xc3800000, 0xdb8800f9, 0xc3ce0002, 0xc0000800, 0xcfc0e700, 0xc3e1fffe, 0x597dfffe, 0x593dfe14,
|
||||
0x94000001, 0x00000000, 0x00000000, 0x00000000, 0xc000487c, 0xc80400f8, 0x00000000, 0x00000000,
|
||||
0x40080000, 0xcbc000f8, 0xc43800f8, 0x00000000, 0xc000480e, 0xca0000f8, 0xc0004858, 0xcb4400f8,
|
||||
0x00000000, 0x00000000, 0x47610000, 0x880000b0, 0x00000000, 0xa7c00048, 0xc0004854, 0xc1000002,
|
||||
0xcd0400f8, 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x800000d8, 0x00000000, 0xa7d20138, 0x00000000,
|
||||
0xc7e14040, 0xc2400000, 0xc6246028, 0xc200006a, 0x46250000, 0xc6240030, 0xc0000810, 0xce440030,
|
||||
0x8000ff70, 0xc2000000, 0xc0000808, 0xca040010, 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x5a200002,
|
||||
0x5e600010, 0x84000010, 0xc2000000, 0xc0000808, 0xce040010, 0xc3400000, 0x80000028, 0xc1200002,
|
||||
0xc0000818, 0xcd061000, 0x5b740002, 0xc0004858, 0xcf4400f8, 0x990059c0, 0xc0004848, 0xc94400f8,
|
||||
0xc1800000, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0x80000600, 0x5b740002, 0xc0004858, 0xcf4400f8,
|
||||
0xc78000f8, 0xc13c0002, 0xcd03de00, 0xc0004848, 0xc94400f8, 0xc1800000, 0xc000082c, 0xc9840028,
|
||||
0x59540002, 0xc0004848, 0xcd4400f8, 0x58880002, 0xb4980580, 0x00000000, 0xc0800000, 0x80000568,
|
||||
0xc000487c, 0xc80400f8, 0x00000000, 0x00000000, 0x40080000, 0xcbc000f8, 0xc42800f8, 0x00000000,
|
||||
0xa7c00130, 0xc000484c, 0xca0400f8, 0xc2400000, 0xc0001aec, 0xca440018, 0x5a200002, 0xc000484c,
|
||||
0xce0400f8, 0xb624008a, 0xc68000f8, 0xc13c0002, 0xcd03de00, 0xc0004848, 0xc94400f8, 0xc1800000,
|
||||
0xc000082c, 0xc9840028, 0x59540002, 0xc0004848, 0xcd4400f8, 0x58880002, 0xb4980470, 0x00000000,
|
||||
0xc0800000, 0x80000458, 0xc0004854, 0xc1000004, 0xcd0400f8, 0xc0000820, 0xc2000002, 0xce0400f8,
|
||||
0xc2000000, 0xc000484c, 0xce0400f8, 0xc0004858, 0xce0400f8, 0x8000ff28, 0xc0004854, 0xc1000000,
|
||||
0xcd0400f8, 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x990059c0, 0xc0004848, 0xc94400f8, 0xc1800000,
|
||||
0xc1200000, 0xc0000818, 0xcd061000, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc2000000, 0xc000484c,
|
||||
0xce0400f8, 0x80000358, 0xc0001ac0, 0xcb8400f8, 0xc000487c, 0xc80400f8, 0x00000000, 0x00000000,
|
||||
0x40080000, 0xcbc000f8, 0xc42800f8, 0x00000000, 0x00000000, 0xc68000f8, 0xc13c0000, 0xcd03de00,
|
||||
0xa780024a, 0x00000000, 0x00000000, 0xa7c0020a, 0x00000000, 0xc0001b00, 0xc2060006, 0xce046308,
|
||||
0xa7e801c2, 0x00000000, 0xc0004850, 0xca0400f8, 0xc2400000, 0xc0001aec, 0xca448018, 0x5a200002,
|
||||
0xc0004850, 0xce0400f8, 0xb62400aa, 0x00000000, 0xc68000f8, 0xc13c0002, 0xcd03de00, 0xc0001acc,
|
||||
0xc2000002, 0xce040000, 0xc0004848, 0xc94400f8, 0xc1800000, 0xc000082c, 0xc9840028, 0x59540002,
|
||||
0xc0004848, 0xcd4400f8, 0x58880002, 0xb49801c8, 0x00000000, 0xc0800000, 0x800001b0, 0xc0004854,
|
||||
0xc1000000, 0xcd0400f8, 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x990059c0, 0xc0004848, 0xc94400f8,
|
||||
0xc1800000, 0xc2000000, 0xc0000820, 0xce0400f8, 0xc1200000, 0xc0000818, 0xcd061000, 0xc11c0002,
|
||||
0xc000082c, 0xcd05ce00, 0xc0004850, 0xce0400f8, 0xc2000002, 0xc0001acc, 0xce040008, 0x800000e8,
|
||||
0xc2000002, 0xc0004850, 0xce0400f8, 0x8000fe88, 0xc2000000, 0xc0004850, 0xce0400f8, 0xa7e60032,
|
||||
0x00000000, 0xc2000002, 0xc0001b00, 0xce040000, 0x8000fe70, 0x00000000, 0xa7860052, 0x00000000,
|
||||
0xc68000f8, 0xc13c0002, 0xcd03de00, 0xc2020002, 0xc7e2a540, 0xc0001b00, 0xce0400f8, 0x8000fe18,
|
||||
0xc2040002, 0xc0001b00, 0xce044200, 0x8000fdf8, 0xc2c80002, 0x6ac56000, 0xdacc00f8, 0xc0004854,
|
||||
0xcb4400f8, 0xc0004848, 0xcb8400f8, 0xc0000838, 0xc3c00000, 0xcbc40028, 0x5ef40004, 0x84000022,
|
||||
0xc3000000, 0xc0001acc, 0xcf042100, 0x47f98000, 0x8400002a, 0x47f98000, 0x88000030, 0xc1006e8c,
|
||||
0x8000b380, 0xc0004840, 0xcc8400f8, 0x8000f6b0, 0xc0001ac0, 0xcac400f8, 0xc0004854, 0xcb4400f8,
|
||||
0xa6c0fbd2, 0x00000000, 0x5ef40000, 0x8400f70a, 0x5ef40002, 0x8400f99a, 0x5ef40004, 0x8400fb9a,
|
||||
0xc1006ce8, 0x8000b2f8, 0x00000000, 0xc0800000, 0xdf4b0038, 0xc0004900, 0xcb8000f8, 0xc2000000,
|
||||
0xc000490a, 0xa78000d0, 0xcbc000f8, 0xc1000000, 0xd90000f9, 0xc1000002, 0xd90c00f8, 0x6ff46000,
|
||||
0x477da000, 0x5b744c80, 0xc2400000, 0x58340004, 0xca400078, 0xc0004900, 0xce000000, 0x5a640002,
|
||||
0x58340004, 0xc6500078, 0xcd000078, 0xc0004914, 0xca4000f8, 0xc2000002, 0x6a3d0000, 0x72612000,
|
||||
0xce4000f8, 0xc0000408, 0xce0000f8, 0xa78200d8, 0xc0004908, 0xcbc000f8, 0xc1000000, 0xd90000f9,
|
||||
0xc1000002, 0xd90c00f8, 0x6ff4a000, 0x6fd44000, 0x4755a000, 0x477da000, 0x5b745e00, 0xc2800000,
|
||||
0x58340006, 0xca800078, 0xc2000000, 0xc0004900, 0xce002100, 0x5ea80002, 0x58340006, 0xc6900078,
|
||||
0xcd000078, 0x5a7c0020, 0xc2000002, 0x6a250000, 0xc0000408, 0xce0000f8, 0xdca800f9, 0x5ea80000,
|
||||
0x8400b168, 0x00000000, 0xa4800230, 0x00000000, 0xc3c00000, 0xc000140e, 0xcbc00018, 0xc3400000,
|
||||
0xc2400000, 0x6ff86000, 0x47bdc000, 0x5bb84c80, 0x58380008, 0xcb400078, 0x58380006, 0xca400078,
|
||||
0x5f740002, 0x58380008, 0xc7500078, 0xcd000078, 0xc2000000, 0x58380004, 0xca020078, 0xc3000000,
|
||||
0x5838000c, 0xcb000020, 0x5a640002, 0x46610000, 0x84000010, 0xc2400000, 0x58380006, 0xc6500078,
|
||||
0xcd000078, 0xc2000000, 0x5838000a, 0xca020078, 0x5b300002, 0x5838000c, 0xc7100020, 0xcd000020,
|
||||
0xc2420020, 0x5a200004, 0x46252000, 0x84000010, 0xc2000000, 0x5838000a, 0xc6101078, 0xcd021078,
|
||||
0xc0004966, 0xca4000f8, 0xc2000002, 0x6a3d0000, 0x72612000, 0xce4000f8, 0x5f740000, 0x84000040,
|
||||
0xc0004912, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0x5f300020,
|
||||
0x84000040, 0xc0004924, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8,
|
||||
0xa4820070, 0xc2400000, 0xc000140e, 0xca408018, 0xc2000002, 0xc0004900, 0xce000000, 0xc000490a,
|
||||
0xce4000f8, 0xc1000000, 0xd90000f9, 0xd8400078, 0xc1000004, 0xd90000f9, 0xa4840270, 0x00000000,
|
||||
0xc3c00000, 0xc000140e, 0xcbc10018, 0xc2800000, 0xc2000000, 0x6ff8a000, 0x6fd44000, 0x4795c000,
|
||||
0x47bdc000, 0x5bb85e00, 0x5838002e, 0xca800078, 0x58380006, 0xca020078, 0xc3400000, 0x5838002e,
|
||||
0xcb420078, 0x5aa80002, 0x46a10000, 0x84000010, 0xc2800000, 0x5838002e, 0xc6900078, 0xcd000078,
|
||||
0x5f740002, 0x5838002e, 0xc7501078, 0xcd021078, 0xc0004968, 0xca4000f8, 0xc2000002, 0x6a3d0000,
|
||||
0x72612000, 0xce4000f8, 0xc000492a, 0xca8000f8, 0x5e740000, 0x84000040, 0xc0004910, 0xca0000f8,
|
||||
0xc2c00002, 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0x6abd4010, 0xa68000ba, 0x00000000,
|
||||
0x58380032, 0xca0000f8, 0x58000002, 0xca4000f8, 0x5838000c, 0x00000000, 0xce0000f9, 0xce4000f8,
|
||||
0xc000492a, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x722d0000, 0xce0000f8, 0xc000492c, 0xca0000f8,
|
||||
0xc2c00002, 0x6afd6000, 0x722d0000, 0xce0000f8, 0x80000040, 0xc000492c, 0xca0000f8, 0xc2c00002,
|
||||
0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0xa4880148, 0xc2c00000, 0xc000140e, 0xcac20018,
|
||||
0xc000490e, 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x7e010000, 0x76612000, 0xce4000f8, 0xc000496a,
|
||||
0xca4000f8, 0xc2000002, 0x6a2d0000, 0x72612000, 0xce4000f8, 0x6ef0a000, 0x6ed44000, 0x47158000,
|
||||
0x472d8000, 0x5b305e00, 0x58300000, 0xca0000f8, 0x00000000, 0xc2400002, 0x76612000, 0x84000072,
|
||||
0x58300000, 0xca4000f8, 0xc2800000, 0x00000000, 0xc6684018, 0xc24c0002, 0xc6a40018, 0xc624c400,
|
||||
0x58300010, 0xca400500, 0x00000000, 0xc0001800, 0xce4000f8, 0xa4860070, 0xc2400000, 0xc000140e,
|
||||
0xca418018, 0xc2020002, 0xc0004900, 0xce002100, 0xc0004908, 0xce4000f8, 0xc1000000, 0xd90000f9,
|
||||
0xd8400078, 0xc1000004, 0xd90000f9, 0xa48c00e8, 0xc2400000, 0xc000140e, 0xca430018, 0x00000000,
|
||||
0x00000000, 0x5d240002, 0x84000058, 0xc00048c4, 0xca0000f8, 0xc00048c6, 0xc1040002, 0x72110000,
|
||||
0xce0000f8, 0xc1000002, 0xc00048cc, 0xcd000000, 0x80000060, 0x5d240004, 0x84000050, 0xc00048c8,
|
||||
0xca0000f8, 0xc00048ca, 0xc1160002, 0x72110000, 0xce0000f8, 0xc1020002, 0xc00048cc, 0xcd002100,
|
||||
0xc0001408, 0xcc8000f8, 0xc10e0002, 0xd90c00f8, 0x8000ecc8, 0xdfbc00f9, 0xc000496e, 0x990066c8,
|
||||
0xc94000f8, 0xc7d800f8, 0x00000000, 0xc57000f8, 0x5ef00020, 0x88000148, 0x6f346000, 0x4771a000,
|
||||
0x5b744c80, 0x58340008, 0xc2400000, 0xca400078, 0x00000000, 0xc2000000, 0x5a640002, 0xce400078,
|
||||
0x58340004, 0xca000078, 0x00000000, 0x00000000, 0x5e200002, 0xce000078, 0xc0004912, 0xca8000f8,
|
||||
0xc2400002, 0x6a712000, 0x72a54000, 0xce8000f8, 0x5e200000, 0x84000052, 0xc000480a, 0xca0000f8,
|
||||
0xc0000408, 0xca8000f8, 0x76250000, 0x00000000, 0x72a14000, 0xce8000f8, 0x80000038, 0xc0004914,
|
||||
0xca0000f8, 0x7e412000, 0x00000000, 0x76250000, 0xce0000f8, 0x800000d0, 0x6ef4a000, 0x6ed44000,
|
||||
0x4755a000, 0x476da000, 0x5b745e00, 0x5834002e, 0xc2400000, 0xca420078, 0x00000000, 0xc2000000,
|
||||
0x5a640002, 0xc6501078, 0xcd021078, 0x58340006, 0xca000078, 0x00000000, 0x00000000, 0x5a200002,
|
||||
0xce000078, 0xc0004910, 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x72612000, 0xce4000f8, 0xc2000002,
|
||||
0x6a310000, 0xc000042a, 0xce0000f8, 0xc1040002, 0xd90c00f8, 0x00000000, 0x8000ea38, 0x00000000,
|
||||
0xc4980928, 0x9d000000, 0xc5580028, 0xc0000838, 0xcd8400f8, 0xc1440200, 0xc1c01600, 0xc55c1070,
|
||||
0xc000100e, 0x9d000000, 0xcd8000f8, 0xc000100c, 0xcdc000f8, 0xc0004862, 0xc9c000f8, 0x00000000,
|
||||
0x00000000, 0xd9d800f9, 0xc0005600, 0x401c0000, 0x5dc05800, 0x88000012, 0x5c000200, 0xcd8000f8,
|
||||
0xc1f0000a, 0x715ca000, 0xdd9800f8, 0xdd9c00f9, 0x41d8e000, 0xc5d40260, 0xc0001010, 0xcd4000f8,
|
||||
0x6c9c8000, 0x45c8e000, 0x45c8e000, 0x59dc0004, 0xc1601260, 0xc5d40260, 0x9d000000, 0xc0001012,
|
||||
0xcd4000f8, 0x00000000, 0x00000000, 0xd95800f8, 0x6d586000, 0x4594c000, 0x59984c80, 0xd99800f9,
|
||||
0x5818000a, 0xc1800000, 0xc9800078, 0xc0005400, 0x6d5ca000, 0x401c0000, 0x40180000, 0xc94000f8,
|
||||
0x58000002, 0x00000000, 0xc9c000f8, 0xc0004930, 0xcd4000f8, 0xc0004932, 0xcdc000f8, 0x59980004,
|
||||
0xc1c20020, 0xb59c0018, 0x00000000, 0xc1800000, 0xdd9c00f9, 0x581c000a, 0xcd800078, 0x581c000c,
|
||||
0xc1800000, 0xc9800020, 0xc1c00002, 0xdd9400f8, 0x69d4e000, 0x5d980002, 0xcd800020, 0xc0004924,
|
||||
0xc98000f8, 0x00000000, 0x9d000000, 0x00000000, 0x719cc000, 0xcd8000f8, 0xc000492a, 0xc94000f8,
|
||||
0xc1c00002, 0x69d8e000, 0x7dc0c000, 0x7558a000, 0xcd4000f8, 0xc000492c, 0xc94000f8, 0xdd8000f9,
|
||||
0x58000032, 0x755ca000, 0x84000090, 0xc94000f9, 0xc98000f8, 0xdd8000f9, 0x5800000c, 0x00000000,
|
||||
0xcd4000f9, 0xcd8000f8, 0xc000492c, 0xc94000f8, 0xc000492a, 0xc98000f8, 0x715ca000, 0xc000492c,
|
||||
0xcd4000f8, 0x719cc000, 0xc000492a, 0xcd8000f8, 0x9d000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xc0004862, 0xc98000f8, 0x00000000, 0xc1c00200, 0x4194c000, 0x459ce000, 0x88000012, 0xc5d800f8,
|
||||
0xc0004862, 0xcd8000f8, 0xc0001406, 0xc98000f8, 0xc1c00002, 0x9d000000, 0xc5d80a00, 0xc5581048,
|
||||
0xcd8000f8, 0xc0004930, 0xc98000f8, 0xc0004932, 0xc9c000f8, 0xc140000e, 0xc5581c18, 0xdd9400f8,
|
||||
0xc0005600, 0x40140000, 0x5d405800, 0x88000012, 0x5c000200, 0xcd8000f8, 0x58000002, 0x5d405800,
|
||||
0x88000012, 0x5c000200, 0xcdc000f8, 0xdd5400f8, 0xc1c00000, 0x58140006, 0xc9c20078, 0xc1800000,
|
||||
0x58140000, 0xc98000d8, 0x6ddc2000, 0xc000491e, 0x41d8e000, 0xcdc000f8, 0xdd9800f8, 0xc1c00022,
|
||||
0xc5d80d70, 0xdd9400f9, 0xc5581c18, 0xc000491c, 0xcd8000f8, 0xdd5400f8, 0xc1c00000, 0x58140006,
|
||||
0xc9c20078, 0xc1800000, 0x58140004, 0xc9820078, 0x00000000, 0x59dc0002, 0x45d8c000, 0x84000010,
|
||||
0xc1c00000, 0x9d000000, 0x58140006, 0xc5d81078, 0xcd821078, 0xc0004860, 0xc94000f8, 0xc1820080,
|
||||
0xc1d00002, 0x58146b00, 0xd58000f8, 0x58000002, 0xd58000f9, 0x59540004, 0xb5580018, 0xc0004860,
|
||||
0xc1400000, 0xcd4000f8, 0xdd9800f9, 0x9d000000, 0xdd9400f8, 0xc0001404, 0xcdc10800, 0xc1c00000,
|
||||
0xc1800200, 0x5d980004, 0xdf5d0048, 0x459ca000, 0x8800fff2, 0xdd8000f9, 0x5800000c, 0x00000000,
|
||||
0xc94000f9, 0xc98000f8, 0xc1c00002, 0xc5d43f00, 0xc5d81e00, 0xc0004862, 0xc9c000f8, 0x00000000,
|
||||
0x00000000, 0x581c5600, 0x5dc05800, 0x88000012, 0x5c000200, 0xcd4000f8, 0x58000002, 0x5dc05800,
|
||||
0x88000012, 0x5c000200, 0xcd8000f8, 0xc0004862, 0xc9c000f8, 0x00000000, 0xc15004c0, 0xc5d40060,
|
||||
0xdd9c00f8, 0xc5d41c18, 0xc1c00000, 0xdd8000f9, 0x58000030, 0xc9c00078, 0xdd8000f9, 0x58000002,
|
||||
0xc98000f8, 0x6ddc2000, 0xc000491c, 0x41d8e000, 0xcd4000f9, 0xcdc000f8, 0xdd9400f9, 0xc1c00000,
|
||||
0x58140030, 0xc9c00078, 0xc1800000, 0x58140006, 0xc9820078, 0x00000000, 0x59dc0002, 0x45d8c000,
|
||||
0x84000010, 0xc1c00000, 0x9d000000, 0x58140030, 0xc5d80078, 0xcd800078, 0xc1c00000, 0xdf5c0038,
|
||||
0x5ddc0080, 0x8400ffea, 0x00000000, 0x9d000000, 0x00000000, 0x00000000, 0x00000000, 0xc160fffe,
|
||||
0xc0000a10, 0xc9440060, 0xc1a0fffe, 0x59981e08, 0xc000100c, 0xcd4000f8, 0xc000100e, 0xcd8000f8,
|
||||
0xc0004964, 0xc98000f8, 0x00000000, 0xc170000a, 0x7158a000, 0x6c988000, 0x4588c000, 0x4588c000,
|
||||
0x59980004, 0xc5940270, 0xc0001010, 0xcd4000f8, 0xc0004946, 0xc94000f8, 0x00000000, 0x00000000,
|
||||
0x6d58a000, 0x6d5c4000, 0x459cc000, 0x4594c000, 0xc000494a, 0xc94000f8, 0xc0004948, 0xc9c000f8,
|
||||
0x4194c000, 0xc1400012, 0xc55c1818, 0x9d000000, 0xc59c0268, 0xc0001012, 0xcdc000f8, 0xc1400000,
|
||||
0x58000012, 0xc9410038, 0xc0004950, 0xc9c000f8, 0xc55800f8, 0xc5940838, 0xc5581078, 0xd99400f8,
|
||||
0xc000493c, 0xc94000f8, 0xc0004954, 0xc98000f8, 0x59dc00a8, 0x45d4e000, 0x41d8e000, 0x5d5c0030,
|
||||
0x88000010, 0xc1c00030, 0xc1800000, 0xc5d84028, 0xc1400000, 0xc5d40008, 0x5dd40002, 0x84000072,
|
||||
0x5dd40004, 0x8400009a, 0x5dd40006, 0x840000c2, 0x5dd80026, 0x840000ea, 0xdd5400f8, 0xdd8000f9,
|
||||
0x58000008, 0x40180000, 0xcd4000f8, 0x59980002, 0x8000ffc0, 0xdd5400f8, 0xdd8000f9, 0x58000008,
|
||||
0x40180000, 0xcd4000b8, 0x59980002, 0x8000ff88, 0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000,
|
||||
0xcd400078, 0x59980002, 0x8000ff50, 0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000, 0xcd400038,
|
||||
0x59980002, 0x8000ff18, 0x00000000, 0x9d000000, 0x00000000, 0x00000000, 0x00000000, 0x58000012,
|
||||
0xc94000f8, 0xc0004954, 0xc9c000f8, 0xc0004950, 0xc9400078, 0xdd8000f9, 0x58000028, 0x5d9c0000,
|
||||
0x84000052, 0x5d9c0002, 0x84000052, 0x5d9c0004, 0x8400006a, 0xc55b0038, 0xc55c08b8, 0xcd800039,
|
||||
0xcdc108b8, 0x80000060, 0xcd4000f8, 0x80000050, 0xc55900b8, 0xc55c1838, 0xcd8000b9, 0xcdc31838,
|
||||
0x80000028, 0xc55a0078, 0xc55c1078, 0xcd800079, 0xcdc21078, 0x9d000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x59540002, 0x6994e018, 0x61c0c008, 0x4194a000, 0x5d940040, 0x88000012, 0xc59400f8,
|
||||
0x9d000000, 0xcd4000f8, 0x00000000, 0x00000000, 0x9d000000, 0x4158a000, 0xcd4000f8, 0x00000000,
|
||||
};
|
||||
|
||||
static unsigned int firmware_binary_data[] = {
|
||||
};
|
||||
|
||||
|
||||
#endif // IFXMIPS_ATM_FW_AMAZON_SE_H
|
||||
@ -32,7 +32,7 @@
|
||||
#define ATM_FW_VER_MINOR 16
|
||||
|
||||
|
||||
static unsigned int firmware_binary_code[] = {
|
||||
static unsigned int ar9_fw_bin[] = {
|
||||
0x800004b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000ffe0, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xc1000002, 0xd90c00f8, 0xc2000002, 0xda0800f9, 0x80004980, 0xc2000000, 0xda0800f9, 0x80003fe8,
|
||||
@ -432,7 +432,7 @@ static unsigned int firmware_binary_code[] = {
|
||||
0xcd4000f8, 0x00000000,
|
||||
};
|
||||
|
||||
static unsigned int firmware_binary_data[] = {
|
||||
static unsigned int ar9_fw_data[] = {
|
||||
};
|
||||
|
||||
|
||||
@ -31,9 +31,11 @@
|
||||
|
||||
#define ATM_FW_VER_MAJOR 0
|
||||
#define ATM_FW_VER_MINOR 17
|
||||
// fix 1 upstream packet stuck in TX queue issue
|
||||
// add multiple queue per PVC feature
|
||||
|
||||
|
||||
static unsigned int firmware_binary_code[] = {
|
||||
static unsigned int danube_fw_bin[] = {
|
||||
0x800004A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFC8, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0x80004968, 0xC2000000, 0xDA080001, 0x80003FD0,
|
||||
@ -433,7 +435,7 @@ static unsigned int firmware_binary_code[] = {
|
||||
0xCD400000, 0x00000000,
|
||||
};
|
||||
|
||||
static unsigned int firmware_binary_data[] = {
|
||||
static unsigned int danube_fw_data[] = {
|
||||
};
|
||||
|
||||
|
||||
@ -1,3 +1,30 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_fw_regs_amazon_se.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM (ADSL)
|
||||
**
|
||||
** DATE : 1 AUG 2005
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM Driver (Firmware Registers)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 4 AUG 2005 Xu Liang Initiate Version
|
||||
** 23 OCT 2006 Xu Liang Add GPL header.
|
||||
** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
#ifndef IFXMIPS_ATM_FW_REGS_AMAZON_SE_H
|
||||
#define IFXMIPS_ATM_FW_REGS_AMAZON_SE_H
|
||||
|
||||
@ -6,9 +33,9 @@
|
||||
/*
|
||||
* Host-PPE Communication Data Address Mapping
|
||||
*/
|
||||
#define FW_VER_ID SB_BUFFER(0x2001) /* Firmware Version ID */
|
||||
#define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2401)) /* Firmware Version ID */
|
||||
#define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */
|
||||
//#define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */
|
||||
#define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */
|
||||
#define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */
|
||||
@ -29,7 +29,6 @@
|
||||
#define IFXMIPS_ATM_FW_REGS_COMMON_H
|
||||
|
||||
|
||||
|
||||
#if defined(CONFIG_DANUBE)
|
||||
#include "ifxmips_atm_fw_regs_danube.h"
|
||||
#elif defined(CONFIG_AMAZON_SE)
|
||||
@ -226,10 +225,12 @@ struct wan_mib_table {
|
||||
};
|
||||
|
||||
struct wtx_queue_config {
|
||||
unsigned int res1 :25;
|
||||
unsigned int res1 :16;
|
||||
unsigned int same_vc_qmap:8;
|
||||
unsigned int res2 :1;
|
||||
unsigned int sbid :1;
|
||||
unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to.
|
||||
unsigned int res2 :1;
|
||||
unsigned int res3 :1;
|
||||
unsigned int qsben :1;
|
||||
};
|
||||
|
||||
@ -365,10 +366,12 @@ struct wan_mib_table {
|
||||
|
||||
struct wtx_queue_config {
|
||||
unsigned int qsben :1;
|
||||
unsigned int res2 :1;
|
||||
unsigned int res3 :1;
|
||||
unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to.
|
||||
unsigned int sbid :1;
|
||||
unsigned int res1 :25;
|
||||
unsigned int res2 :1;
|
||||
unsigned int same_vc_qmap:8;
|
||||
unsigned int res1 :16;
|
||||
};
|
||||
|
||||
struct wrx_dma_channel_config
|
||||
@ -0,0 +1,51 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_fw_regs_danube.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM (ADSL)
|
||||
**
|
||||
** DATE : 1 AUG 2005
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM Driver (Firmware Registers)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 4 AUG 2005 Xu Liang Initiate Version
|
||||
** 23 OCT 2006 Xu Liang Add GPL header.
|
||||
** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
#ifndef IFXMIPS_ATM_FW_REGS_DANUBE_H
|
||||
#define IFXMIPS_ATM_FW_REGS_DANUBE_H
|
||||
|
||||
#define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2001))
|
||||
#define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */
|
||||
#define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */
|
||||
#define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */
|
||||
#define WRX_DMACH_ON SB_BUFFER(0x2405) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */
|
||||
#define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */
|
||||
#define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */
|
||||
|
||||
#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20))
|
||||
#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7))
|
||||
#define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i)))
|
||||
#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x2710 + (i) * 27))
|
||||
#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x2711 + (i) * 27))
|
||||
#define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410))
|
||||
#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2000 + (i)))
|
||||
#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2020 + (i)))
|
||||
#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2040 + (i)))
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,72 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_fw_regs_vr9.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM (ADSL)
|
||||
**
|
||||
** DATE : 1 AUG 2005
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM Driver (Firmware Registers)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 4 AUG 2005 Xu Liang Initiate Version
|
||||
** 23 OCT 2006 Xu Liang Add GPL header.
|
||||
** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
#ifndef IFXMIPS_ATM_FW_REGS_VR9_H
|
||||
#define IFXMIPS_ATM_FW_REGS_VR9_H
|
||||
|
||||
#define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2001))
|
||||
|
||||
/* WAN RX HTU Table Size, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRX_HTUTS SB_BUFFER(0x2010)
|
||||
/* WAN RX Queue Number */
|
||||
#define CFG_WRX_QNUM SB_BUFFER(0x2011)
|
||||
/* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRX_DCHNUM SB_BUFFER(0x2012)
|
||||
/* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */
|
||||
#define CFG_WTX_DCHNUM SB_BUFFER(0x2013)
|
||||
/* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRDES_DELAY SB_BUFFER(0x2014)
|
||||
/* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */
|
||||
#define WRX_DMACH_ON SB_BUFFER(0x2015)
|
||||
/* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */
|
||||
#define WTX_DMACH_ON SB_BUFFER(0x2016)
|
||||
/* WAN RX HUNT Threshold, must be between 2 to 8. */
|
||||
#define WRX_HUNT_BITTH SB_BUFFER(0x2017)
|
||||
/* i < 16 */
|
||||
#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config *) SB_BUFFER(0x4C00 + (i) * 20))
|
||||
/* i < 8 */
|
||||
#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config *) SB_BUFFER(0x4F80 + (i) * 7))
|
||||
/* i < 2 */
|
||||
#define WTX_PORT_CONFIG(i) ((struct wtx_port_config *) SB_BUFFER(0x4FB8 + (i)))
|
||||
/* i < 16 */
|
||||
#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config *) SB_BUFFER(0x3A00 + (i) * 27))
|
||||
/* i < 16 */
|
||||
#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config *) SB_BUFFER(0x3A01 + (i) * 27))
|
||||
|
||||
#define WAN_MIB_TABLE ((struct wan_mib_table *) SB_BUFFER(0x4EF0))
|
||||
/* i < 32 */
|
||||
#define HTU_ENTRY(i) ((struct htu_entry *) SB_BUFFER(0x26A0 + (i)))
|
||||
/* i < 32 */
|
||||
#define HTU_MASK(i) ((struct htu_mask *) SB_BUFFER(0x26C0 + (i)))
|
||||
/* i < 32 */
|
||||
#define HTU_RESULT(i) ((struct htu_result *) SB_BUFFER(0x26E0 + (i)))
|
||||
/* bit 0~3 - 0x0F: in showtime, 0x00: not in showtime */
|
||||
#define UTP_CFG SB_BUFFER(0x2018)
|
||||
|
||||
|
||||
|
||||
#endif // IFXMIPS_ATM_FW_REGS_VR9_H
|
||||
@ -32,7 +32,7 @@
|
||||
#define ATM_FW_VER_MINOR 24
|
||||
|
||||
|
||||
static u32 firmware_binary_code[] = {
|
||||
static u32 vr9_fw_bin[] = {
|
||||
0x800004B8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFE0, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xC1000002, 0xD90C00F8, 0xC2000002, 0xDA0800F9, 0x80004390, 0xC2000000, 0xDA0800F9, 0x80003A10,
|
||||
@ -419,7 +419,7 @@ static u32 firmware_binary_code[] = {
|
||||
0xCE0000F8, 0xC000697E, 0xCE4000F8, 0x9D000000, 0x4158A000, 0xCD4000F8, 0x00000000,
|
||||
};
|
||||
|
||||
static u32 firmware_binary_data[] = {
|
||||
static u32 vr9_fw_data[] = {
|
||||
};
|
||||
|
||||
|
||||
@ -1,3 +1,30 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_ppe_amazon_se.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM (ADSL)
|
||||
**
|
||||
** DATE : 1 AUG 2005
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM Driver (PPE Registers)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 4 AUG 2005 Xu Liang Initiate Version
|
||||
** 23 OCT 2006 Xu Liang Add GPL header.
|
||||
** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
#ifndef IFXMIPS_ATM_PPE_AMAZON_SE_H
|
||||
#define IFXMIPS_ATM_PPE_AMAZON_SE_H
|
||||
|
||||
@ -87,7 +114,7 @@
|
||||
/*
|
||||
* Mailbox IGU1 Interrupt
|
||||
*/
|
||||
#define PPE_MAILBOX_IGU1_INT (INT_NUM_IM2_IRL0 + 13)
|
||||
#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL13
|
||||
|
||||
|
||||
|
||||
@ -181,7 +181,7 @@
|
||||
/*
|
||||
* Mailbox IGU1 Interrupt
|
||||
*/
|
||||
#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL0 + 24
|
||||
#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
|
||||
|
||||
|
||||
|
||||
@ -27,7 +27,10 @@
|
||||
|
||||
#ifndef IFXMIPS_ATM_PPE_COMMON_H
|
||||
#define IFXMIPS_ATM_PPE_COMMON_H
|
||||
#if defined(CONFIG_DANUBE)
|
||||
|
||||
|
||||
|
||||
#if defined(CONFIG_DANUBE)
|
||||
#include "ifxmips_atm_ppe_danube.h"
|
||||
#elif defined(CONFIG_AMAZON_SE)
|
||||
#include "ifxmips_atm_ppe_amazon_se.h"
|
||||
@ -28,7 +28,7 @@
|
||||
#ifndef IFXMIPS_ATM_PPE_DANUBE_H
|
||||
#define IFXMIPS_ATM_PPE_DANUBE_H
|
||||
|
||||
#include <lantiq.h>
|
||||
|
||||
|
||||
/*
|
||||
* FPI Configuration Bus Register and Memory Address Mapping
|
||||
@ -122,8 +122,7 @@
|
||||
/*
|
||||
* Mailbox IGU1 Interrupt
|
||||
*/
|
||||
#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
|
||||
#define PPE_MAILBOX_IGU1_INT LTQ_PPE_MBOX_INT
|
||||
#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
|
||||
|
||||
|
||||
|
||||
@ -185,7 +185,7 @@
|
||||
/*
|
||||
* Mailbox IGU1 Interrupt
|
||||
*/
|
||||
#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL0 + 24
|
||||
#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
|
||||
|
||||
|
||||
|
||||
190
package/platform/lantiq/ltq-atm/src/ifxmips_atm_vr9.c
Normal file
190
package/platform/lantiq/ltq-atm/src/ifxmips_atm_vr9.c
Normal file
@ -0,0 +1,190 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_vr9.c
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM
|
||||
**
|
||||
** DATE : 7 Jul 2009
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM driver common source file (core functions)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 07 JUL 2009 Xu Liang Init Version
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Head File
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* Common Head File
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioctl.h>
|
||||
#include <asm/delay.h>
|
||||
|
||||
#include "ifxmips_atm_core.h"
|
||||
#include "ifxmips_atm_fw_vr9.h"
|
||||
|
||||
#ifdef CONFIG_VR9
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
||||
#define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
|
||||
#define IFX_PMU_MODULE_PPE_TC BIT(21)
|
||||
#define IFX_PMU_MODULE_PPE_EMA BIT(22)
|
||||
#define IFX_PMU_MODULE_PPE_QSB BIT(18)
|
||||
#define IFX_PMU_MODULE_AHBS BIT(13)
|
||||
#define IFX_PMU_MODULE_DSL_DFE BIT(9)
|
||||
|
||||
static inline void vr9_reset_ppe(void)
|
||||
{
|
||||
/*#ifdef MODULE
|
||||
// reset PPE
|
||||
ifx_rcu_rst(IFX_RCU_DOMAIN_DSLDFE, IFX_RCU_MODULE_ATM);
|
||||
udelay(1000);
|
||||
ifx_rcu_rst(IFX_RCU_DOMAIN_DSLTC, IFX_RCU_MODULE_ATM);
|
||||
udelay(1000);
|
||||
ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
|
||||
udelay(1000);
|
||||
*PP32_SRST &= ~0x000303CF;
|
||||
udelay(1000);
|
||||
*PP32_SRST |= 0x000303CF;
|
||||
udelay(1000);
|
||||
#endif*/
|
||||
}
|
||||
|
||||
static inline int vr9_pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
|
||||
{
|
||||
unsigned int clr, set;
|
||||
volatile u32 *dest;
|
||||
|
||||
if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
|
||||
|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
|
||||
return -1;
|
||||
|
||||
clr = pp32 ? 0xF0 : 0x0F;
|
||||
if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
|
||||
set = pp32 ? (3 << 6): (2 << 2);
|
||||
else
|
||||
set = 0x00;
|
||||
IFX_REG_W32_MASK(clr, set, CDM_CFG);
|
||||
|
||||
dest = CDM_CODE_MEMORY(pp32, 0);
|
||||
while ( code_dword_len-- > 0 )
|
||||
IFX_REG_W32(*code_src++, dest++);
|
||||
|
||||
dest = CDM_DATA_MEMORY(pp32, 0);
|
||||
while ( data_dword_len-- > 0 )
|
||||
IFX_REG_W32(*data_src++, dest++);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void vr9_fw_ver(unsigned int *major, unsigned int *minor)
|
||||
{
|
||||
|
||||
*major = FW_VER_ID->major;
|
||||
*minor = FW_VER_ID->minor;
|
||||
}
|
||||
|
||||
static void vr9_init(void)
|
||||
{
|
||||
volatile u32 *p;
|
||||
unsigned int i;
|
||||
|
||||
/* setup pmu */
|
||||
ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
|
||||
IFX_PMU_MODULE_PPE_TC |
|
||||
IFX_PMU_MODULE_PPE_EMA |
|
||||
IFX_PMU_MODULE_PPE_QSB |
|
||||
IFX_PMU_MODULE_AHBS |
|
||||
IFX_PMU_MODULE_DSL_DFE);
|
||||
|
||||
vr9_reset_ppe();
|
||||
|
||||
/* pdma init */
|
||||
IFX_REG_W32(0x08, PDMA_CFG);
|
||||
IFX_REG_W32(0x00203580, SAR_PDMA_RX_CMDBUF_CFG);
|
||||
IFX_REG_W32(0x004035A0, SAR_PDMA_RX_FW_CMDBUF_CFG);
|
||||
|
||||
/* mailbox init */
|
||||
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
|
||||
IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
|
||||
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
|
||||
IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
|
||||
|
||||
/* tc init - clear sync state */
|
||||
*SFSM_STATE0 = 0;
|
||||
*SFSM_STATE1 = 0;
|
||||
|
||||
/* init shared buffer */
|
||||
p = SB_RAM0_ADDR(0);
|
||||
for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
|
||||
IFX_REG_W32(0, p++);
|
||||
|
||||
p = SB_RAM6_ADDR(0);
|
||||
for ( i = 0; i < SB_RAM6_DWLEN; i++ )
|
||||
IFX_REG_W32(0, p++);
|
||||
}
|
||||
|
||||
static void vr9_shutdown(void)
|
||||
{
|
||||
}
|
||||
|
||||
static int vr9_start(int pp32)
|
||||
{
|
||||
unsigned int mask = 1 << (pp32 << 4);
|
||||
int ret;
|
||||
|
||||
/* download firmware */
|
||||
ret = vr9_pp32_download_code(pp32,
|
||||
vr9_fw_bin, sizeof(vr9_fw_bin) / sizeof(*vr9_fw_bin),
|
||||
vr9_fw_data, sizeof(vr9_fw_data) / sizeof(*vr9_fw_data));
|
||||
if ( ret != 0 )
|
||||
return ret;
|
||||
|
||||
/* run PP32 */
|
||||
IFX_REG_W32_MASK(mask, 0, PP32_FREEZE);
|
||||
|
||||
/* idle for a while to let PP32 init itself */
|
||||
udelay(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void vr9_stop(int pp32)
|
||||
{
|
||||
unsigned int mask = 1 << (pp32 << 4);
|
||||
|
||||
IFX_REG_W32_MASK(0, mask, PP32_FREEZE);
|
||||
}
|
||||
|
||||
struct ltq_atm_ops vr9_ops = {
|
||||
.init = vr9_init,
|
||||
.shutdown = vr9_shutdown,
|
||||
.start = vr9_start,
|
||||
.stop = vr9_stop,
|
||||
.fw_ver = vr9_fw_ver,
|
||||
};
|
||||
|
||||
#endif
|
||||
1897
package/platform/lantiq/ltq-atm/src/ltq_atm.c
Normal file
1897
package/platform/lantiq/ltq-atm/src/ltq_atm.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,53 +0,0 @@
|
||||
#
|
||||
# Copyright (C) 2011 OpenWrt.org
|
||||
#
|
||||
# This is free software, licensed under the GNU General Public License v2.
|
||||
# See /LICENSE for more information.
|
||||
#
|
||||
|
||||
include $(TOPDIR)/rules.mk
|
||||
|
||||
PKG_NAME:=ltq-dsl-fw
|
||||
PKG_VERSION:=0.1
|
||||
PKG_RELEASE:=1
|
||||
|
||||
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
|
||||
PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/
|
||||
PKG_MD5SUM:=4700a36b66b955b4c5544227267356f4
|
||||
PKG_MAINTAINER:=John Crispin <blogic@openwrt.org>
|
||||
|
||||
include $(INCLUDE_DIR)/package.mk
|
||||
|
||||
define Package/kmod-ltq-dsl-firmware-template
|
||||
TITLE+=Firmware Annex-$(1) $(2)
|
||||
SECTION:=sys
|
||||
CATEGORY:=Kernel modules
|
||||
SUBMENU:=Network Devices
|
||||
VARIANT:= $(1)-$(2)
|
||||
URL:=http://www.lantiq.com/
|
||||
DEPENDS:=@(TARGET_lantiq_$(2)||TARGET_lantiq_$(3)) kmod-ltq-dsl-$(2)
|
||||
endef
|
||||
|
||||
Package/kmod-ltq-dsl-firmware-a-danube=$(call Package/kmod-ltq-dsl-firmware-template,a,danube,xway)
|
||||
Package/kmod-ltq-dsl-firmware-b-danube=$(call Package/kmod-ltq-dsl-firmware-template,b,danube,xway)
|
||||
Package/kmod-ltq-dsl-firmware-a-ar9=$(call Package/kmod-ltq-dsl-firmware-template,a,ar9,xway)
|
||||
Package/kmod-ltq-dsl-firmware-b-ar9=$(call Package/kmod-ltq-dsl-firmware-template,b,ar9,xway)
|
||||
Package/kmod-ltq-dsl-firmware-a-ase=$(call Package/kmod-ltq-dsl-firmware-template,a,ase,ase)
|
||||
Package/kmod-ltq-dsl-firmware-b-ase=$(call Package/kmod-ltq-dsl-firmware-template,b,ase,ase)
|
||||
|
||||
define Build/Compile
|
||||
echo
|
||||
endef
|
||||
|
||||
define Package/kmod-ltq-dsl-firmware-$(BUILD_VARIANT)/install
|
||||
$(INSTALL_DIR) $(1)/lib/firmware/
|
||||
$(CP) $(PKG_BUILD_DIR)/$(FW_NAME)/ltq-dsl-fw-$(BUILD_VARIANT).bin $(1)/lib/firmware/
|
||||
ln -s /lib/firmware/$(FW_NAME)/ltq-dsl-fw-$(BUILD_VARIANT).bin $(1)/lib/firmware/ModemHWE.bin
|
||||
endef
|
||||
|
||||
$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-a-danube))
|
||||
$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-b-danube))
|
||||
$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-a-ase))
|
||||
$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-b-ase))
|
||||
$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-a-ar9))
|
||||
$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-b-ar9))
|
||||
@ -1,125 +0,0 @@
|
||||
--- a/src/include/drv_dsl_cpe_device_danube.h
|
||||
+++ b/src/include/drv_dsl_cpe_device_danube.h
|
||||
@@ -24,7 +24,7 @@
|
||||
#include "drv_dsl_cpe_simulator_danube.h"
|
||||
#else
|
||||
/* Include for the low level driver interface header file */
|
||||
-#include "asm/ifx/ifx_mei_bsp.h"
|
||||
+#include "mei/ifxmips_mei_interface.h"
|
||||
#endif /* defined(DSL_CPE_SIMULATOR_DRIVER) && defined(WIN32)*/
|
||||
|
||||
#define DSL_MAX_LINE_NUMBER 1
|
||||
--- a/src/common/drv_dsl_cpe_os_linux.c
|
||||
+++ b/src/common/drv_dsl_cpe_os_linux.c
|
||||
@@ -11,6 +11,7 @@
|
||||
#ifdef __LINUX__
|
||||
|
||||
#define DSL_INTERN
|
||||
+#include <linux/device.h>
|
||||
|
||||
#include "drv_dsl_cpe_api.h"
|
||||
#include "drv_dsl_cpe_api_ioctl.h"
|
||||
@@ -34,9 +35,13 @@
|
||||
static DSL_ssize_t DSL_DRV_Write(DSL_DRV_file_t *pFile, const DSL_char_t * pBuf,
|
||||
DSL_DRV_size_t nSize, DSL_DRV_offset_t * pLoff);
|
||||
|
||||
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
|
||||
static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode, DSL_DRV_file_t * pFile,
|
||||
DSL_uint_t nCommand, unsigned long nArg);
|
||||
-
|
||||
+#else
|
||||
+static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_file_t * pFile,
|
||||
+ DSL_uint_t nCommand, unsigned long nArg);
|
||||
+#endif
|
||||
static int DSL_DRV_Open(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);
|
||||
|
||||
static int DSL_DRV_Release(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);
|
||||
@@ -72,7 +77,11 @@
|
||||
open: DSL_DRV_Open,
|
||||
release: DSL_DRV_Release,
|
||||
write: DSL_DRV_Write,
|
||||
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
|
||||
ioctl: DSL_DRV_Ioctls,
|
||||
+#else
|
||||
+ unlocked_ioctl: DSL_DRV_Ioctls,
|
||||
+#endif
|
||||
poll: DSL_DRV_Poll
|
||||
};
|
||||
#else
|
||||
@@ -168,10 +177,17 @@
|
||||
\return Success or failure.
|
||||
\ingroup Internal
|
||||
*/
|
||||
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
|
||||
static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode,
|
||||
DSL_DRV_file_t * pFile,
|
||||
DSL_uint_t nCommand,
|
||||
unsigned long nArg)
|
||||
+#else
|
||||
+static DSL_int_t DSL_DRV_Ioctls(
|
||||
+ DSL_DRV_file_t * pFile,
|
||||
+ DSL_uint_t nCommand,
|
||||
+ unsigned long nArg)
|
||||
+#endif
|
||||
{
|
||||
DSL_int_t nErr=0;
|
||||
DSL_boolean_t bIsInKernel;
|
||||
@@ -216,16 +232,7 @@
|
||||
}
|
||||
}
|
||||
}
|
||||
-
|
||||
- if (pINode == DSL_NULL)
|
||||
- {
|
||||
- bIsInKernel = DSL_TRUE;
|
||||
- }
|
||||
- else
|
||||
- {
|
||||
- bIsInKernel = DSL_FALSE;
|
||||
- }
|
||||
-
|
||||
+ bIsInKernel = DSL_FALSE;
|
||||
if ( (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API) ||
|
||||
(_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_G997) ||
|
||||
(_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_PM) ||
|
||||
@@ -1058,6 +1065,7 @@
|
||||
/* Entry point of driver */
|
||||
int __init DSL_ModuleInit(void)
|
||||
{
|
||||
+ struct class *dsl_class;
|
||||
DSL_int_t i;
|
||||
|
||||
printk(DSL_DRV_CRLF DSL_DRV_CRLF "Infineon CPE API Driver version: %s" DSL_DRV_CRLF,
|
||||
@@ -1104,7 +1112,8 @@
|
||||
}
|
||||
|
||||
DSL_DRV_DevNodeInit();
|
||||
-
|
||||
+ dsl_class = class_create(THIS_MODULE, "dsl_cpe_api");
|
||||
+ device_create(dsl_class, NULL, MKDEV(DRV_DSL_CPE_API_DEV_MAJOR, 0), NULL, "dsl_cpe_api");
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- a/src/include/drv_dsl_cpe_os_linux.h
|
||||
+++ b/src/include/drv_dsl_cpe_os_linux.h
|
||||
@@ -17,17 +17,17 @@
|
||||
#endif
|
||||
|
||||
#include <asm/ioctl.h>
|
||||
-#include <linux/autoconf.h>
|
||||
+#include <generated/autoconf.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/spinlock.h>
|
||||
-
|
||||
+#include <linux/sched.h>
|
||||
|
||||
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
|
||||
- #include <linux/utsrelease.h>
|
||||
+ #include <generated/utsrelease.h>
|
||||
#endif
|
||||
|
||||
#include <linux/types.h>
|
||||
@ -1,227 +0,0 @@
|
||||
--- a/configure.in
|
||||
+++ b/configure.in
|
||||
@@ -310,7 +310,7 @@
|
||||
AC_ARG_ENABLE(kernelbuild,
|
||||
AC_HELP_STRING(--enable-kernel-build=x,Set the target kernel build path),
|
||||
[
|
||||
- if test -e $enableval/include/linux/autoconf.h; then
|
||||
+ if test -e $enableval/include/linux/autoconf.h -o -e $enableval/include/generated/autoconf.h; then
|
||||
AC_SUBST([KERNEL_BUILD_PATH],[$enableval])
|
||||
else
|
||||
AC_MSG_ERROR([The kernel build directory is not valid or not configured!])
|
||||
@@ -333,12 +333,12 @@
|
||||
echo Set the lib_ifxos include path $enableval
|
||||
AC_SUBST([IFXOS_INCLUDE_PATH],[$enableval])
|
||||
else
|
||||
- echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
|
||||
+ echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
|
||||
AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
|
||||
fi
|
||||
],
|
||||
[
|
||||
- echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
|
||||
+ echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
|
||||
AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
|
||||
]
|
||||
)
|
||||
@@ -1702,73 +1702,73 @@
|
||||
AC_SUBST([DISTCHECK_CONFIGURE_PARAMS],[$CONFIGURE_OPTIONS])
|
||||
|
||||
AC_CONFIG_COMMANDS_PRE([
|
||||
-echo -e "------------------------------------------------------------------------"
|
||||
-echo -e " Configuration for drv_dsl_cpe_api:"
|
||||
-echo -e " Configure model type: $DSL_CONFIG_MODEL_TYPE"
|
||||
-echo -e " Source code location: $srcdir"
|
||||
-echo -e " Compiler: $CC"
|
||||
-echo -e " Compiler c-flags: $CFLAGS"
|
||||
-echo -e " Extra compiler c-flags: $EXTRA_DRV_CFLAGS"
|
||||
-echo -e " Host System Type: $host"
|
||||
-echo -e " Install path: $prefix"
|
||||
-echo -e " Linux kernel include path: $KERNEL_INCL_PATH"
|
||||
-echo -e " Linux kernel build path: $KERNEL_BUILD_PATH"
|
||||
-echo -e " Linux kernel architecture: $KERNEL_ARCH"
|
||||
-echo -e " Include IFXOS: $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
|
||||
-echo -e " IFXOS include path: $IFXOS_INCLUDE_PATH"
|
||||
-echo -e " Driver Include Path $DSL_DRIVER_INCL_PATH"
|
||||
-echo -e " DSL device: $DSL_DEVICE_NAME"
|
||||
-echo -e " Max device number: $DSL_DRV_MAX_DEVICE_NUMBER"
|
||||
-echo -e " Channels per line: $DSL_CHANNELS_PER_LINE"
|
||||
-echo -e " Build lib (only for kernel 2.6) $DSL_CPE_API_LIBRARY_BUILD_2_6"
|
||||
-echo -e " DSL data led flash frequency: $DSL_DATA_LED_FLASH_FREQUENCY Hz"
|
||||
-echo -e " Disable debug prints: $DSL_DEBUG_DISABLE"
|
||||
-echo -e " Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
|
||||
-echo -e " Preselected max. debug level: $DSL_DBG_MAX_LEVEL_PRE"
|
||||
-echo -e " Include deprecated functions: $INCLUDE_DEPRECATED"
|
||||
-echo -e " Include Device Exception Codes: $INCLUDE_DEVICE_EXCEPTION_CODES"
|
||||
-echo -e " Include FW request support: $INCLUDE_FW_REQUEST_SUPPORT"
|
||||
-echo -e " Include ADSL trace buffer: $INCLUDE_DSL_CPE_TRACE_BUFFER"
|
||||
-echo -e " Include ADSL MIB: $INCLUDE_DSL_ADSL_MIB"
|
||||
-echo -e " Include ADSL LED: $INCLUDE_ADSL_LED"
|
||||
-echo -e " Include CEOC: $INCLUDE_DSL_CEOC"
|
||||
-echo -e " Include config get support: $INCLUDE_DSL_CONFIG_GET"
|
||||
-echo -e " Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
|
||||
-echo -e " Include Resource Statistics: $INCLUDE_DSL_RESOURCE_STATISTICS"
|
||||
-echo -e " Include Framing Parameters: $INCLUDE_DSL_FRAMING_PARAMETERS"
|
||||
-echo -e " Include G997 Line Inventory: $INCLUDE_DSL_G997_LINE_INVENTORY"
|
||||
-echo -e " Include G997 Framing Parameters: $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
|
||||
-echo -e " Include G997 per tone data: $INCLUDE_DSL_G997_PER_TONE"
|
||||
-echo -e " Include G997 status: $INCLUDE_DSL_G997_STATUS"
|
||||
-echo -e " Include G997 alarm: $INCLUDE_DSL_G997_ALARM"
|
||||
-echo -e " Include DSL Bonding: $INCLUDE_DSL_BONDING"
|
||||
-echo -e " Include Misc Line Status $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
|
||||
-echo -e " Include DELT: $INCLUDE_DSL_DELT"
|
||||
-echo -e " Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
|
||||
-echo -e " Include PM: $INCLUDE_DSL_PM"
|
||||
-echo -e " Include PM config: $INCLUDE_DSL_CPE_PM_CONFIG"
|
||||
-echo -e " Include PM total: $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
|
||||
-echo -e " Include PM history: $INCLUDE_DSL_CPE_PM_HISTORY"
|
||||
-echo -e " Include PM showtime: $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
|
||||
-echo -e " Include PM optional: $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
|
||||
-echo -e " Include PM line: $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
|
||||
-echo -e " Include PM line event showtime: $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
|
||||
-echo -e " Include PM channel: $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
|
||||
-echo -e " Include PM channel extended: $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
|
||||
-echo -e " Include PM data path: $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
|
||||
-echo -e " Include PM data path failure: $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
|
||||
-echo -e " Include PM ReTx: $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
|
||||
-echo -e " Include PM line threshold: $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
|
||||
-echo -e " Include PM channel threshold: $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
|
||||
-echo -e " Include PM data path threshold: $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
|
||||
-echo -e " Include PM ReTx threshold: $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
|
||||
-echo -e " Include FW memory free support: $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
|
||||
-echo -e "----------------------- deprectated ! ----------------------------------"
|
||||
-echo -e " Include PM line failure: $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
|
||||
-echo -e ""
|
||||
-echo -e " Settings:"
|
||||
-echo -e " Configure options: $CONFIGURE_OPTIONS"
|
||||
-echo -e "------------------------------------------------------------------------"
|
||||
+echo "------------------------------------------------------------------------"
|
||||
+echo " Configuration for drv_dsl_cpe_api:"
|
||||
+echo " Configure model type: $DSL_CONFIG_MODEL_TYPE"
|
||||
+echo " Source code location: $srcdir"
|
||||
+echo " Compiler: $CC"
|
||||
+echo " Compiler c-flags: $CFLAGS"
|
||||
+echo " Extra compiler c-flags: $EXTRA_DRV_CFLAGS"
|
||||
+echo " Host System Type: $host"
|
||||
+echo " Install path: $prefix"
|
||||
+echo " Linux kernel include path: $KERNEL_INCL_PATH"
|
||||
+echo " Linux kernel build path: $KERNEL_BUILD_PATH"
|
||||
+echo " Linux kernel architecture: $KERNEL_ARCH"
|
||||
+echo " Include IFXOS: $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
|
||||
+echo " IFXOS include path: $IFXOS_INCLUDE_PATH"
|
||||
+echo " Driver Include Path $DSL_DRIVER_INCL_PATH"
|
||||
+echo " DSL device: $DSL_DEVICE_NAME"
|
||||
+echo " Max device number: $DSL_DRV_MAX_DEVICE_NUMBER"
|
||||
+echo " Channels per line: $DSL_CHANNELS_PER_LINE"
|
||||
+echo " Build lib (only for kernel 2.6) $DSL_CPE_API_LIBRARY_BUILD_2_6"
|
||||
+echo " DSL data led flash frequency: $DSL_DATA_LED_FLASH_FREQUENCY Hz"
|
||||
+echo " Disable debug prints: $DSL_DEBUG_DISABLE"
|
||||
+echo " Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
|
||||
+echo " Preselected max. debug level: $DSL_DBG_MAX_LEVEL_PRE"
|
||||
+echo " Include deprecated functions: $INCLUDE_DEPRECATED"
|
||||
+echo " Include Device Exception Codes: $INCLUDE_DEVICE_EXCEPTION_CODES"
|
||||
+echo " Include FW request support: $INCLUDE_FW_REQUEST_SUPPORT"
|
||||
+echo " Include ADSL trace buffer: $INCLUDE_DSL_CPE_TRACE_BUFFER"
|
||||
+echo " Include ADSL MIB: $INCLUDE_DSL_ADSL_MIB"
|
||||
+echo " Include ADSL LED: $INCLUDE_ADSL_LED"
|
||||
+echo " Include CEOC: $INCLUDE_DSL_CEOC"
|
||||
+echo " Include config get support: $INCLUDE_DSL_CONFIG_GET"
|
||||
+echo " Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
|
||||
+echo " Include Resource Statistics: $INCLUDE_DSL_RESOURCE_STATISTICS"
|
||||
+echo " Include Framing Parameters: $INCLUDE_DSL_FRAMING_PARAMETERS"
|
||||
+echo " Include G997 Line Inventory: $INCLUDE_DSL_G997_LINE_INVENTORY"
|
||||
+echo " Include G997 Framing Parameters: $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
|
||||
+echo " Include G997 per tone data: $INCLUDE_DSL_G997_PER_TONE"
|
||||
+echo " Include G997 status: $INCLUDE_DSL_G997_STATUS"
|
||||
+echo " Include G997 alarm: $INCLUDE_DSL_G997_ALARM"
|
||||
+echo " Include DSL Bonding: $INCLUDE_DSL_BONDING"
|
||||
+echo " Include Misc Line Status $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
|
||||
+echo " Include DELT: $INCLUDE_DSL_DELT"
|
||||
+echo " Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
|
||||
+echo " Include PM: $INCLUDE_DSL_PM"
|
||||
+echo " Include PM config: $INCLUDE_DSL_CPE_PM_CONFIG"
|
||||
+echo " Include PM total: $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
|
||||
+echo " Include PM history: $INCLUDE_DSL_CPE_PM_HISTORY"
|
||||
+echo " Include PM showtime: $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
|
||||
+echo " Include PM optional: $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
|
||||
+echo " Include PM line: $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
|
||||
+echo " Include PM line event showtime: $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
|
||||
+echo " Include PM channel: $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
|
||||
+echo " Include PM channel extended: $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
|
||||
+echo " Include PM data path: $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
|
||||
+echo " Include PM data path failure: $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
|
||||
+echo " Include PM ReTx: $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
|
||||
+echo " Include PM line threshold: $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
|
||||
+echo " Include PM channel threshold: $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
|
||||
+echo " Include PM data path threshold: $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
|
||||
+echo " Include PM ReTx threshold: $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
|
||||
+echo " Include FW memory free support: $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
|
||||
+echo "----------------------- deprectated ! ----------------------------------"
|
||||
+echo " Include PM line failure: $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
|
||||
+echo ""
|
||||
+echo " Settings:"
|
||||
+echo " Configure options: $CONFIGURE_OPTIONS"
|
||||
+echo "------------------------------------------------------------------------"
|
||||
])
|
||||
|
||||
AC_CONFIG_FILES([Makefile src/Makefile])
|
||||
--- a/src/Makefile.am
|
||||
+++ b/src/Makefile.am
|
||||
@@ -303,7 +303,7 @@
|
||||
drv_dsl_cpe_api_OBJS = "$(subst .c,.o,$(filter %.c,$(drv_dsl_cpe_api_SOURCES)))"
|
||||
|
||||
drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SOURCES)
|
||||
- @echo -e "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
|
||||
+ @echo "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
|
||||
if test ! -e common/drv_dsl_cpe_api.c ; then \
|
||||
echo "copy source files (as links only!)"; \
|
||||
for f in $(filter %.c,$(drv_dsl_cpe_api_SOURCES)); do \
|
||||
@@ -311,10 +311,10 @@
|
||||
cp -s $(addprefix @abs_srcdir@/,$$f) $(PWD)/`dirname $$f`/ ; \
|
||||
done \
|
||||
fi
|
||||
- @echo -e "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
|
||||
- @echo -e "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild
|
||||
- @echo -e "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)" >> $(PWD)/Kbuild
|
||||
- @echo -e "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild
|
||||
+ @echo "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
|
||||
+ @echo "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild
|
||||
+ @echo "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)" >> $(PWD)/Kbuild
|
||||
+ @echo "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild
|
||||
$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules
|
||||
|
||||
clean-generic:
|
||||
--- a/src/include/drv_dsl_cpe_os_linux.h
|
||||
+++ b/src/include/drv_dsl_cpe_os_linux.h
|
||||
@@ -16,8 +16,6 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
-#include <asm/ioctl.h>
|
||||
-#include <generated/autoconf.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
@@ -26,8 +24,10 @@
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/sched.h>
|
||||
|
||||
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
|
||||
- #include <generated/utsrelease.h>
|
||||
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))
|
||||
+#include <linux/utsrelease.h>
|
||||
+#else
|
||||
+#include <generated/utsrelease.h>
|
||||
#endif
|
||||
|
||||
#include <linux/types.h>
|
||||
@@ -39,7 +39,8 @@
|
||||
#include <linux/delay.h>
|
||||
#include <linux/poll.h>
|
||||
#include <asm/uaccess.h>
|
||||
-#include <linux/smp_lock.h>
|
||||
+//#include <linux/smp_lock.h>
|
||||
+#include <asm/ioctl.h>
|
||||
|
||||
#ifdef INCLUDE_DSL_CPE_API_IFXOS_SUPPORT
|
||||
/** IFXOS includes*/
|
||||
@ -1,25 +0,0 @@
|
||||
obj-m = lantiq_mei.o lantiq_atm.o
|
||||
lantiq_atm-objs := ifxmips_atm_core.o
|
||||
|
||||
CFLAGS_MODULE+=-DSOC_TYPE_XWAY
|
||||
EXTRA_CFLAGS+=-DSOC_TYPE_XWAY
|
||||
ifeq ($(BUILD_VARIANT),danube)
|
||||
CFLAGS_MODULE+=-DCONFIG_DANUBE
|
||||
EXTRA_CFLAGS+=-DCONFIG_DANUBE
|
||||
lantiq_atm-objs += ifxmips_atm_danube.o
|
||||
endif
|
||||
ifeq ($(BUILD_VARIANT),ase)
|
||||
CFLAGS_MODULE+=-DCONFIG_AMAZON_SE
|
||||
EXTRA_CFLAGS+=-DCONFIG_AMAZON_SE
|
||||
lantiq_atm-objs += ifxmips_atm_amazon_se.o
|
||||
endif
|
||||
ifeq ($(BUILD_VARIANT),ar9)
|
||||
CFLAGS_MODULE+=-DCONFIG_AR9
|
||||
EXTRA_CFLAGS+=-DCONFIG_AR9
|
||||
lantiq_atm-objs += ifxmips_atm_ar9.o
|
||||
endif
|
||||
ifeq ($(BUILD_VARIANT),vr9)
|
||||
CFLAGS_MODULE+=-DCONFIG_VR9
|
||||
EXTRA_CFLAGS+=-DCONFIG_VR9
|
||||
lantiq_atm-objs += ifxmips_atm_vr9.o
|
||||
endif
|
||||
@ -1,196 +0,0 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifx_atm.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM
|
||||
**
|
||||
** DATE : 17 Jun 2009
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : Global ATM driver header file
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 07 JUL 2009 Xu Liang Init Version
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef IFX_ATM_H
|
||||
#define IFX_ATM_H
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM UEIP Project - ATM driver module
|
||||
\brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM_IOCTL IOCTL Commands
|
||||
\ingroup IFX_ATM
|
||||
\brief IOCTL Commands used by user application.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM_STRUCT Structures
|
||||
\ingroup IFX_ATM
|
||||
\brief Structures used by user application.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\file ifx_atm.h
|
||||
\ingroup IFX_ATM
|
||||
\brief ATM driver header file
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Definition
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
\addtogroup IFX_ATM_STRUCT
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/*
|
||||
* ATM MIB
|
||||
*/
|
||||
|
||||
/*!
|
||||
\struct atm_cell_ifEntry_t
|
||||
\brief Structure used for Cell Level MIB Counters.
|
||||
|
||||
User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
|
||||
*/
|
||||
typedef struct {
|
||||
__u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
|
||||
__u32 ifInErrors; /*!< counter of error ingress cells */
|
||||
__u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
|
||||
__u32 ifOutErrors; /*!< counter of error egress cells */
|
||||
} atm_cell_ifEntry_t;
|
||||
|
||||
/*!
|
||||
\struct atm_aal5_ifEntry_t
|
||||
\brief Structure used for AAL5 Frame Level MIB Counters.
|
||||
|
||||
User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
|
||||
*/
|
||||
typedef struct {
|
||||
__u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
|
||||
__u32 ifInUcastPkts; /*!< counter of ingress packets */
|
||||
__u32 ifOutUcastPkts; /*!< counter of egress packets */
|
||||
__u32 ifInErrors; /*!< counter of error ingress packets */
|
||||
__u32 ifInDiscards; /*!< counter of dropped ingress packets */
|
||||
__u32 ifOutErros; /*!< counter of error egress packets */
|
||||
__u32 ifOutDiscards; /*!< counter of dropped egress packets */
|
||||
} atm_aal5_ifEntry_t;
|
||||
|
||||
/*!
|
||||
\struct atm_aal5_vcc_t
|
||||
\brief Structure used for per PVC AAL5 Frame Level MIB Counters.
|
||||
|
||||
This structure is a part of structure "atm_aal5_vcc_x_t".
|
||||
*/
|
||||
typedef struct {
|
||||
__u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
|
||||
__u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
|
||||
__u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
|
||||
} atm_aal5_vcc_t;
|
||||
|
||||
/*!
|
||||
\struct atm_aal5_vcc_x_t
|
||||
\brief Structure used for per PVC AAL5 Frame Level MIB Counters.
|
||||
|
||||
User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
|
||||
*/
|
||||
typedef struct {
|
||||
int vpi; /*!< VPI of the VCC to get MIB counters */
|
||||
int vci; /*!< VCI of the VCC to get MIB counters */
|
||||
atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
|
||||
} atm_aal5_vcc_x_t;
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* IOCTL
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
\addtogroup IFX_ATM_IOCTL
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/*
|
||||
* ioctl Command
|
||||
*/
|
||||
/*!
|
||||
\brief ATM IOCTL Magic Number
|
||||
*/
|
||||
#define PPE_ATM_IOC_MAGIC 'o'
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get Cell Level MIB Counters
|
||||
|
||||
This command is obsolete. User can get cell level MIB from DSL API.
|
||||
This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get AAL5 Level MIB Counters
|
||||
|
||||
Get AAL5 packet counters.
|
||||
This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get Per PVC MIB Counters
|
||||
|
||||
Get AAL5 packet counters for each PVC.
|
||||
This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
|
||||
/*!
|
||||
\brief Total Number of ATM IOCTL Commands
|
||||
*/
|
||||
#define PPE_ATM_IOC_MAXNR 3
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* API
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
#ifdef __KERNEL__
|
||||
struct port_cell_info {
|
||||
unsigned int port_num;
|
||||
unsigned int tx_link_rate[2];
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif // IFX_ATM_H
|
||||
|
||||
@ -1,172 +0,0 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifx_atm.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM
|
||||
**
|
||||
** DATE : 17 Jun 2009
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : Global ATM driver header file
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 07 JUL 2009 Xu Liang Init Version
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef IFX_ATM_H
|
||||
#define IFX_ATM_H
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM UEIP Project - ATM driver module
|
||||
\brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM_IOCTL IOCTL Commands
|
||||
\ingroup IFX_ATM
|
||||
\brief IOCTL Commands used by user application.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM_STRUCT Structures
|
||||
\ingroup IFX_ATM
|
||||
\brief Structures used by user application.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\file ifx_atm.h
|
||||
\ingroup IFX_ATM
|
||||
\brief ATM driver header file
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Definition
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
\addtogroup IFX_ATM_STRUCT
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/*
|
||||
* ATM MIB
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
__u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
|
||||
__u32 ifInErrors; /*!< counter of error ingress cells */
|
||||
__u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
|
||||
__u32 ifOutErrors; /*!< counter of error egress cells */
|
||||
} atm_cell_ifEntry_t;
|
||||
|
||||
typedef struct {
|
||||
__u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
|
||||
__u32 ifInUcastPkts; /*!< counter of ingress packets */
|
||||
__u32 ifOutUcastPkts; /*!< counter of egress packets */
|
||||
__u32 ifInErrors; /*!< counter of error ingress packets */
|
||||
__u32 ifInDiscards; /*!< counter of dropped ingress packets */
|
||||
__u32 ifOutErros; /*!< counter of error egress packets */
|
||||
__u32 ifOutDiscards; /*!< counter of dropped egress packets */
|
||||
} atm_aal5_ifEntry_t;
|
||||
|
||||
typedef struct {
|
||||
__u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
|
||||
__u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
|
||||
__u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
|
||||
} atm_aal5_vcc_t;
|
||||
|
||||
typedef struct {
|
||||
int vpi; /*!< VPI of the VCC to get MIB counters */
|
||||
int vci; /*!< VCI of the VCC to get MIB counters */
|
||||
atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
|
||||
} atm_aal5_vcc_x_t;
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* IOCTL
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
\addtogroup IFX_ATM_IOCTL
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/*
|
||||
* ioctl Command
|
||||
*/
|
||||
/*!
|
||||
\brief ATM IOCTL Magic Number
|
||||
*/
|
||||
#define PPE_ATM_IOC_MAGIC 'o'
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get Cell Level MIB Counters
|
||||
|
||||
This command is obsolete. User can get cell level MIB from DSL API.
|
||||
This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get AAL5 Level MIB Counters
|
||||
|
||||
Get AAL5 packet counters.
|
||||
This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get Per PVC MIB Counters
|
||||
|
||||
Get AAL5 packet counters for each PVC.
|
||||
This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
|
||||
/*!
|
||||
\brief Total Number of ATM IOCTL Commands
|
||||
*/
|
||||
#define PPE_ATM_IOC_MAXNR 3
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* API
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
#ifdef __KERNEL__
|
||||
struct port_cell_info {
|
||||
unsigned int port_num;
|
||||
unsigned int tx_link_rate[2];
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif // IFX_ATM_H
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,326 +0,0 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_danube.c
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM
|
||||
**
|
||||
** DATE : 7 Jul 2009
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM driver common source file (core functions)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 07 JUL 2009 Xu Liang Init Version
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Head File
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* Common Head File
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioctl.h>
|
||||
#include <linux/clk.h>
|
||||
#include <asm/delay.h>
|
||||
|
||||
/*
|
||||
* Chip Specific Head File
|
||||
*/
|
||||
#include <lantiq_soc.h>
|
||||
#include "ifxmips_compat.h"
|
||||
#include "ifxmips_atm_core.h"
|
||||
#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
|
||||
#include "ifxmips_atm_fw_danube_retx.h"
|
||||
#else
|
||||
#include "ifxmips_atm_fw_danube.h"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Definition
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* EMA Settings
|
||||
*/
|
||||
#define EMA_CMD_BUF_LEN 0x0040
|
||||
#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
|
||||
#define EMA_DATA_BUF_LEN 0x0100
|
||||
#define EMA_DATA_BASE_ADDR (0x00001900 << 2)
|
||||
#define EMA_WRITE_BURST 0x2
|
||||
#define EMA_READ_BURST 0x2
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Declaration
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* Hardware Init/Uninit Functions
|
||||
*/
|
||||
static inline void init_pmu(void);
|
||||
static inline void uninit_pmu(void);
|
||||
static inline void reset_ppe(void);
|
||||
static inline void init_ema(void);
|
||||
static inline void init_mailbox(void);
|
||||
static inline void init_atm_tc(void);
|
||||
static inline void clear_share_buffer(void);
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Local Variable
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Local Function
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
static inline void init_pmu(void)
|
||||
{
|
||||
//*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
|
||||
//PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
/* PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
|
||||
struct clk *clk = clk_get_sys("ltq_dsl", NULL);
|
||||
clk_enable(clk);
|
||||
}
|
||||
|
||||
static inline void uninit_pmu(void)
|
||||
{
|
||||
/* PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);*/
|
||||
//PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
struct clk *clk = clk_get_sys("ltq_dsl", NULL);
|
||||
clk_disable(clk);
|
||||
}
|
||||
|
||||
static inline void reset_ppe(void)
|
||||
{
|
||||
#if 0 //def MODULE
|
||||
unsigned int etop_cfg;
|
||||
unsigned int etop_mdio_cfg;
|
||||
unsigned int etop_ig_plen_ctrl;
|
||||
unsigned int enet_mac_cfg;
|
||||
|
||||
etop_cfg = *IFX_PP32_ETOP_CFG;
|
||||
etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
|
||||
etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
|
||||
enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
|
||||
|
||||
*IFX_PP32_ETOP_CFG &= ~0x03C0;
|
||||
|
||||
// reset PPE
|
||||
ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
|
||||
|
||||
*IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
|
||||
*IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
|
||||
*IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
|
||||
*IFX_PP32_ETOP_CFG = etop_cfg;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void init_ema(void)
|
||||
{
|
||||
IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
|
||||
IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
|
||||
IFX_REG_W32(0x000000FF, EMA_IER);
|
||||
IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
|
||||
}
|
||||
|
||||
static inline void init_mailbox(void)
|
||||
{
|
||||
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
|
||||
IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
|
||||
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
|
||||
IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
|
||||
}
|
||||
|
||||
static inline void init_atm_tc(void)
|
||||
{
|
||||
IFX_REG_W32(0x0000, DREG_AT_CTRL);
|
||||
IFX_REG_W32(0x0000, DREG_AR_CTRL);
|
||||
IFX_REG_W32(0x0, DREG_AT_IDLE0);
|
||||
IFX_REG_W32(0x0, DREG_AT_IDLE1);
|
||||
IFX_REG_W32(0x0, DREG_AR_IDLE0);
|
||||
IFX_REG_W32(0x0, DREG_AR_IDLE1);
|
||||
IFX_REG_W32(0x40, RFBI_CFG);
|
||||
IFX_REG_W32(0x1600, SFSM_DBA0);
|
||||
IFX_REG_W32(0x1718, SFSM_DBA1);
|
||||
IFX_REG_W32(0x1830, SFSM_CBA0);
|
||||
IFX_REG_W32(0x1844, SFSM_CBA1);
|
||||
IFX_REG_W32(0x14014, SFSM_CFG0);
|
||||
IFX_REG_W32(0x14014, SFSM_CFG1);
|
||||
IFX_REG_W32(0x1858, FFSM_DBA0);
|
||||
IFX_REG_W32(0x18AC, FFSM_DBA1);
|
||||
IFX_REG_W32(0x10006, FFSM_CFG0);
|
||||
IFX_REG_W32(0x10006, FFSM_CFG1);
|
||||
IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
|
||||
IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
|
||||
}
|
||||
|
||||
static inline void clear_share_buffer(void)
|
||||
{
|
||||
volatile u32 *p = SB_RAM0_ADDR(0);
|
||||
unsigned int i;
|
||||
|
||||
for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
|
||||
IFX_REG_W32(0, p++);
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Download PPE firmware binary code.
|
||||
* Input:
|
||||
* src --- u32 *, binary code buffer
|
||||
* dword_len --- unsigned int, binary code length in DWORD (32-bit)
|
||||
* Output:
|
||||
* int --- IFX_SUCCESS: Success
|
||||
* else: Error Code
|
||||
*/
|
||||
static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
|
||||
{
|
||||
volatile u32 *dest;
|
||||
|
||||
if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
|
||||
|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
|
||||
return IFX_ERROR;
|
||||
|
||||
if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
|
||||
IFX_REG_W32(0x00, CDM_CFG);
|
||||
else
|
||||
IFX_REG_W32(0x04, CDM_CFG);
|
||||
|
||||
/* copy code */
|
||||
dest = CDM_CODE_MEMORY(0, 0);
|
||||
while ( code_dword_len-- > 0 )
|
||||
IFX_REG_W32(*code_src++, dest++);
|
||||
|
||||
/* copy data */
|
||||
dest = CDM_DATA_MEMORY(0, 0);
|
||||
while ( data_dword_len-- > 0 )
|
||||
IFX_REG_W32(*data_src++, dest++);
|
||||
|
||||
return IFX_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Global Function
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
|
||||
{
|
||||
ASSERT(major != NULL, "pointer is NULL");
|
||||
ASSERT(minor != NULL, "pointer is NULL");
|
||||
|
||||
#if (defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX) || defined(VER_IN_FIRMWARE)
|
||||
*major = FW_VER_ID->major;
|
||||
*minor = FW_VER_ID->minor;
|
||||
#else
|
||||
*major = ATM_FW_VER_MAJOR;
|
||||
*minor = ATM_FW_VER_MINOR;
|
||||
#endif
|
||||
}
|
||||
|
||||
void ifx_atm_init_chip(void)
|
||||
{
|
||||
init_pmu();
|
||||
|
||||
reset_ppe();
|
||||
|
||||
init_ema();
|
||||
|
||||
init_mailbox();
|
||||
|
||||
init_atm_tc();
|
||||
|
||||
clear_share_buffer();
|
||||
}
|
||||
|
||||
void ifx_atm_uninit_chip(void)
|
||||
{
|
||||
uninit_pmu();
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Initialize and start up PP32.
|
||||
* Input:
|
||||
* none
|
||||
* Output:
|
||||
* int --- IFX_SUCCESS: Success
|
||||
* else: Error Code
|
||||
*/
|
||||
int ifx_pp32_start(int pp32)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* download firmware */
|
||||
ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
|
||||
if ( ret != IFX_SUCCESS )
|
||||
return ret;
|
||||
|
||||
/* run PP32 */
|
||||
IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
|
||||
|
||||
/* idle for a while to let PP32 init itself */
|
||||
udelay(10);
|
||||
|
||||
return IFX_SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Halt PP32.
|
||||
* Input:
|
||||
* none
|
||||
* Output:
|
||||
* none
|
||||
*/
|
||||
void ifx_pp32_stop(int pp32)
|
||||
{
|
||||
/* halt PP32 */
|
||||
IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,178 +0,0 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_fw_regs_danube.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM (ADSL)
|
||||
**
|
||||
** DATE : 1 AUG 2005
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM Driver (Firmware Registers)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 4 AUG 2005 Xu Liang Initiate Version
|
||||
** 23 OCT 2006 Xu Liang Add GPL header.
|
||||
** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
#ifndef IFXMIPS_ATM_FW_REGS_DANUBE_H
|
||||
#define IFXMIPS_ATM_FW_REGS_DANUBE_H
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Host-PPE Communication Data Address Mapping
|
||||
*/
|
||||
#define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2001))
|
||||
#define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */
|
||||
#define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */
|
||||
#define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */
|
||||
#define WRX_DMACH_ON SB_BUFFER(0x2405) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */
|
||||
#define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */
|
||||
#define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */
|
||||
#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20))
|
||||
#define WRX_QUEUE_CONTEXT(i) ((struct wrx_queue_context*) SB_BUFFER(0x2504 + (i) * 20))
|
||||
#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7))
|
||||
#define WRX_DESC_CONTEXT(i) ((struct wrx_desc_context*) SB_BUFFER(0x2643 + (i) * 7))
|
||||
#define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i)))
|
||||
#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x2710 + (i) * 27))
|
||||
#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x2711 + (i) * 27))
|
||||
#define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410))
|
||||
#if !defined(ENABLE_ATM_RETX) || !ENABLE_ATM_RETX
|
||||
#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2000 + (i)))
|
||||
#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2020 + (i)))
|
||||
#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2040 + (i)))
|
||||
#else
|
||||
#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2020 + (i)))
|
||||
#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2040 + (i)))
|
||||
#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2060 + (i)))
|
||||
#endif
|
||||
|
||||
#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
|
||||
|
||||
#define RETX_MODE_CFG ((volatile struct Retx_mode_cfg *) SB_BUFFER(0x2408))
|
||||
#define RETX_TSYNC_CFG ((volatile struct Retx_Tsync_cfg *) SB_BUFFER(0x2409))
|
||||
#define RETX_TD_CFG ((volatile struct Retx_Td_cfg *) SB_BUFFER(0x240A))
|
||||
#define RETX_MIB_TIMER_CFG ((volatile struct Retx_MIB_Timer_cfg *) SB_BUFFER(0x240B))
|
||||
#define RETX_PLAYOUT_BUFFER_BASE SB_BUFFER(0x240D)
|
||||
#define RETX_SERVICE_HEADER_CFG SB_BUFFER(0x240E)
|
||||
#define RETX_MASK_HEADER_CFG SB_BUFFER(0x240F)
|
||||
|
||||
#define RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) PPE_REG_ADDR(0x0D78))
|
||||
#define BAD_REC_RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AC))
|
||||
#define FIRST_BAD_REC_RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AE))
|
||||
|
||||
#define PB_BUFFER_USAGE SB_BUFFER(0x2100)
|
||||
#define DTU_STAT_INFO ((volatile struct DTU_stat_info *) SB_BUFFER(0x2180))
|
||||
#define DTU_VLD_STAT SB_BUFFER(0x2380)
|
||||
|
||||
|
||||
//=====================================================================
|
||||
// retx firmware mib, for debug purpose
|
||||
// address : 0x2388 - 0x238F
|
||||
// size : 8
|
||||
//=====================================================================
|
||||
#define URETX_RX_TOTAL_DTU SB_BUFFER(0x2388)
|
||||
#define URETX_RX_BAD_DTU SB_BUFFER(0x2389)
|
||||
#define URETX_RX_GOOD_DTU SB_BUFFER(0x238A)
|
||||
#define URETX_RX_CORRECTED_DTU SB_BUFFER(0x238B)
|
||||
#define URETX_RX_OUTOFDATE_DTU SB_BUFFER(0x238C)
|
||||
#define URETX_RX_DUPLICATE_DTU SB_BUFFER(0x238D)
|
||||
#define URETX_RX_TIMEOUT_DTU SB_BUFFER(0x238E)
|
||||
|
||||
#define URETX_ALPHA_SWITCH_TO_HUNT_TIMES SB_BUFFER(0x238F)
|
||||
|
||||
// cell counter for debug purpose
|
||||
#define WRX_BC0_CELL_NUM SB_BUFFER(0x23E0)
|
||||
#define WRX_BC0_DROP_CELL_NUM SB_BUFFER(0x23E1)
|
||||
#define WRX_BC0_NONRETX_CELL_NUM SB_BUFFER(0x23E2)
|
||||
#define WRX_BC0_RETX_CELL_NUM SB_BUFFER(0x23E3)
|
||||
#define WRX_BC0_OUTOFDATE_CELL_NUM SB_BUFFER(0x23E4)
|
||||
#define WRX_BC0_DIRECTUP_NUM SB_BUFFER(0x23E5)
|
||||
#define WRX_BC0_PBW_TOTAL_NUM SB_BUFFER(0x23E6)
|
||||
#define WRX_BC0_PBW_SUCC_NUM SB_BUFFER(0x23E7)
|
||||
#define WRX_BC0_PBW_FAIL_NUM SB_BUFFER(0x23E8)
|
||||
#define WRX_BC1_CELL_NUM SB_BUFFER(0x23E9)
|
||||
|
||||
// debug info (interface)
|
||||
|
||||
#define DBG_DTU_INTF_WRPTR SB_BUFFER(0x2390)
|
||||
#define DBG_INTF_FCW_DUP_CNT SB_BUFFER(0x2391)
|
||||
#define DBG_INTF_SID_CHANGE_IN_DTU_CNT SB_BUFFER(0x2392)
|
||||
#define DBG_INTF_LCW_DUP_CNT SB_BUFFER(0x2393)
|
||||
|
||||
#define DBG_RFBI_DONE_INT_CNT SB_BUFFER(0x2394)
|
||||
#define DBG_DREG_BEG_END SB_BUFFER(0x2395)
|
||||
#define DBG_RFBI_BC0_INVALID_CNT SB_BUFFER(0x2396)
|
||||
#define DBG_RFBI_LAST_T SB_BUFFER(0x2397)
|
||||
|
||||
#define DBG_RFBI_INTV0 SB_BUFFER(0x23EE)
|
||||
#define DBG_RFBI_INTV1 SB_BUFFER(0x23EF)
|
||||
|
||||
#define DBG_INTF_INFO(i) ((volatile struct Retx_adsl_ppe_intf_rec *) SB_BUFFER(0x23F0 + i))
|
||||
|
||||
// Internal status
|
||||
#define URetx_curr_time SB_BUFFER(0x2398)
|
||||
#define URetx_sec_counter SB_BUFFER(0x2399)
|
||||
#define RxCURR_EFB SB_BUFFER(0x239A)
|
||||
#define RxDTURetransmittedCNT SB_BUFFER(0x239B)
|
||||
|
||||
//=====================================================================
|
||||
// standardized MIB counter
|
||||
// address : 0x239C - 0x239F
|
||||
// size : 4
|
||||
//=====================================================================
|
||||
#define RxLastEFBCNT SB_BUFFER(0x239C)
|
||||
#define RxDTUCorrectedCNT SB_BUFFER(0x239D)
|
||||
#define RxDTUCorruptedCNT SB_BUFFER(0x239E)
|
||||
#define RxRetxDTUUncorrectedCNT SB_BUFFER(0x239F)
|
||||
|
||||
|
||||
//=====================================================================
|
||||
// General URetx Context
|
||||
// address : 0x23A0 - 0x23AF
|
||||
// size : 16
|
||||
//=====================================================================
|
||||
#define NEXT_DTU_SID_OUT SB_BUFFER(0x23A0)
|
||||
#define LAST_DTU_SID_IN SB_BUFFER(0x23A1)
|
||||
#define NEXT_CELL_SID_OUT SB_BUFFER(0x23A2)
|
||||
#define ISR_CELL_ID SB_BUFFER(0x23A3)
|
||||
#define PB_CELL_SEARCH_IDX SB_BUFFER(0x23A4)
|
||||
#define PB_READ_PEND_FLAG SB_BUFFER(0x23A5)
|
||||
#define RFBI_FIRST_CW SB_BUFFER(0x23A6)
|
||||
#define RFBI_BAD_CW SB_BUFFER(0x23A7)
|
||||
#define RFBI_INVALID_CW SB_BUFFER(0x23A8)
|
||||
#define RFBI_RETX_CW SB_BUFFER(0x23A9)
|
||||
#define RFBI_CHK_DTU_STATUS SB_BUFFER(0x23AA)
|
||||
|
||||
//=====================================================================
|
||||
// per PVC counter for RX error_pdu and correct_pdu
|
||||
// address : 0x23B0 - 0x23CF
|
||||
// size : 32
|
||||
//=====================================================================
|
||||
#define WRX_PER_PVC_CORRECT_PDU_BASE SB_BUFFER(0x23B0)
|
||||
#define WRX_PER_PVC_ERROR_PDU_BASE SB_BUFFER(0x23C0)
|
||||
|
||||
#define __WRXCTXT_L2_RdPtr(i) SB_BUFFER(0x2422 + (i))
|
||||
#define __WRXCTXT_L2Pages(i) SB_BUFFER(0x2424 + (i))
|
||||
|
||||
#define __WTXCTXT_TC_WRPTR(i) SB_BUFFER(0x2450 + (i))
|
||||
#define __WRXCTXT_PortState(i) SB_BUFFER(0x242A + (i))
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif // IFXMIPS_ATM_FW_REGS_DANUBE_H
|
||||
@ -1,59 +0,0 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_fw_regs_vr9.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM (ADSL)
|
||||
**
|
||||
** DATE : 1 AUG 2005
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM Driver (Firmware Registers)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 4 AUG 2005 Xu Liang Initiate Version
|
||||
** 23 OCT 2006 Xu Liang Add GPL header.
|
||||
** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
#ifndef IFXMIPS_ATM_FW_REGS_VR9_H
|
||||
#define IFXMIPS_ATM_FW_REGS_VR9_H
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Host-PPE Communication Data Address Mapping
|
||||
*/
|
||||
#define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2001))
|
||||
#define CFG_WRX_HTUTS SB_BUFFER(0x2010) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRX_QNUM SB_BUFFER(0x2011) /* WAN RX Queue Number */
|
||||
#define CFG_WRX_DCHNUM SB_BUFFER(0x2012) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */
|
||||
#define CFG_WTX_DCHNUM SB_BUFFER(0x2013) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRDES_DELAY SB_BUFFER(0x2014) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */
|
||||
#define WRX_DMACH_ON SB_BUFFER(0x2015) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */
|
||||
#define WTX_DMACH_ON SB_BUFFER(0x2016) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */
|
||||
#define WRX_HUNT_BITTH SB_BUFFER(0x2017) /* WAN RX HUNT Threshold, must be between 2 to 8. */
|
||||
#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x4C00 + (i) * 20)) /* i < 16 */
|
||||
#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x4F80 + (i) * 7)) /* i < 8 */
|
||||
#define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x4FB8 + (i))) /* i < 2 */
|
||||
#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x3A00 + (i) * 27)) /* i < 16 */
|
||||
#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x3A01 + (i) * 27)) /* i < 16 */
|
||||
#define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x4EF0))
|
||||
#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x26A0 + (i))) /* i < 32 */
|
||||
#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x26C0 + (i))) /* i < 32 */
|
||||
#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x26E0 + (i))) /* i < 32 */
|
||||
|
||||
#define UTP_CFG SB_BUFFER(0x2018) // bit 0~3 - 0x0F: in showtime, 0x00: not in showtime
|
||||
|
||||
|
||||
|
||||
#endif // IFXMIPS_ATM_FW_REGS_VR9_H
|
||||
@ -1,303 +0,0 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_vr9.c
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM
|
||||
**
|
||||
** DATE : 7 Jul 2009
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM driver common source file (core functions)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 07 JUL 2009 Xu Liang Init Version
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Head File
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* Common Head File
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioctl.h>
|
||||
#include <asm/delay.h>
|
||||
|
||||
/*
|
||||
* Chip Specific Head File
|
||||
*/
|
||||
#include <ifx_types.h>
|
||||
#include <ifx_regs.h>
|
||||
#include <common_routines.h>
|
||||
#include <ifx_pmu.h>
|
||||
#include <ifx_rcu.h>
|
||||
#include "ifxmips_atm_core.h"
|
||||
#include "ifxmips_atm_fw_vr9.h"
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Definition
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Declaration
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* Hardware Init/Uninit Functions
|
||||
*/
|
||||
static inline void init_pmu(void);
|
||||
static inline void uninit_pmu(void);
|
||||
static inline void reset_ppe(void);
|
||||
static inline void init_pdma(void);
|
||||
static inline void init_mailbox(void);
|
||||
static inline void init_atm_tc(void);
|
||||
static inline void clear_share_buffer(void);
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Local Variable
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Local Function
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
static inline void init_pmu(void)
|
||||
{
|
||||
//*PMU_PWDCR &= ~((1 << 29) | (1 << 22) | (1 << 21) | (1 << 19) | (1 << 18));
|
||||
//PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
}
|
||||
|
||||
static inline void uninit_pmu(void)
|
||||
{
|
||||
PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
//PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
}
|
||||
|
||||
static inline void reset_ppe(void)
|
||||
{
|
||||
#ifdef MODULE
|
||||
// reset PPE
|
||||
ifx_rcu_rst(IFX_RCU_DOMAIN_DSLDFE, IFX_RCU_MODULE_ATM);
|
||||
udelay(1000);
|
||||
ifx_rcu_rst(IFX_RCU_DOMAIN_DSLTC, IFX_RCU_MODULE_ATM);
|
||||
udelay(1000);
|
||||
ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
|
||||
udelay(1000);
|
||||
*PP32_SRST &= ~0x000303CF;
|
||||
udelay(1000);
|
||||
*PP32_SRST |= 0x000303CF;
|
||||
udelay(1000);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void init_pdma(void)
|
||||
{
|
||||
IFX_REG_W32(0x08, PDMA_CFG);
|
||||
IFX_REG_W32(0x00203580, SAR_PDMA_RX_CMDBUF_CFG);
|
||||
IFX_REG_W32(0x004035A0, SAR_PDMA_RX_FW_CMDBUF_CFG);
|
||||
}
|
||||
|
||||
static inline void init_mailbox(void)
|
||||
{
|
||||
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
|
||||
IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
|
||||
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
|
||||
IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
|
||||
}
|
||||
|
||||
static inline void init_atm_tc(void)
|
||||
{
|
||||
/* clear sync state */
|
||||
*SFSM_STATE0 = 0;
|
||||
*SFSM_STATE1 = 0;
|
||||
|
||||
/* enable keep IDLE */
|
||||
// *SFSM_CFG0 |= 1 << 15;
|
||||
// *SFSM_CFG1 |= 1 << 15;
|
||||
}
|
||||
|
||||
static inline void clear_share_buffer(void)
|
||||
{
|
||||
volatile u32 *p;
|
||||
unsigned int i;
|
||||
|
||||
p = SB_RAM0_ADDR(0);
|
||||
for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
|
||||
IFX_REG_W32(0, p++);
|
||||
|
||||
p = SB_RAM6_ADDR(0);
|
||||
for ( i = 0; i < SB_RAM6_DWLEN; i++ )
|
||||
IFX_REG_W32(0, p++);
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Download PPE firmware binary code.
|
||||
* Input:
|
||||
* pp32 --- int, which pp32 core
|
||||
* src --- u32 *, binary code buffer
|
||||
* dword_len --- unsigned int, binary code length in DWORD (32-bit)
|
||||
* Output:
|
||||
* int --- IFX_SUCCESS: Success
|
||||
* else: Error Code
|
||||
*/
|
||||
static inline int pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
|
||||
{
|
||||
unsigned int clr, set;
|
||||
volatile u32 *dest;
|
||||
|
||||
if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
|
||||
|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
|
||||
return IFX_ERROR;
|
||||
|
||||
clr = pp32 ? 0xF0 : 0x0F;
|
||||
if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
|
||||
set = pp32 ? (3 << 6): (2 << 2);
|
||||
else
|
||||
set = 0x00;
|
||||
IFX_REG_W32_MASK(clr, set, CDM_CFG);
|
||||
|
||||
/* copy code */
|
||||
dest = CDM_CODE_MEMORY(pp32, 0);
|
||||
while ( code_dword_len-- > 0 )
|
||||
IFX_REG_W32(*code_src++, dest++);
|
||||
|
||||
/* copy data */
|
||||
dest = CDM_DATA_MEMORY(pp32, 0);
|
||||
while ( data_dword_len-- > 0 )
|
||||
IFX_REG_W32(*data_src++, dest++);
|
||||
|
||||
return IFX_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Global Function
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
|
||||
{
|
||||
ASSERT(major != NULL, "pointer is NULL");
|
||||
ASSERT(minor != NULL, "pointer is NULL");
|
||||
|
||||
#ifdef VER_IN_FIRMWARE
|
||||
*major = FW_VER_ID->major;
|
||||
*minor = FW_VER_ID->minor;
|
||||
#else
|
||||
*major = ATM_FW_VER_MAJOR;
|
||||
*minor = ATM_FW_VER_MINOR;
|
||||
#endif
|
||||
}
|
||||
|
||||
void ifx_atm_init_chip(void)
|
||||
{
|
||||
init_pmu();
|
||||
|
||||
reset_ppe();
|
||||
|
||||
init_pdma();
|
||||
|
||||
init_mailbox();
|
||||
|
||||
init_atm_tc();
|
||||
|
||||
clear_share_buffer();
|
||||
}
|
||||
|
||||
void ifx_atm_uninit_chip(void)
|
||||
{
|
||||
uninit_pmu();
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Initialize and start up PP32.
|
||||
* Input:
|
||||
* none
|
||||
* Output:
|
||||
* int --- IFX_SUCCESS: Success
|
||||
* else: Error Code
|
||||
*/
|
||||
int ifx_pp32_start(int pp32)
|
||||
{
|
||||
unsigned int mask = 1 << (pp32 << 4);
|
||||
int ret;
|
||||
|
||||
/* download firmware */
|
||||
ret = pp32_download_code(pp32, firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
|
||||
if ( ret != IFX_SUCCESS )
|
||||
return ret;
|
||||
|
||||
/* run PP32 */
|
||||
IFX_REG_W32_MASK(mask, 0, PP32_FREEZE);
|
||||
|
||||
/* idle for a while to let PP32 init itself */
|
||||
udelay(10);
|
||||
|
||||
return IFX_SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Halt PP32.
|
||||
* Input:
|
||||
* none
|
||||
* Output:
|
||||
* none
|
||||
*/
|
||||
void ifx_pp32_stop(int pp32)
|
||||
{
|
||||
unsigned int mask = 1 << (pp32 << 4);
|
||||
|
||||
/* halt PP32 */
|
||||
IFX_REG_W32_MASK(0, mask, PP32_FREEZE);
|
||||
}
|
||||
@ -1,56 +0,0 @@
|
||||
#ifndef _IFXMIPS_COMPAT_H__
|
||||
#define _IFXMIPS_COMPAT_H__
|
||||
|
||||
#define IFX_SUCCESS 0
|
||||
#define IFX_ERROR (-1)
|
||||
|
||||
#define ATM_VBR_NRT ATM_VBR
|
||||
#define ATM_VBR_RT 6
|
||||
#define ATM_UBR_PLUS 7
|
||||
#define ATM_GFR 8
|
||||
|
||||
#define NUM_ENTITY(x) (sizeof(x) / sizeof(*(x)))
|
||||
|
||||
#define SET_BITS(x, msb, lsb, value) \
|
||||
(((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
|
||||
|
||||
|
||||
#define IFX_PP32_ETOP_CFG 0x16020
|
||||
#define IFX_PP32_ETOP_MDIO_CFG 0x11804
|
||||
#define IFX_PP32_ETOP_IG_PLEN_CTRL 0x16080
|
||||
#define IFX_PP32_ENET_MAC_CFG 0x1840
|
||||
|
||||
#define IFX_RCU_DOMAIN_PPE (1 << 8)
|
||||
#define IFX_RCU_MODULE_ATM
|
||||
|
||||
#define IFX_PMU_ENABLE 1
|
||||
#define IFX_PMU_DISABLE 0
|
||||
|
||||
#define IFX_PMU_MODULE_DSL_DFE (1 << 9)
|
||||
#define IFX_PMU_MODULE_AHBS (1 << 13)
|
||||
#define IFX_PMU_MODULE_PPE_QSB (1 << 18)
|
||||
#define IFX_PMU_MODULE_PPE_SLL01 (1 << 19)
|
||||
#define IFX_PMU_MODULE_PPE_TC (1 << 21)
|
||||
#define IFX_PMU_MODULE_PPE_EMA (1 << 22)
|
||||
#define IFX_PMU_MODULE_PPE_TOP (1 << 29)
|
||||
|
||||
extern void ltq_pmu_enable(unsigned int module);
|
||||
extern void ltq_pmu_disable(unsigned int module);
|
||||
|
||||
#define ifx_pmu_set(a,b) {if(a == IFX_PMU_ENABLE) ltq_pmu_enable(b); else ltq_pmu_disable(b);}
|
||||
|
||||
#define PPE_TOP_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x))
|
||||
#define PPE_SLL01_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_SLL01, (__x))
|
||||
#define PPE_TC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TC, (__x))
|
||||
#define PPE_EMA_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_EMA, (__x))
|
||||
#define PPE_QSB_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_QSB, (__x))
|
||||
#define PPE_TPE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHBS, (__x))
|
||||
#define DSL_DFE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DSL_DFE, (__x))
|
||||
|
||||
#define IFX_REG_W32(_v, _r) __raw_writel((_v), (_r))
|
||||
|
||||
#define CONFIG_IFXMIPS_DSL_CPE_MEI y
|
||||
|
||||
#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user