mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 03:13:20 +02:00
finally fix the v1 hardware bug :)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@1346 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
7cfb11cbe6
commit
ae8a1e654c
@ -1,6 +1,6 @@
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diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
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--- linux.old/arch/mips/kernel/entry.S 2005-06-26 16:27:01.000000000 +0200
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+++ linux.dev/arch/mips/kernel/entry.S 2005-06-29 20:24:54.000000000 +0200
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--- linux.old/arch/mips/kernel/entry.S 2005-07-04 23:39:26.000000000 +0200
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+++ linux.dev/arch/mips/kernel/entry.S 2005-07-05 14:33:14.000000000 +0200
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@@ -100,6 +100,10 @@
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* and R4400 SC and MC versions.
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*/
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@ -13,8 +13,8 @@ diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
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mfc0 k0, CP0_INDEX
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#endif
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diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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--- linux.old/arch/mips/mm/c-r4k.c 2005-06-26 16:27:01.000000000 +0200
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+++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-30 22:24:29.000000000 +0200
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--- linux.old/arch/mips/mm/c-r4k.c 2005-07-04 23:39:26.000000000 +0200
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+++ linux.dev/arch/mips/mm/c-r4k.c 2005-07-05 15:11:49.000000000 +0200
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@@ -14,6 +14,12 @@
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#include <linux/mm.h>
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#include <linux/bitops.h>
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@ -36,7 +36,42 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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struct bcache_ops *bcops = &no_sc_ops;
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#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
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@@ -266,6 +273,7 @@
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@@ -64,8 +71,10 @@
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static inline void r4k_blast_dcache_page_setup(void)
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{
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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-
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- if (dc_lsize == 16)
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+
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+ if (bcm4710)
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+ r4k_blast_dcache_page = blast_dcache_page;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache_page = blast_dcache16_page;
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else if (dc_lsize == 32)
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r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
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@@ -77,7 +86,9 @@
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{
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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- if (dc_lsize == 16)
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+ if (bcm4710)
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+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
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else if (dc_lsize == 32)
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r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
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@@ -89,7 +100,9 @@
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{
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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- if (dc_lsize == 16)
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+ if (bcm4710)
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+ r4k_blast_dcache = blast_dcache;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache = blast_dcache16;
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else if (dc_lsize == 32)
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r4k_blast_dcache = blast_dcache32;
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@@ -266,6 +279,7 @@
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r4k_blast_dcache();
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r4k_blast_icache();
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@ -44,7 +79,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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switch (current_cpu_data.cputype) {
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case CPU_R4000SC:
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case CPU_R4000MC:
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@@ -304,10 +312,10 @@
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@@ -304,10 +318,10 @@
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* Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
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* only flush the primary caches but R10000 and R12000 behave sane ...
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*/
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@ -57,7 +92,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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r4k_blast_scache();
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}
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@@ -383,12 +391,15 @@
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@@ -383,12 +397,15 @@
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unsigned long ic_lsize = current_cpu_data.icache.linesz;
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unsigned long addr, aend;
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@ -75,7 +110,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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while (1) {
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/* Hit_Writeback_Inv_D */
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@@ -403,8 +414,6 @@
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@@ -403,8 +420,6 @@
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if (end - start > icache_size)
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r4k_blast_icache();
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else {
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@ -84,7 +119,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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while (1) {
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/* Hit_Invalidate_I */
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protected_flush_icache_line(addr);
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@@ -443,7 +452,8 @@
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@@ -443,7 +458,8 @@
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if (cpu_has_subset_pcaches) {
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unsigned long addr = (unsigned long) page_address(page);
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@ -94,7 +129,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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ClearPageDcacheDirty(page);
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return;
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@@ -451,6 +461,7 @@
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@@ -451,6 +467,7 @@
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if (!cpu_has_ic_fills_f_dc) {
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unsigned long addr = (unsigned long) page_address(page);
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@ -102,7 +137,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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r4k_blast_dcache_page(addr);
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ClearPageDcacheDirty(page);
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}
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@@ -477,7 +488,7 @@
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@@ -477,7 +494,7 @@
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/* Catch bad driver code */
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BUG_ON(size == 0);
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@ -111,7 +146,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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unsigned long sc_lsize = current_cpu_data.scache.linesz;
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if (size >= scache_size) {
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@@ -509,6 +520,8 @@
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@@ -509,6 +526,8 @@
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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@ -120,7 +155,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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@@ -527,7 +540,7 @@
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@@ -527,7 +546,7 @@
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/* Catch bad driver code */
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BUG_ON(size == 0);
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@ -129,7 +164,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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unsigned long sc_lsize = current_cpu_data.scache.linesz;
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if (size >= scache_size) {
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@@ -554,6 +567,8 @@
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@@ -554,6 +573,8 @@
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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@ -138,7 +173,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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@@ -577,6 +592,8 @@
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@@ -577,6 +598,8 @@
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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R4600_HIT_CACHEOP_WAR_IMPL;
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@ -147,7 +182,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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protected_flush_icache_line(addr & ~(ic_lsize - 1));
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if (MIPS4K_ICACHE_REFILL_WAR) {
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@@ -986,10 +1003,12 @@
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@@ -986,10 +1009,12 @@
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case CPU_R4000MC:
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case CPU_R4400SC:
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case CPU_R4400MC:
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@ -164,7 +199,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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break;
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case CPU_R10000:
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@@ -1041,6 +1060,19 @@
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@@ -1041,6 +1066,19 @@
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static inline void coherency_setup(void)
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{
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change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
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@ -184,7 +219,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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/*
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* c0_status.cu=0 specifies that updates by the sc instruction use
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@@ -1062,6 +1094,42 @@
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@@ -1062,6 +1100,42 @@
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}
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@ -227,7 +262,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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void __init ld_mmu_r4xx0(void)
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{
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extern void build_clear_page(void);
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@@ -1073,6 +1141,11 @@
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@@ -1073,6 +1147,11 @@
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memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
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memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80);
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@ -239,7 +274,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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probe_pcache();
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setup_scache();
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@@ -1117,47 +1190,9 @@
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@@ -1117,47 +1196,9 @@
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build_clear_page();
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build_copy_page();
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@ -290,8 +325,8 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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}
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diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c
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--- linux.old/arch/mips/mm/tlb-r4k.c 2005-06-26 16:24:26.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-06-29 20:29:16.000000000 +0200
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--- linux.old/arch/mips/mm/tlb-r4k.c 2005-07-04 23:39:26.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-07-05 14:33:14.000000000 +0200
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@@ -38,6 +38,7 @@
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old_ctx = read_c0_entryhi();
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write_c0_entrylo0(0);
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@ -349,8 +384,8 @@ diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c
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write_c0_entryhi(entryhi);
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write_c0_entrylo0(entrylo0);
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diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
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--- linux.old/arch/mips/mm/tlbex-mips32.S 2005-06-26 16:27:01.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-06-29 20:24:54.000000000 +0200
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--- linux.old/arch/mips/mm/tlbex-mips32.S 2005-07-04 23:39:26.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-07-05 14:33:14.000000000 +0200
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@@ -90,6 +90,9 @@
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.set noat
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LEAF(except_vec0_r4000)
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@ -362,8 +397,8 @@ diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mip
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mfc0 k1, CP0_CONTEXT
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la k0, pgd_current
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diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
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--- linux.old/include/asm-mips/r4kcache.h 2005-06-26 16:27:01.000000000 +0200
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+++ linux.dev/include/asm-mips/r4kcache.h 2005-06-30 22:39:42.000000000 +0200
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--- linux.old/include/asm-mips/r4kcache.h 2005-07-04 23:39:26.000000000 +0200
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+++ linux.dev/include/asm-mips/r4kcache.h 2005-07-05 15:13:56.000000000 +0200
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@@ -15,6 +15,18 @@
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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@ -407,41 +442,89 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca
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__asm__ __volatile__(
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".set noreorder\n\t"
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".set mips3\n"
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@@ -148,8 +163,10 @@
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@@ -138,6 +153,59 @@
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: "r" (base), \
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"i" (op));
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+#define cache_unroll(base,op) \
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+ __asm__ __volatile__(" \
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+ .set noreorder; \
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+ .set mips3; \
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+ cache %1, (%0); \
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+ .set mips0; \
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+ .set reorder" \
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+ : \
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+ : "r" (base), \
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+ "i" (op));
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+
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+
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+static inline void blast_dcache(void)
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+{
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+ unsigned long start = KSEG0;
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+ unsigned long end = start + current_cpu_data.dcache.waysize;
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+
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+ while(start < end) {
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+ BCM4710_DUMMY_RREG();
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+ cache_unroll(start,Index_Writeback_Inv_D);
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+ start += current_cpu_data.dcache.linesz;
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+ }
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+}
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+
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+static inline void blast_dcache_page(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = start + PAGE_SIZE;
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+
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+ BCM4710_FILL_TLB(start);
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+ do {
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+ BCM4710_DUMMY_RREG();
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+ cache_unroll(start,Hit_Writeback_Inv_D);
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+ start += current_cpu_data.dcache.linesz;
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+ } while (start < end);
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+}
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+
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+static inline void blast_dcache_page_indexed(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = start + PAGE_SIZE;
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+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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+ unsigned long ws_end = current_cpu_data.dcache.ways <<
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+ current_cpu_data.dcache.waybit;
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+ unsigned long ws, addr;
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+
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+ for (ws = 0; ws < ws_end; ws += ws_inc)
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+ for (addr = start; addr < end; addr += start += current_cpu_data.dcache.linesz) {
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+ BCM4710_DUMMY_RREG();
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+ cache_unroll(addr,Index_Writeback_Inv_D);
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+ }
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+}
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+
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static inline void blast_dcache16(void)
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{
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unsigned long start = KSEG0;
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@@ -148,8 +216,9 @@
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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- for (addr = start; addr < end; addr += 0x200)
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+ for (addr = start; addr < end; addr += 0x200) {
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+ BCM4710_DUMMY_RREG();
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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+ }
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}
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static inline void blast_dcache16_page(unsigned long page)
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@@ -157,7 +174,9 @@
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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+ BCM4710_FILL_TLB(start);
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do {
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+ BCM4710_DUMMY_RREG();
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cache16_unroll32(start,Hit_Writeback_Inv_D);
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start += 0x200;
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} while (start < end);
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@@ -173,8 +192,10 @@
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@@ -173,8 +242,9 @@
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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- for (addr = start; addr < end; addr += 0x200)
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+ for (addr = start; addr < end; addr += 0x200) {
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+ BCM4710_DUMMY_RREG();
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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+ }
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}
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static inline void blast_icache16(void)
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@@ -196,6 +217,7 @@
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@@ -196,6 +266,7 @@
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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@ -449,7 +532,7 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca
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do {
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cache16_unroll32(start,Hit_Invalidate_I);
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start += 0x200;
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@@ -281,6 +303,7 @@
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@@ -281,6 +352,7 @@
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: "r" (base), \
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"i" (op));
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@ -457,41 +540,29 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca
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static inline void blast_dcache32(void)
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{
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unsigned long start = KSEG0;
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@@ -291,8 +314,10 @@
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@@ -291,8 +363,9 @@
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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- for (addr = start; addr < end; addr += 0x400)
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+ for (addr = start; addr < end; addr += 0x400) {
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
|
||||
+ }
|
||||
}
|
||||
|
||||
static inline void blast_dcache32_page(unsigned long page)
|
||||
@@ -300,7 +325,9 @@
|
||||
unsigned long start = page;
|
||||
unsigned long end = start + PAGE_SIZE;
|
||||
|
||||
+ BCM4710_FILL_TLB(start);
|
||||
do {
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
cache32_unroll32(start,Hit_Writeback_Inv_D);
|
||||
start += 0x400;
|
||||
} while (start < end);
|
||||
@@ -316,8 +343,10 @@
|
||||
@@ -316,8 +389,9 @@
|
||||
unsigned long ws, addr;
|
||||
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
- for (addr = start; addr < end; addr += 0x400)
|
||||
+ for (addr = start; addr < end; addr += 0x400) {
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
|
||||
+ }
|
||||
}
|
||||
|
||||
static inline void blast_icache32(void)
|
||||
@@ -339,6 +368,7 @@
|
||||
@@ -339,6 +413,7 @@
|
||||
unsigned long start = page;
|
||||
unsigned long end = start + PAGE_SIZE;
|
||||
|
||||
@ -499,7 +570,7 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca
|
||||
do {
|
||||
cache32_unroll32(start,Hit_Invalidate_I);
|
||||
start += 0x400;
|
||||
@@ -443,6 +473,7 @@
|
||||
@@ -443,6 +518,7 @@
|
||||
unsigned long start = page;
|
||||
unsigned long end = start + PAGE_SIZE;
|
||||
|
||||
@ -508,8 +579,8 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca
|
||||
cache64_unroll32(start,Hit_Invalidate_I);
|
||||
start += 0x800;
|
||||
diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
|
||||
--- linux.old/include/asm-mips/stackframe.h 2005-06-26 16:27:01.000000000 +0200
|
||||
+++ linux.dev/include/asm-mips/stackframe.h 2005-06-30 19:04:46.000000000 +0200
|
||||
--- linux.old/include/asm-mips/stackframe.h 2005-07-04 23:39:26.000000000 +0200
|
||||
+++ linux.dev/include/asm-mips/stackframe.h 2005-07-05 14:33:14.000000000 +0200
|
||||
@@ -172,6 +172,46 @@
|
||||
rfe; \
|
||||
.set pop
|
||||
|
Loading…
Reference in New Issue
Block a user