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add some fixes for v1 hardware (doesn't work reliably yet)

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@1100 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd 2005-05-29 15:54:26 +00:00
parent 44e34b9a00
commit ba4a86fba5
2 changed files with 255 additions and 0 deletions
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108
target/linux/linux-2.4/patches/006-bcm47xx_workarounds.patch Normal file
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@ -0,0 +1,108 @@
diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
--- linux.old/arch/mips/mm/tlbex-mips32.S 2005-05-28 17:42:03.000000000 +0200
+++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-05-28 21:48:55.000000000 +0200
@@ -90,6 +90,9 @@
.set noat
LEAF(except_vec0_r4000)
.set mips3
+#ifdef CONFIG_BCM4704
+ nop
+#endif
#ifdef CONFIG_SMP
mfc0 k1, CP0_CONTEXT
la k0, pgd_current
diff -urN linux.old/arch/mips/mm/pg-r4k.c linux.dev/arch/mips/mm/pg-r4k.c
--- linux.old/arch/mips/mm/pg-r4k.c 2005-01-19 15:09:29.000000000 +0100
+++ linux.dev/arch/mips/mm/pg-r4k.c 2005-05-28 21:57:52.000000000 +0200
@@ -180,6 +180,7 @@
static inline void build_cdex_s(void)
{
+#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
union mips_instruction mi;
if ((store_offset & (cpu_scache_line_size() - 1)))
@@ -192,10 +193,12 @@
mi.c_format.simmediate = store_offset;
emit_instruction(mi);
+#endif
}
static inline void build_cdex_p(void)
{
+#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
union mips_instruction mi;
if (store_offset & (cpu_dcache_line_size() - 1))
@@ -218,6 +221,7 @@
mi.c_format.simmediate = store_offset;
emit_instruction(mi);
+#endif
}
static void __build_store_reg(int reg)
diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
--- linux.old/include/asm-mips/stackframe.h 2002-11-29 00:53:15.000000000 +0100
+++ linux.dev/include/asm-mips/stackframe.h 2005-05-28 21:53:03.000000000 +0200
@@ -172,6 +172,46 @@
rfe; \
.set pop
+#elif defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
+
+#define RESTORE_SOME \
+ .set push; \
+ .set reorder; \
+ mfc0 t0, CP0_STATUS; \
+ .set pop; \
+ ori t0, 0x1f; \
+ xori t0, 0x1f; \
+ mtc0 t0, CP0_STATUS; \
+ li v1, 0xff00; \
+ and t0, v1; \
+ lw v0, PT_STATUS(sp); \
+ nor v1, $0, v1; \
+ and v0, v1; \
+ or v0, t0; \
+ ori v1, v0, ST0_IE; \
+ xori v1, v1, ST0_IE; \
+ mtc0 v1, CP0_STATUS; \
+ mtc0 v0, CP0_STATUS; \
+ lw v1, PT_EPC(sp); \
+ mtc0 v1, CP0_EPC; \
+ lw $31, PT_R31(sp); \
+ lw $28, PT_R28(sp); \
+ lw $25, PT_R25(sp); \
+ lw $7, PT_R7(sp); \
+ lw $6, PT_R6(sp); \
+ lw $5, PT_R5(sp); \
+ lw $4, PT_R4(sp); \
+ lw $3, PT_R3(sp); \
+ lw $2, PT_R2(sp)
+
+#define RESTORE_SP_AND_RET \
+ lw sp, PT_R29(sp); \
+ nop; \
+ nop; \
+ .set mips3; \
+ eret; \
+ .set mips0
+
#else
#define RESTORE_SOME \
diff -urN linux.old/arch/mips/mm/tlbex-r4k.S linux.dev/arch/mips/mm/tlbex-r4k.S
--- linux.old/arch/mips/mm/tlbex-r4k.S 2005-05-28 17:42:03.000000000 +0200
+++ linux.dev/arch/mips/mm/tlbex-r4k.S 2005-05-29 15:04:43.000000000 +0200
@@ -168,6 +168,9 @@
.set noat
LEAF(except_vec0_r4000)
.set mips3
+#ifdef CONFIG_BCM4704
+ nop
+#endif
GET_PGD(k0, k1) # get pgd pointer
mfc0 k0, CP0_BADVADDR # Get faulting address
srl k0, k0, _PGDIR_SHIFT # get pgd only bits

147
target/linux/linux-2.4/patches/007-bcm94710_mmu.patch Normal file
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@ -0,0 +1,147 @@
diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
--- linux.old/arch/mips/mm/c-r4k.c 2005-05-28 17:42:06.000000000 +0200
+++ linux.dev/arch/mips/mm/c-r4k.c 2005-05-29 18:26:34.000000000 +0200
@@ -14,6 +14,12 @@
#include <linux/mm.h>
#include <linux/bitops.h>
+#ifdef CONFIG_BCM4710
+#include "../bcm947xx/include/typedefs.h"
+#include "../bcm947xx/include/sbconfig.h"
+#include <asm/paccess.h>
+#endif
+
#include <asm/bcache.h>
#include <asm/bootinfo.h>
#include <asm/cacheops.h>
@@ -390,6 +396,11 @@
addr = start & ~(dc_lsize - 1);
aend = (end - 1) & ~(dc_lsize - 1);
+#ifdef CONFIG_BCM4710
+ BCM4710_FILL_TLB(addr);
+ BCM4710_FILL_TLB(aend);
+#endif
+
while (1) {
/* Hit_Writeback_Inv_D */
protected_writeback_dcache_line(addr);
@@ -509,6 +520,10 @@
R4600_HIT_CACHEOP_WAR_IMPL;
a = addr & ~(dc_lsize - 1);
end = (addr + size - 1) & ~(dc_lsize - 1);
+#ifdef CONFIG_BCM4710
+ BCM4710_FILL_TLB(a);
+ BCM4710_FILL_TLB(end);
+#endif
while (1) {
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
if (a == end)
@@ -576,6 +591,10 @@
unsigned long ic_lsize = current_cpu_data.icache.linesz;
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
+#ifdef CONFIG_BCM4710
+ BCM4710_PROTECTED_FILL_TLB(addr);
+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
+#endif
R4600_HIT_CACHEOP_WAR_IMPL;
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
protected_flush_icache_line(addr & ~(ic_lsize - 1));
diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
--- linux.old/include/asm-mips/r4kcache.h 2005-05-28 17:42:06.000000000 +0200
+++ linux.dev/include/asm-mips/r4kcache.h 2005-05-29 18:34:46.000000000 +0200
@@ -15,6 +15,25 @@
#include <asm/asm.h>
#include <asm/cacheops.h>
+#ifdef CONFIG_BCM4710
+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
+
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
+
+#define cache_op(op,addr) \
+ BCM4710_DUMMY_RREG(); \
+ __asm__ __volatile__( \
+ " .set noreorder \n" \
+ " .set mips3\n\t \n" \
+ " cache %0, %1 \n" \
+ " .set mips0 \n" \
+ " .set reorder" \
+ : \
+ : "i" (op), "m" (*(unsigned char *)(addr)))
+
+#else
+
#define cache_op(op,addr) \
__asm__ __volatile__( \
" .set noreorder \n" \
@@ -24,6 +43,8 @@
" .set reorder" \
: \
: "i" (op), "m" (*(unsigned char *)(addr)))
+#endif
+
static inline void flush_icache_line_indexed(unsigned long addr)
{
@@ -47,6 +68,10 @@
static inline void flush_dcache_line(unsigned long addr)
{
+
+#ifdef CONFIG_BCM4710
+ BCM4710_DUMMY_RREG();
+#endif
cache_op(Hit_Writeback_Inv_D, addr);
}
@@ -196,7 +221,13 @@
unsigned long start = page;
unsigned long end = start + PAGE_SIZE;
+#ifdef CONFIG_BCM4710
+ BCM4710_FILL_TLB(start);
+#endif
do {
+#ifdef CONFIG_BCM4710
+ BCM4710_DUMMY_RREG();
+#endif
cache16_unroll32(start,Hit_Invalidate_I);
start += 0x200;
} while (start < end);
@@ -291,8 +322,12 @@
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x400)
+ for (addr = start; addr < end; addr += 0x400) {
+#ifdef CONFIG_BCM4710
+ BCM4710_DUMMY_RREG();
+#endif
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
+ }
}
static inline void blast_dcache32_page(unsigned long page)
@@ -300,6 +335,9 @@
unsigned long start = page;
unsigned long end = start + PAGE_SIZE;
+#ifdef CONFIG_BCM4710
+ __asm__ __volatile__("nop;nop;nop;nop");
+#endif
do {
cache32_unroll32(start,Hit_Writeback_Inv_D);
start += 0x400;
@@ -339,6 +377,9 @@
unsigned long start = page;
unsigned long end = start + PAGE_SIZE;
+#ifdef CONFIG_BCM4710
+ BCM4710_FILL_TLB(start);
+#endif
do {
cache32_unroll32(start,Hit_Invalidate_I);
start += 0x400;