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ar71xx: ag71xx: make switch register access atomic
Reading of the PHY registers occasionally returns with bogus values under heavy load. This misleads the PHY driver and thus causes false link/speed change notifications which leads to performance loss. This is easily noticable during an iperf session: ... [ 3] 52.0-53.0 sec 11.3 MBytes 94.4 Mbits/sec [ 3] 53.0-54.0 sec 11.4 MBytes 95.4 Mbits/sec eth1: link down br-lan: port 2(eth1) entering forwarding state eth1: link up (100Mbps/Full duplex) br-lan: port 2(eth1) entering forwarding state br-lan: port 2(eth1) entering forwarding state [ 3] 54.0-55.0 sec 6.75 MBytes 56.6 Mbits/sec [ 3] 55.0-56.0 sec 0.00 Bytes 0.00 bits/sec [ 3] 56.0-57.0 sec 10.5 MBytes 88.1 Mbits/sec ... [ 3] 169.0-170.0 sec 11.4 MBytes 95.4 Mbits/sec [ 3] 170.0-171.0 sec 11.4 MBytes 95.4 Mbits/sec eth1: link up (10Mbps/Half duplex) [ 3] 171.0-172.0 sec 7.63 MBytes 64.0 Mbits/sec [ 3] 172.0-173.0 sec 9.38 MBytes 78.6 Mbits/sec eth1: link up (100Mbps/Full duplex) [ 3] 173.0-174.0 sec 11.3 MBytes 94.4 Mbits/sec [ 3] 174.0-175.0 sec 11.4 MBytes 95.4 Mbits/sec git-svn-id: svn://svn.openwrt.org/openwrt/trunk@26856 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -233,37 +233,39 @@ static inline u16 mk_high_addr(u32 reg)
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static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
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{
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unsigned long flags;
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u16 phy_addr;
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u16 phy_reg;
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u32 hi, lo;
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reg = (reg & 0xfffffffc) >> 2;
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ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
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phy_addr = mk_phy_addr(reg);
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phy_reg = mk_phy_reg(reg);
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local_irq_save(flags);
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ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
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lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
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hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
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local_irq_restore(flags);
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return (hi << 16) | lo;
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}
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static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
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{
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unsigned long flags;
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u16 phy_addr;
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u16 phy_reg;
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reg = (reg & 0xfffffffc) >> 2;
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ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
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phy_addr = mk_phy_addr(reg);
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phy_reg = mk_phy_reg(reg);
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local_irq_save(flags);
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ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
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ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
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ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
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local_irq_restore(flags);
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}
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static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
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