mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 02:48:37 +02:00
lots of ifxmips fixes and features
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11673 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
parent
c4b8e2f0b8
commit
c223e82fd4
@ -32,7 +32,6 @@
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#include <asm/io.h>
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#include <linux/etherdevice.h>
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#include <asm/ifxmips/ifxmips.h>
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#include <asm/ifxmips/ifxmips_mii0.h>
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#define MAX_BOARD_NAME_LEN 32
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#define MAX_IFXMIPS_DEVS 9
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@ -63,7 +62,8 @@ struct ifxmips_board {
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spinlock_t ebu_lock = SPIN_LOCK_UNLOCKED;
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EXPORT_SYMBOL_GPL(ebu_lock);
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static struct ifxmips_mac ifxmips_mii_mac;
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static unsigned char ifxmips_mii_mac[6];
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static int ifxmips_brn = 0;
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static struct platform_device
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ifxmips_led =
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@ -86,7 +86,7 @@ ifxmips_mii =
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.id = 0,
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.name = "ifxmips_mii0",
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.dev = {
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.platform_data = &ifxmips_mii_mac,
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.platform_data = ifxmips_mii_mac,
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}
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};
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@ -172,9 +172,9 @@ ifxmips_set_mii0_mac(char *str)
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goto out;
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if((i != 5) && (str[(3 * i) + 2] != ':'))
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goto out;
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ifxmips_mii_mac.mac[i] = simple_strtoul(&str[3 * i], NULL, 16);
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ifxmips_mii_mac[i] = simple_strtoul(&str[3 * i], NULL, 16);
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}
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if(is_valid_ether_addr(ifxmips_mii_mac.mac))
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if(is_valid_ether_addr(ifxmips_mii_mac))
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cmdline_mac = 1;
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out:
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return 1;
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@ -257,7 +257,24 @@ static struct ifxmips_board boards[] =
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},
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};
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struct ifxmips_board* ifxmips_find_board(void)
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int
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ifxmips_find_brn_block(void){
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unsigned char temp[0];
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memcpy_fromio(temp, (void*)KSEG1ADDR(IFXMIPS_FLASH_START + 0x800000 - 0x10000), 8);
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if(memcmp(temp, "BRN-BOOT", 8) == 0)
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return 1;
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else
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return 0;
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}
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int
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ifxmips_has_brn_block(void)
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{
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return ifxmips_brn;
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}
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struct ifxmips_board*
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ifxmips_find_board(void)
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{
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int i;
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if(!*board_name)
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@ -274,9 +291,10 @@ ifxmips_init_devices(void)
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struct ifxmips_board *board = ifxmips_find_board();
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chiprev = ifxmips_r32(IFXMIPS_MPS_CHIPID);
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ifxmips_brn = ifxmips_find_brn_block();
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if(!cmdline_mac)
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random_ether_addr(ifxmips_mii_mac.mac);
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random_ether_addr(ifxmips_mii_mac);
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if(!board)
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{
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@ -31,46 +31,45 @@
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#include <linux/errno.h>
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#include <asm/ifxmips/ifxmips.h>
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#define FIX_FOR_36M_CRYSTAL 1
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#define BASIC_INPUT_CLOCK_FREQUENCY_1 35328000
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#define BASIC_INPUT_CLOCK_FREQUENCY_2 36000000
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#define BASIS_INPUT_CRYSTAL_USB 12000000
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#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
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#define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
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#define CGU_PLL0_PHASE_DIVIDER_ENABLE (*IFXMIPS_CGU_PLL0_CFG & (1 << 31))
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#define CGU_PLL0_BYPASS (*IFXMIPS_CGU_PLL0_CFG & (1 << 30))
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#define CGU_PLL0_SRC (*IFXMIPS_CGU_PLL0_CFG & (1 << 29))
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#define CGU_PLL0_CFG_DSMSEL (*IFXMIPS_CGU_PLL0_CFG & (1 << 28))
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#define CGU_PLL0_CFG_FRAC_EN (*IFXMIPS_CGU_PLL0_CFG & (1 << 27))
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#define CGU_PLL0_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 31))
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#define CGU_PLL0_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 30))
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#define CGU_PLL0_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 28))
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#define CGU_PLL0_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 27))
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#define CGU_PLL1_SRC (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 31))
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#define CGU_PLL1_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 30))
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#define CGU_PLL1_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 28))
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#define CGU_PLL1_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 27))
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#define CGU_PLL2_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 20))
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#define CGU_PLL2_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 19))
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#define CGU_SYS_FPI_SEL (1 << 6)
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#define CGU_SYS_DDR_SEL 0x3
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#define CGU_PLL0_SRC (1 << 29)
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#define CGU_PLL0_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
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#define CGU_PLL0_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
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#define CGU_PLL0_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
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#define CGU_PLL1_SRC (*IFXMIPS_CGU_PLL1_CFG & (1 << 31))
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#define CGU_PLL1_BYPASS (*IFXMIPS_CGU_PLL1_CFG & (1 << 30))
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#define CGU_PLL1_CFG_DSMSEL (*IFXMIPS_CGU_PLL1_CFG & (1 << 28))
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#define CGU_PLL1_CFG_FRAC_EN (*IFXMIPS_CGU_PLL1_CFG & (1 << 27))
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#define CGU_PLL1_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
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#define CGU_PLL1_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
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#define CGU_PLL1_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
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#define CGU_PLL2_PHASE_DIVIDER_ENABLE (*IFXMIPS_CGU_PLL2_CFG & (1 << 20))
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#define CGU_PLL2_BYPASS (*IFXMIPS_CGU_PLL2_CFG & (1 << 19))
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#define CGU_PLL2_SRC GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
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#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
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#define CGU_PLL2_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
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#define CGU_PLL2_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
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#define CGU_SYS_PPESEL GET_BITS(*IFXMIPS_CGU_SYS, 8, 7)
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#define CGU_SYS_FPI_SEL (*IFXMIPS_CGU_SYS & (1 << 6))
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#define CGU_SYS_CPU1SEL GET_BITS(*IFXMIPS_CGU_SYS, 5, 4)
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#define CGU_SYS_CPU0SEL GET_BITS(*IFXMIPS_CGU_SYS, 3, 2)
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#define CGU_SYS_DDR_SEL GET_BITS(*IFXMIPS_CGU_SYS, 1, 0)
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#define CGU_IF_CLK_PCI_CLK GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
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#define CGU_IF_CLK_USBSEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 5, 4)
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#define CGU_IF_CLK_MIISEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 1, 0)
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static unsigned int cgu_get_pll0_fdiv(void);
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unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
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#define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
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static inline unsigned int
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get_input_clock(int pll)
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@ -78,7 +77,7 @@ get_input_clock(int pll)
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switch(pll)
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{
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case 0:
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if(CGU_PLL0_SRC)
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if(ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
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return BASIS_INPUT_CRYSTAL_USB;
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else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
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return BASIC_INPUT_CLOCK_FREQUENCY_1;
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@ -169,134 +168,18 @@ cgu_get_pll0_fosc(void)
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CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
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}
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static inline unsigned int
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cgu_get_pll0_fps(int phase)
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{
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register unsigned int fps = cgu_get_pll0_fosc();
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switch(phase)
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{
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case 1:
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/* 1.25 */
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fps = ((fps << 2) + 2) / 5;
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break;
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case 2:
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/* 1.5 */
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fps = ((fps << 1) + 1) / 3;
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break;
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}
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return fps;
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}
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static unsigned int
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cgu_get_pll0_fdiv(void)
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{
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register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
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return (cgu_get_pll0_fosc() + (div >> 1)) / div;
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}
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static inline unsigned int
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cgu_get_pll1_fosc(void)
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{
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if(CGU_PLL1_BYPASS)
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return get_input_clock(1);
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else
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return !CGU_PLL1_CFG_FRAC_EN
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? dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, 0, CGU_PLL1_CFG_DSMSEL, 0)
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: dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, CGU_PLL1_CFG_PLLK, CGU_PLL1_CFG_DSMSEL, 0);
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}
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static inline unsigned int
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cgu_get_pll1_fps(void)
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{
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register unsigned int fps = cgu_get_pll1_fosc();
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return ((fps << 1) + 1) / 3;
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}
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static inline unsigned int
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cgu_get_pll1_fdiv(void)
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{
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return cgu_get_pll1_fosc();
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}
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static inline unsigned int
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cgu_get_pll2_fosc(void)
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{
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u64 res, clock = get_input_clock(2);
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if ( CGU_PLL2_BYPASS )
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return get_input_clock(2);
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res = (CGU_PLL2_CFG_PLLN + 1) * clock;
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do_div(res, CGU_PLL2_CFG_PLLM + 1);
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return res;
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}
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static inline unsigned int
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cgu_get_pll2_fps(int phase)
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{
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register unsigned int fps = cgu_get_pll2_fosc();
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switch ( phase )
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{
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case 1:
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/* 1.125 */
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fps = ((fps << 2) + 2) / 5; break;
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case 2:
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/* 1.25 */
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fps = ((fps << 3) + 4) / 9;
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}
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return fps;
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}
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static inline unsigned int
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cgu_get_pll2_fdiv(void)
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{
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register unsigned int div = CGU_IF_CLK_PCI_CLK + 1;
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return (cgu_get_pll2_fosc() + (div >> 1)) / div;
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}
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unsigned int
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cgu_get_mips_clock(int cpu)
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{
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register unsigned int ret = cgu_get_pll0_fosc();
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register unsigned int cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
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if(cpusel == 0)
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return ret;
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else if(cpusel == 2)
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ret <<= 1;
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switch(CGU_SYS_DDR_SEL)
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{
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default:
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case 0:
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return (ret + 1) / 2;
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case 1:
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return (ret * 2 + 2) / 5;
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case 2:
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return (ret + 1) / 3;
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case 3:
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return (ret + 2) / 4;
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}
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}
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unsigned int
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cgu_get_cpu_clock(void)
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{
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return cgu_get_mips_clock(0);
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}
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unsigned int
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cgu_get_io_region_clock(void)
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{
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register unsigned int ret = cgu_get_pll0_fosc();
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switch(CGU_SYS_DDR_SEL)
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switch(ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL)
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{
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default:
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case 0:
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@ -314,112 +197,16 @@ unsigned int
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cgu_get_fpi_bus_clock(int fpi)
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{
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register unsigned int ret = cgu_get_io_region_clock();
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if((fpi == 2) && (CGU_SYS_FPI_SEL))
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if((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
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ret >>= 1;
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return ret;
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}
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unsigned int
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cgu_get_pp32_clock(void)
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{
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switch(CGU_SYS_PPESEL)
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{
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default:
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case 0:
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return cgu_get_pll2_fps(1);
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case 1:
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return cgu_get_pll2_fps(2);
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case 2:
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return (cgu_get_pll2_fps(1) + 1) >> 1;
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case 3:
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return (cgu_get_pll2_fps(2) + 1) >> 1;
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}
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}
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unsigned int
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cgu_get_ethernet_clock(int mii)
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{
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switch(CGU_IF_CLK_MIISEL)
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{
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case 0:
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return (cgu_get_pll2_fosc() + 3) / 12;
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case 1:
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return (cgu_get_pll2_fosc() + 3) / 6;
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case 2:
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return 50000000;
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case 3:
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return 25000000;
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}
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return 0;
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}
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unsigned int
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cgu_get_usb_clock(void)
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{
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switch(CGU_IF_CLK_USBSEL)
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{
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case 0:
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return (cgu_get_pll2_fosc() + 12) / 25;
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case 1:
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return 12000000;
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case 2:
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return 12000000 / 4;
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case 3:
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return 12000000;
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}
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return 0;
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}
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unsigned int
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cgu_get_clockout(int clkout)
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{
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unsigned int fosc1 = cgu_get_pll1_fosc();
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unsigned int fosc2 = cgu_get_pll2_fosc();
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if(clkout > 3 || clkout < 0)
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return 0;
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switch(((unsigned int)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2))
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{
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case 0: /* 32.768KHz */
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case 15:
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return (fosc1 + 6000) / 12000;
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case 1: /* 1.536MHz */
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return (fosc1 + 128) / 256;
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case 2: /* 2.5MHz */
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return (fosc2 + 60) / 120;
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case 3: /* 12MHz */
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case 5:
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case 12:
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return (fosc2 + 12) / 25;
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case 4: /* 40MHz */
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return (cgu_get_pll2_fps(2) + 3) / 6;
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case 6: /* 24MHz */
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return (cgu_get_pll2_fps(2) + 5) / 10;
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case 7: /* 48MHz */
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return (cgu_get_pll2_fps(2) + 2) / 5;
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case 8: /* 25MHz */
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case 14:
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return (fosc2 + 6) / 12;
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case 9: /* 50MHz */
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case 13:
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return (fosc2 + 3) / 6;
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case 10:/* 30MHz */
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return (fosc2 + 5) / 10;
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case 11:/* 60MHz */
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return (fosc2 + 2) / 5;
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}
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return 0;
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}
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void cgu_setup_pci_clk(int external_clock)
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{
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//set clock to 33Mhz
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ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
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ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
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// internal or external clock
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if(external_clock)
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{
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ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~ (1 << 16), IFXMIPS_CGU_IFCCR);
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@ -430,26 +217,10 @@ void cgu_setup_pci_clk(int external_clock)
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}
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}
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unsigned int
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ifxmips_get_ddr_hz(void)
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{
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switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3)
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{
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||||
case 0:
|
||||
return CLOCK_167M;
|
||||
case 1:
|
||||
return CLOCK_133M;
|
||||
case 2:
|
||||
return CLOCK_111M;
|
||||
}
|
||||
return CLOCK_83M;
|
||||
}
|
||||
EXPORT_SYMBOL(ifxmips_get_ddr_hz);
|
||||
|
||||
unsigned int
|
||||
ifxmips_get_cpu_hz(void)
|
||||
{
|
||||
unsigned int ddr_clock = ifxmips_get_ddr_hz();
|
||||
unsigned int ddr_clock = DDR_HZ;
|
||||
switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
|
||||
{
|
||||
case 0:
|
||||
@ -464,11 +235,9 @@ EXPORT_SYMBOL(ifxmips_get_cpu_hz);
|
||||
unsigned int
|
||||
ifxmips_get_fpi_hz(void)
|
||||
{
|
||||
unsigned int ddr_clock = ifxmips_get_ddr_hz();
|
||||
unsigned int ddr_clock = DDR_HZ;
|
||||
if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
|
||||
return ddr_clock >> 1;
|
||||
return ddr_clock;
|
||||
}
|
||||
EXPORT_SYMBOL(ifxmips_get_fpi_hz);
|
||||
|
||||
|
||||
|
||||
@ -39,7 +39,6 @@
|
||||
#include <asm/semaphore.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/ifxmips/ifxmips.h>
|
||||
#include <asm/ifxmips/ifxmips_ioctl.h>
|
||||
|
||||
#define MAX_PORTS 2
|
||||
#define PINS_PER_PORT 16
|
||||
|
||||
@ -18,6 +18,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/ifxmips/ifxmips.h>
|
||||
@ -83,11 +84,13 @@ unsigned int *prom_get_cp1_base(void)
|
||||
{
|
||||
return prom_cp1_base;
|
||||
}
|
||||
EXPORT_SYMBOL(prom_get_cp1_base);
|
||||
|
||||
unsigned int prom_get_cp1_size(void)
|
||||
{
|
||||
return prom_cp1_size;
|
||||
}
|
||||
EXPORT_SYMBOL(prom_get_cp1_size);
|
||||
|
||||
void __init
|
||||
prom_init(void)
|
||||
|
||||
@ -27,6 +27,7 @@
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/cfi.h>
|
||||
#include <asm/ifxmips/ifxmips.h>
|
||||
#include <asm/ifxmips/ifxmips_prom.h>
|
||||
#include <asm/ifxmips/ifxmips_ebu.h>
|
||||
#include <linux/magic.h>
|
||||
#include <linux/platform_device.h>
|
||||
@ -90,14 +91,14 @@ ifxmips_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_
|
||||
}
|
||||
|
||||
static struct mtd_partition
|
||||
ifxmips_partitions[4] = {
|
||||
ifxmips_partitions[] = {
|
||||
{
|
||||
name:"U-Boot",
|
||||
name:"uboot",
|
||||
offset:0x00000000,
|
||||
size:0x00020000,
|
||||
},
|
||||
{
|
||||
name:"U-Boot-Env",
|
||||
name:"uboot_env",
|
||||
offset:0x00020000,
|
||||
size:0x00010000,
|
||||
},
|
||||
@ -111,6 +112,11 @@ ifxmips_partitions[4] = {
|
||||
offset:0x0,
|
||||
size:0x0,
|
||||
},
|
||||
{
|
||||
name:"board_config",
|
||||
offset:0x0,
|
||||
size:0x0,
|
||||
},
|
||||
};
|
||||
|
||||
int
|
||||
@ -121,6 +127,18 @@ find_uImage_size(unsigned long start_offset){
|
||||
return temp + 0x40;
|
||||
}
|
||||
|
||||
int
|
||||
find_brn_block(unsigned long start_offset){
|
||||
unsigned char temp[9];
|
||||
ifxmips_copy_from(&ifxmips_map, &temp, start_offset, 8);
|
||||
temp[8] = '\0';
|
||||
printk(KERN_INFO "data in brn block %s\n", temp);
|
||||
if(memcmp(temp, "BRN-BOOT", 8) == 0)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
detect_squashfs_partition(unsigned long start_offset){
|
||||
unsigned long temp;
|
||||
@ -170,12 +188,19 @@ ifxmips_mtd_probe(struct platform_device *dev)
|
||||
uimage_size += 0x10000;
|
||||
}
|
||||
|
||||
parts = &ifxmips_partitions[0];
|
||||
ifxmips_partitions[2].size = uimage_size;
|
||||
ifxmips_partitions[3].offset = ifxmips_partitions[2].offset + ifxmips_partitions[2].size;
|
||||
ifxmips_partitions[3].size = ((ifxmips_mtd->size >> 20) * 1024 * 1024) - ifxmips_partitions[3].offset;
|
||||
|
||||
parts = &ifxmips_partitions[0];
|
||||
add_mtd_partitions(ifxmips_mtd, parts, 4);
|
||||
if(ifxmips_has_brn_block())
|
||||
{
|
||||
ifxmips_partitions[3].size -= ifxmips_mtd->erasesize;
|
||||
ifxmips_partitions[4].offset = ifxmips_mtd->size - ifxmips_mtd->erasesize;
|
||||
ifxmips_partitions[4].size = ifxmips_mtd->erasesize;
|
||||
add_mtd_partitions(ifxmips_mtd, parts, 5);
|
||||
} else {
|
||||
add_mtd_partitions(ifxmips_mtd, parts, 4);
|
||||
}
|
||||
|
||||
printk(KERN_INFO "ifxmips_mtd: added ifxmips flash with %dMB\n", ifxmips_mtd->size >> 20);
|
||||
return 0;
|
||||
|
||||
@ -36,10 +36,15 @@
|
||||
#include <linux/init.h>
|
||||
#include <asm/delay.h>
|
||||
#include <asm/ifxmips/ifxmips.h>
|
||||
#include <asm/ifxmips/ifxmips_mii0.h>
|
||||
#include <asm/ifxmips/ifxmips_dma.h>
|
||||
#include <asm/ifxmips/ifxmips_pmu.h>
|
||||
|
||||
struct ifxmips_mii_priv {
|
||||
struct net_device_stats stats;
|
||||
struct dma_device_info *dma_device;
|
||||
struct sk_buff *skb;
|
||||
};
|
||||
|
||||
static struct net_device *ifxmips_mii0_dev;
|
||||
static unsigned char mac_addr[MAX_ADDR_LEN];
|
||||
|
||||
@ -63,6 +68,7 @@ ifxmips_read_mdio(u32 phy_addr, u32 phy_reg)
|
||||
((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
|
||||
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
|
||||
|
||||
while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
|
||||
ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
|
||||
while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
|
||||
val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
|
||||
@ -343,10 +349,10 @@ static int
|
||||
ifxmips_mii_probe(struct platform_device *dev)
|
||||
{
|
||||
int result = 0;
|
||||
struct ifxmips_mac *mac = (struct ifxmips_mac*)dev->dev.platform_data;
|
||||
unsigned char *mac = (unsigned char*)dev->dev.platform_data;
|
||||
ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv));
|
||||
ifxmips_mii0_dev->init = ifxmips_mii_dev_init;
|
||||
memcpy(mac_addr, mac->mac, 6);
|
||||
memcpy(mac_addr, mac, 6);
|
||||
strcpy(ifxmips_mii0_dev->name, "eth%d");
|
||||
ifxmips_mii_chip_init(REV_MII_MODE);
|
||||
result = register_netdev(ifxmips_mii0_dev);
|
||||
|
||||
@ -48,7 +48,6 @@
|
||||
#include <asm/bitops.h>
|
||||
#include <asm/ifxmips/ifxmips.h>
|
||||
#include <asm/ifxmips/ifxmips_irq.h>
|
||||
#include <asm/ifxmips/ifxmips_serial.h>
|
||||
|
||||
#define PORT_IFXMIPSASC 111
|
||||
|
||||
@ -161,7 +160,7 @@ ifxmipsasc_tx_chars(struct uart_port *port)
|
||||
}
|
||||
|
||||
while(((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
|
||||
>> ASCFSTAT_TXFFLOFF) != IFXMIPSASC_TXFIFO_FULL)
|
||||
>> ASCFSTAT_TXFFLOFF) != TXFIFO_FULL)
|
||||
{
|
||||
if(port->x_char)
|
||||
{
|
||||
@ -248,8 +247,8 @@ ifxmipsasc_startup(struct uart_port *port)
|
||||
ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC);
|
||||
ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC);
|
||||
ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL);
|
||||
ifxmips_w32(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
|
||||
ifxmips_w32(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
|
||||
ifxmips_w32(((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
|
||||
ifxmips_w32(((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
|
||||
wmb ();
|
||||
ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
|
||||
|
||||
@ -399,7 +398,7 @@ ifxmipsasc_type(struct uart_port *port)
|
||||
{
|
||||
if(port->type == PORT_IFXMIPSASC)
|
||||
{
|
||||
if(port->membase == IFXMIPS_ASC_BASE_ADDR)
|
||||
if(port->membase == (void*)IFXMIPS_ASC_BASE_ADDR)
|
||||
return "asc0";
|
||||
else
|
||||
return "asc1";
|
||||
@ -501,7 +500,7 @@ ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
|
||||
do {
|
||||
fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
|
||||
>> ASCFSTAT_TXFFLOFF;
|
||||
} while(fifocnt == IFXMIPSASC_TXFIFO_FULL);
|
||||
} while(fifocnt == TXFIFO_FULL);
|
||||
|
||||
if(s[i] == '\0')
|
||||
break;
|
||||
@ -512,7 +511,7 @@ ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
|
||||
do {
|
||||
fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
|
||||
>> ASCFSTAT_TXFFLOFF;
|
||||
} while(fifocnt == IFXMIPSASC_TXFIFO_FULL);
|
||||
} while(fifocnt == TXFIFO_FULL);
|
||||
}
|
||||
ifxmips_w32(s[i], (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
|
||||
}
|
||||
|
||||
@ -15,7 +15,6 @@
|
||||
*
|
||||
* Copyright (C) 2005 infineon
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
#ifndef _IFXMIPS_H__
|
||||
#define _IFXMIPS_H__
|
||||
@ -71,8 +70,41 @@
|
||||
#define ASCOPT_STOPB 0x8
|
||||
#define ASCOPT_PARODD 0x0
|
||||
#define ASCOPT_CREAD 0x20
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
#define TXFIFO_FL 1
|
||||
#define RXFIFO_FL 1
|
||||
#define TXFIFO_FULL 16
|
||||
#define ASCCLC_RMCMASK 0x0000FF00
|
||||
#define ASCCLC_RMCOFFSET 8
|
||||
#define ASCCON_M_8ASYNC 0x0
|
||||
#define ASCCON_M_7ASYNC 0x2
|
||||
#define ASCCON_ODD 0x00000020
|
||||
#define ASCCON_STP 0x00000080
|
||||
#define ASCCON_BRS 0x00000100
|
||||
#define ASCCON_FDE 0x00000200
|
||||
#define ASCCON_R 0x00008000
|
||||
#define ASCCON_FEN 0x00020000
|
||||
#define ASCCON_ROEN 0x00080000
|
||||
#define ASCCON_TOEN 0x00100000
|
||||
#define ASCSTATE_PE 0x00010000
|
||||
#define ASCSTATE_FE 0x00020000
|
||||
#define ASCSTATE_ROE 0x00080000
|
||||
#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
|
||||
#define ASCWHBSTATE_CLRREN 0x00000001
|
||||
#define ASCWHBSTATE_SETREN 0x00000002
|
||||
#define ASCWHBSTATE_CLRPE 0x00000004
|
||||
#define ASCWHBSTATE_CLRFE 0x00000008
|
||||
#define ASCWHBSTATE_CLRROE 0x00000020
|
||||
#define ASCTXFCON_TXFEN 0x0001
|
||||
#define ASCTXFCON_TXFFLU 0x0002
|
||||
#define ASCTXFCON_TXFITLMASK 0x3F00
|
||||
#define ASCTXFCON_TXFITLOFF 8
|
||||
#define ASCRXFCON_RXFEN 0x0001
|
||||
#define ASCRXFCON_RXFFLU 0x0002
|
||||
#define ASCRXFCON_RXFITLMASK 0x3F00
|
||||
#define ASCRXFCON_RXFITLOFF 8
|
||||
#define ASCFSTAT_RXFFLMASK 0x003F
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
|
||||
|
||||
|
||||
@ -334,7 +366,7 @@
|
||||
#define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
|
||||
#define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
|
||||
#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
|
||||
#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
|
||||
#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
|
||||
#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
|
||||
#define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
|
||||
#define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
|
||||
@ -472,7 +504,7 @@
|
||||
#define IFXMIPS_MPS_AD0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
|
||||
#define IFXMIPS_MPS_AD1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
|
||||
|
||||
#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
|
||||
#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
|
||||
#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
|
||||
#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
|
||||
#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
|
||||
|
||||
@ -1,15 +1,29 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
#ifndef _IFXMIPS_CGU_H__
|
||||
#define _IFXMIPS_CGU_H__
|
||||
u32 cgu_get_mips_clock(int cpu);
|
||||
u32 cgu_get_cpu_clock(void);
|
||||
u32 cgu_get_io_region_clock(void);
|
||||
u32 cgu_get_fpi_bus_clock(int fpi);
|
||||
u32 cgu_get_pp32_clock(void);
|
||||
u32 cgu_get_ethernet_clock(int mii);
|
||||
u32 cgu_get_usb_clock(void);
|
||||
u32 cgu_get_clockout(int clkout);
|
||||
|
||||
unsigned int cgu_get_mips_clock(int cpu);
|
||||
unsigned int cgu_get_io_region_clock(void);
|
||||
unsigned int cgu_get_fpi_bus_clock(int fpi);
|
||||
void cgu_setup_pci_clk(int internal_clock);
|
||||
u32 ifxmips_get_ddr_hz(void);
|
||||
u32 ifxmips_get_cpu_hz(void);
|
||||
u32 ifxmips_get_fpi_hz(void);
|
||||
unsigned int ifxmips_get_ddr_hz(void);
|
||||
unsigned int ifxmips_get_fpi_hz(void);
|
||||
unsigned int ifxmips_get_cpu_hz(void);
|
||||
|
||||
#endif
|
||||
|
||||
@ -12,9 +12,7 @@
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
#ifndef _IFXMIPS_GPIO_H__
|
||||
#define _IFXMIPS_GPIO_H__
|
||||
|
||||
@ -1,42 +0,0 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
#ifndef _IFXMIPS_IOCTL_H__
|
||||
#define _IFXMIPS_IOCTL_H__
|
||||
|
||||
/*------------ LED */
|
||||
|
||||
struct ifxmips_port_ioctl_parm
|
||||
{
|
||||
int port;
|
||||
int pin;
|
||||
int value;
|
||||
};
|
||||
|
||||
#define IFXMIPS_PORT_IOC_MAGIC 0xbf
|
||||
#define IFXMIPS_PORT_IOCOD _IOW(IFXMIPS_PORT_IOC_MAGIC,0,struct ifxmips_port_ioctl_parm)
|
||||
#define IFXMIPS_PORT_IOCPUDSEL _IOW(IFXMIPS_PORT_IOC_MAGIC,1,struct ifxmips_port_ioctl_parm)
|
||||
#define IFXMIPS_PORT_IOCPUDEN _IOW(IFXMIPS_PORT_IOC_MAGIC,2,struct ifxmips_port_ioctl_parm)
|
||||
#define IFXMIPS_PORT_IOCSTOFF _IOW(IFXMIPS_PORT_IOC_MAGIC,3,struct ifxmips_port_ioctl_parm)
|
||||
#define IFXMIPS_PORT_IOCDIR _IOW(IFXMIPS_PORT_IOC_MAGIC,4,struct ifxmips_port_ioctl_parm)
|
||||
#define IFXMIPS_PORT_IOCOUTPUT _IOW(IFXMIPS_PORT_IOC_MAGIC,5,struct ifxmips_port_ioctl_parm)
|
||||
#define IFXMIPS_PORT_IOCINPUT _IOWR(IFXMIPS_PORT_IOC_MAGIC,6,struct ifxmips_port_ioctl_parm)
|
||||
#define IFXMIPS_PORT_IOCALTSEL0 _IOW(IFXMIPS_PORT_IOC_MAGIC,7,struct ifxmips_port_ioctl_parm)
|
||||
#define IFXMIPS_PORT_IOCALTSEL1 _IOW(IFXMIPS_PORT_IOC_MAGIC,8,struct ifxmips_port_ioctl_parm)
|
||||
|
||||
#endif
|
||||
@ -15,7 +15,6 @@
|
||||
*
|
||||
* Copyright (C) 2005 infineon
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
#ifndef _IFXMIPS_IRQ__
|
||||
#define _IFXMIPS_IRQ__
|
||||
|
||||
@ -15,8 +15,12 @@
|
||||
*
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
#ifndef _IFXMIPS_LED_H__
|
||||
#define _IFXMIPS_LED_H__
|
||||
|
||||
extern void ifxmips_led_set(unsigned int led);
|
||||
extern void ifxmips_led_clear(unsigned int led);
|
||||
extern void ifxmips_led_blink_set(unsigned int led);
|
||||
extern void ifxmips_led_blink_clear(unsigned int led);
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,34 +0,0 @@
|
||||
#ifndef IFXMIPS_MII0_H
|
||||
#define IFXMIPS_MII0_H
|
||||
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/netdevice.h>
|
||||
|
||||
struct ifxmips_mii_priv {
|
||||
struct net_device_stats stats;
|
||||
struct dma_device_info *dma_device;
|
||||
struct sk_buff *skb;
|
||||
};
|
||||
|
||||
struct ifxmips_mac {
|
||||
unsigned char mac[6];
|
||||
};
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -14,7 +14,6 @@
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
#ifndef _IFXMIPS_PMU_H__
|
||||
#define _IFXMIPS_PMU_H__
|
||||
|
||||
@ -14,14 +14,13 @@
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2008 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _IFXPROM_H__
|
||||
#define _IFXPROM_H__
|
||||
|
||||
extern void prom_printf(const char * fmt, ...);
|
||||
extern u32 *prom_get_cp1_base(void);
|
||||
extern u32 prom_get_cp1_size(void);
|
||||
extern int ifxmips_has_brn_block(void);
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,194 +0,0 @@
|
||||
/* incaAscSio.h - (IFXMIPS) ASC UART tty driver header */
|
||||
|
||||
#ifndef __IFXMIPS_ASC_H
|
||||
#define __IFXMIPS_ASC_H
|
||||
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : serial.c
|
||||
** PROJECT : IFXMips
|
||||
** MODULES : ASC/UART
|
||||
**
|
||||
** DATE : 27 MAR 2006
|
||||
** AUTHOR : Liu Peng
|
||||
** DESCRIPTION : Asynchronous Serial Channel (ASC/UART) Driver Header File
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 27 MAR 2006 Liu Peng Initiate Version (rev 1.7)
|
||||
** 23 OCT 2006 Xu Liang Add GPL header.
|
||||
*******************************************************************************/
|
||||
|
||||
/* channel operating modes */
|
||||
/*#define ASCOPT_CSIZE 0x00000003
|
||||
#define ASCOPT_CS7 0x00000001
|
||||
#define ASCOPT_CS8 0x00000002
|
||||
#define ASCOPT_PARENB 0x00000004
|
||||
#define ASCOPT_STOPB 0x00000008
|
||||
#define ASCOPT_PARODD 0x00000010
|
||||
#define ASCOPT_CREAD 0x00000020
|
||||
*/
|
||||
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
|
||||
|
||||
/* ASC input select (0 or 1) */
|
||||
#define CONSOLE_TTY 0
|
||||
|
||||
#define IFXMIPSASC_TXFIFO_FL 1
|
||||
#define IFXMIPSASC_RXFIFO_FL 1
|
||||
#define IFXMIPSASC_TXFIFO_FULL 16
|
||||
|
||||
/* interrupt lines masks for the ASC device interrupts*/
|
||||
/* change these macroses if it's necessary */
|
||||
#define IFXMIPSASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
|
||||
|
||||
#define IFXMIPSASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
|
||||
#define IFXMIPSASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
|
||||
#define IFXMIPSASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
|
||||
#define IFXMIPSASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
|
||||
#define IFXMIPSASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
|
||||
#define IFXMIPSASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
|
||||
#define IFXMIPSASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
|
||||
|
||||
/* interrupt controller access macros */
|
||||
#define ASC_INTERRUPTS_ENABLE(X) \
|
||||
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) |= X;
|
||||
#define ASC_INTERRUPTS_DISABLE(X) \
|
||||
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) &= ~X;
|
||||
#define ASC_INTERRUPTS_CLEAR(X) \
|
||||
*((volatile unsigned int*) IFXMIPS_ICU_IM0_ISR) = X;
|
||||
|
||||
/* CLC register's bits and bitfields */
|
||||
#define ASCCLC_DISR 0x00000001
|
||||
#define ASCCLC_DISS 0x00000002
|
||||
#define ASCCLC_RMCMASK 0x0000FF00
|
||||
#define ASCCLC_RMCOFFSET 8
|
||||
|
||||
/* CON register's bits and bitfields */
|
||||
#define ASCCON_MODEMASK 0x0000000f
|
||||
#define ASCCON_M_8ASYNC 0x0
|
||||
#define ASCCON_M_8IRDA 0x1
|
||||
#define ASCCON_M_7ASYNC 0x2
|
||||
#define ASCCON_M_7IRDA 0x3
|
||||
#define ASCCON_WLSMASK 0x0000000c
|
||||
#define ASCCON_WLSOFFSET 2
|
||||
#define ASCCON_WLS_8BIT 0x0
|
||||
#define ASCCON_WLS_7BIT 0x1
|
||||
#define ASCCON_PEN 0x00000010
|
||||
#define ASCCON_ODD 0x00000020
|
||||
#define ASCCON_SP 0x00000040
|
||||
#define ASCCON_STP 0x00000080
|
||||
#define ASCCON_BRS 0x00000100
|
||||
#define ASCCON_FDE 0x00000200
|
||||
#define ASCCON_ERRCLK 0x00000400
|
||||
#define ASCCON_EMMASK 0x00001800
|
||||
#define ASCCON_EMOFFSET 11
|
||||
#define ASCCON_EM_ECHO_OFF 0x0
|
||||
#define ASCCON_EM_ECHO_AB 0x1
|
||||
#define ASCCON_EM_ECHO_ON 0x2
|
||||
#define ASCCON_LB 0x00002000
|
||||
#define ASCCON_ACO 0x00004000
|
||||
#define ASCCON_R 0x00008000
|
||||
#define ASCCON_PAL 0x00010000
|
||||
#define ASCCON_FEN 0x00020000
|
||||
#define ASCCON_RUEN 0x00040000
|
||||
#define ASCCON_ROEN 0x00080000
|
||||
#define ASCCON_TOEN 0x00100000
|
||||
#define ASCCON_BEN 0x00200000
|
||||
#define ASCCON_TXINV 0x01000000
|
||||
#define ASCCON_RXINV 0x02000000
|
||||
#define ASCCON_TXMSB 0x04000000
|
||||
#define ASCCON_RXMSB 0x08000000
|
||||
|
||||
/* STATE register's bits and bitfields */
|
||||
#define ASCSTATE_REN 0x00000001
|
||||
#define ASCSTATE_PE 0x00010000
|
||||
#define ASCSTATE_FE 0x00020000
|
||||
#define ASCSTATE_RUE 0x00040000
|
||||
#define ASCSTATE_ROE 0x00080000
|
||||
#define ASCSTATE_TOE 0x00100000
|
||||
#define ASCSTATE_BE 0x00200000
|
||||
#define ASCSTATE_TXBVMASK 0x07000000
|
||||
#define ASCSTATE_TXBVOFFSET 24
|
||||
#define ASCSTATE_TXEOM 0x08000000
|
||||
#define ASCSTATE_RXBVMASK 0x70000000
|
||||
#define ASCSTATE_RXBVOFFSET 28
|
||||
#define ASCSTATE_RXEOM 0x80000000
|
||||
#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
|
||||
|
||||
/* WHBSTATE register's bits and bitfields */
|
||||
#define ASCWHBSTATE_CLRREN 0x00000001
|
||||
#define ASCWHBSTATE_SETREN 0x00000002
|
||||
#define ASCWHBSTATE_CLRPE 0x00000004
|
||||
#define ASCWHBSTATE_CLRFE 0x00000008
|
||||
#define ASCWHBSTATE_CLRRUE 0x00000010
|
||||
#define ASCWHBSTATE_CLRROE 0x00000020
|
||||
#define ASCWHBSTATE_CLRTOE 0x00000040
|
||||
#define ASCWHBSTATE_CLRBE 0x00000080
|
||||
#define ASCWHBSTATE_SETPE 0x00000100
|
||||
#define ASCWHBSTATE_SETFE 0x00000200
|
||||
#define ASCWHBSTATE_SETRUE 0x00000400
|
||||
#define ASCWHBSTATE_SETROE 0x00000800
|
||||
#define ASCWHBSTATE_SETTOE 0x00001000
|
||||
#define ASCWHBSTATE_SETBE 0x00002000
|
||||
|
||||
/* ABCON register's bits and bitfields */
|
||||
#define ASCABCON_ABEN 0x0001
|
||||
#define ASCABCON_AUREN 0x0002
|
||||
#define ASCABCON_ABSTEN 0x0004
|
||||
#define ASCABCON_ABDETEN 0x0008
|
||||
#define ASCABCON_FCDETEN 0x0010
|
||||
|
||||
/* FDV register mask, offset and bitfields*/
|
||||
#define ASCFDV_VALUE_MASK 0x000001FF
|
||||
|
||||
/* WHBABCON register's bits and bitfields */
|
||||
#define ASCWHBABCON_CLRABEN 0x0001
|
||||
#define ASCWHBABCON_SETABEN 0x0002
|
||||
|
||||
/* ABSTAT register's bits and bitfields */
|
||||
#define ASCABSTAT_FCSDET 0x0001
|
||||
#define ASCABSTAT_FCCDET 0x0002
|
||||
#define ASCABSTAT_SCSDET 0x0004
|
||||
#define ASCABSTAT_SCCDET 0x0008
|
||||
#define ASCABSTAT_DETWAIT 0x0010
|
||||
|
||||
/* WHBABSTAT register's bits and bitfields */
|
||||
#define ASCWHBABSTAT_CLRFCSDET 0x0001
|
||||
#define ASCWHBABSTAT_SETFCSDET 0x0002
|
||||
#define ASCWHBABSTAT_CLRFCCDET 0x0004
|
||||
#define ASCWHBABSTAT_SETFCCDET 0x0008
|
||||
#define ASCWHBABSTAT_CLRSCSDET 0x0010
|
||||
#define ASCWHBABSTAT_SETSCSDET 0x0020
|
||||
#define ASCWHBABSTAT_CLRSCCDET 0x0040
|
||||
#define ASCWHBABSTAT_SETSCCDET 0x0080
|
||||
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
|
||||
#define ASCWHBABSTAT_SETDETWAIT 0x0200
|
||||
|
||||
/* TXFCON register's bits and bitfields */
|
||||
#define ASCTXFCON_TXFIFO1 0x00000400
|
||||
#define ASCTXFCON_TXFEN 0x0001
|
||||
#define ASCTXFCON_TXFFLU 0x0002
|
||||
#define ASCTXFCON_TXFITLMASK 0x3F00
|
||||
#define ASCTXFCON_TXFITLOFF 8
|
||||
|
||||
/* RXFCON register's bits and bitfields */
|
||||
#define ASCRXFCON_RXFIFO1 0x00000400
|
||||
#define ASCRXFCON_RXFEN 0x0001
|
||||
#define ASCRXFCON_RXFFLU 0x0002
|
||||
#define ASCRXFCON_RXFITLMASK 0x3F00
|
||||
#define ASCRXFCON_RXFITLOFF 8
|
||||
|
||||
/* FSTAT register's bits and bitfields */
|
||||
#define ASCFSTAT_RXFFLMASK 0x003F
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
|
||||
#endif /* __IFXMIPS_ASC_H */
|
||||
Loading…
Reference in New Issue
Block a user