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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 03:32:25 +02:00
[brcm63xx] some more fixes to the SPI controller driver
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@15146 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -36,7 +36,7 @@
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#include <bcm63xx_dev_spi.h>
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#define PFX KBUILD_MODNAME
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#define DRV_VER "0.1.1"
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#define DRV_VER "0.1.2"
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struct bcm63xx_spi {
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/* bitbang has to be first */
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@ -62,15 +62,16 @@ struct bcm63xx_spi {
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static void bcm63xx_spi_chipselect(struct spi_device *spi, int is_on)
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{
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struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
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u16 val;
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val = bcm_spi_readw(SPI_CMD);
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val = bcm_spi_readw(bs->regs, SPI_CMD);
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if (is_on == BITBANG_CS_INACTIVE)
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val |= SPI_CMD_NOOP;
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else if (is_on == BITBANG_CS_ACTIVE)
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val |= (1 << spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
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bcm_spi_writew(val, SPI_CMD);
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bcm_spi_writew(val, bs->regs, SPI_CMD);
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}
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static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
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@ -125,7 +126,7 @@ static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
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break;
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}
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bcm_spi_writeb(clk_cfg, SPI_CLK_CFG);
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bcm_spi_writeb(clk_cfg, bs->regs, SPI_CLK_CFG);
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dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
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div, hz, clk_cfg);
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@ -172,14 +173,14 @@ static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
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u8 tail;
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/* Fill the Tx FIFO with as many bytes as possible */
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tail = bcm_spi_readb(SPI_MSG_TAIL);
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tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
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while ((tail < bs->fifo_size) && (bs->remaining_bytes > 0)) {
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if (bs->tx_ptr)
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bcm_spi_writeb(*bs->tx_ptr++, SPI_MSG_DATA);
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bcm_spi_writeb(*bs->tx_ptr++, bs->regs, SPI_MSG_DATA);
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else
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bcm_spi_writeb(0, SPI_MSG_DATA);
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bcm_spi_writeb(0, bs->regs, SPI_MSG_DATA);
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bs->remaining_bytes--;
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tail = bcm_spi_readb(SPI_MSG_TAIL);
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tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
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}
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}
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@ -202,24 +203,24 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
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/* Enable the command done interrupt which
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* we use to determine completion of a command */
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bcm_writeb(SPI_INTR_CMD_DONE, SPI_INT_MASK);
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bcm_spi_writeb(SPI_INTR_CMD_DONE, bs->regs, SPI_INT_MASK);
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/* Fill in the Message control register */
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msg_ctl = bcm_spi_readb(SPI_MSG_CTL);
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msg_ctl = bcm_spi_readb(bs->regs, SPI_MSG_CTL);
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msg_ctl |= (t->len << SPI_BYTE_CNT_SHIFT);
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msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
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bcm_spi_writeb(msg_ctl, SPI_MSG_CTL);
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bcm_spi_writeb(msg_ctl, bs->regs, SPI_MSG_CTL);
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/* Issue the transfer */
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cmd = bcm_spi_readb(SPI_CMD);
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cmd = bcm_spi_readb(bs->regs, SPI_CMD);
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cmd |= SPI_CMD_START_IMMEDIATE;
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cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
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bcm_spi_writeb(cmd, SPI_CMD);
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bcm_spi_writeb(cmd, bs->regs, SPI_CMD);
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wait_for_completion(&bs->done);
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/* Disable the CMD_DONE interrupt */
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bcm_spi_writeb(~(SPI_INTR_CMD_DONE), SPI_INT_MASK);
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bcm_spi_writeb(~(SPI_INTR_CMD_DONE), bs->regs, SPI_INT_MASK);
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return t->len - bs->remaining_bytes;
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}
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@ -235,23 +236,23 @@ static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
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u16 cmd;
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/* Read interupts and clear them immediately */
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intr = bcm_spi_readb(SPI_INT_STATUS);
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bcm_writeb(SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
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intr = bcm_spi_readb(bs->regs, SPI_INT_STATUS);
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bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_STATUS);
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/* A tansfer completed */
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if (intr & SPI_INTR_CMD_DONE) {
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u8 rx_empty;
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rx_empty = bcm_spi_readb(SPI_ST);
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rx_empty = bcm_spi_readb(bs->regs, SPI_ST);
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/* Read out all the data */
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while ((rx_empty & SPI_RX_EMPTY) == 0) {
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u8 data;
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data = bcm_spi_readb(SPI_RX_DATA);
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data = bcm_spi_readb(bs->regs, SPI_RX_DATA);
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if (bs->rx_ptr)
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*bs->rx_ptr++ = data;
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rx_empty = bcm_spi_readb(SPI_RX_EMPTY);
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rx_empty = bcm_spi_readb(bs->regs, SPI_RX_EMPTY);
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}
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/* See if there is more data to send */
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@ -259,10 +260,10 @@ static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
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bcm63xx_spi_fill_tx_fifo(bs);
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/* Start the transfer */
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cmd = bcm_spi_readb(SPI_CMD);
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cmd = bcm_spi_readb(bs->regs, SPI_CMD);
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cmd |= SPI_CMD_START_IMMEDIATE;
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cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
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bcm_spi_writeb(cmd, SPI_CMD);
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bcm_spi_writeb(cmd, bs->regs, SPI_CMD);
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} else
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complete(&bs->done);
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}
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@ -346,8 +347,8 @@ static int __init bcm63xx_spi_probe(struct platform_device *pdev)
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/* Initialize hardware */
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clk_enable(bs->clk);
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bcm_spi_writew(SPI_CMD_HARD_RESET, SPI_CMD);
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bcm_spi_writeb(SPI_INTR_CLEAR_ALL, SPI_INT_MASK);
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bcm_spi_writew(SPI_CMD_HARD_RESET, bs->regs, SPI_CMD);
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bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
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dev_info(&pdev->dev, PFX " at 0x%08x (irq %d, FIFOs size %d) v%s\n",
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r->start, irq, bs->fifo_size, DRV_VER);
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@ -442,3 +443,4 @@ MODULE_ALIAS("platform:bcm63xx_spi");
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MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
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MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(DRV_VER);
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@ -93,15 +93,15 @@
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/*
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* helpers for the SPI register sets
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*/
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#define bcm_spi_readb(o) bcm_readb(bcm63xx_regset_address(RSET_SPI) + \
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#define bcm_spi_readb(b,o) bcm_readb((b) + \
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bcm63xx_spireg(o))
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#define bcm_spi_readw(o) bcm_readw(bcm63xx_regset_address(RSET_SPI) + \
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#define bcm_spi_readw(b,o) bcm_readw((b) + \
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bcm63xx_spireg(o))
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#define bcm_spi_writeb(v,o) bcm_writeb((v), \
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bcm63xx_regset_address(RSET_SPI) + \
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#define bcm_spi_writeb(v,b,o) bcm_writeb((v), \
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(b) + \
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bcm63xx_spireg(o))
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#define bcm_spi_writew(v,o) bcm_writew((v), \
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bcm63xx_regset_address(RSET_SPI) + \
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#define bcm_spi_writew(v,b,o) bcm_writew((v), \
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(b) + \
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bcm63xx_spireg(o))
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#endif /* ! BCM63XX_IO_H_ */
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