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[ar71xx] fix AR7240 PCI IRQ support
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16669 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -93,6 +93,81 @@ static void __init ar71xx_pci_irq_init(void)
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setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
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}
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static void ar724x_pci_irq_dispatch(void)
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{
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u32 pending;
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pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
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ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
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if (pending & AR724X_PCI_INT_DEV0)
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do_IRQ(AR71XX_PCI_IRQ_DEV0);
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else
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spurious_interrupt();
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}
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static void ar724x_pci_irq_unmask(unsigned int irq)
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{
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switch (irq) {
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case AR71XX_PCI_IRQ_DEV0:
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irq -= AR71XX_PCI_IRQ_BASE;
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ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
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ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
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AR724X_PCI_INT_DEV0);
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/* flush write */
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ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
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}
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}
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static void ar724x_pci_irq_mask(unsigned int irq)
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{
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switch (irq) {
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case AR71XX_PCI_IRQ_DEV0:
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irq -= AR71XX_PCI_IRQ_BASE;
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ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
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ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
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~AR724X_PCI_INT_DEV0);
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/* flush write */
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ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
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ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
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ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
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AR724X_PCI_INT_DEV0);
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/* flush write */
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ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
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}
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}
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static struct irq_chip ar724x_pci_irq_chip = {
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.name = "AR724X PCI ",
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.mask = ar724x_pci_irq_mask,
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.unmask = ar724x_pci_irq_unmask,
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.mask_ack = ar724x_pci_irq_mask,
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};
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static struct irqaction ar724x_pci_irqaction = {
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.handler = no_action,
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.name = "cascade [AR724X PCI]",
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};
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static void __init ar724x_pci_irq_init(void)
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{
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int i;
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ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
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ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
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for (i = AR71XX_PCI_IRQ_BASE;
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i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
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handle_level_irq);
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}
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setup_irq(AR71XX_CPU_IRQ_PCI, &ar724x_pci_irqaction);
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}
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#endif /* CONFIG_PCI */
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static void ar71xx_gpio_irq_dispatch(void)
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@ -306,10 +381,14 @@ void __init arch_init_irq(void)
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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case AR71XX_SOC_AR7240:
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#ifdef CONFIG_PCI
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ar71xx_pci_irq_init();
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ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
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#endif
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case AR71XX_SOC_AR7240:
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#ifdef CONFIG_PCI
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ar724x_pci_irq_init();
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ar71xx_ip2_irq_handler = ar724x_pci_irq_dispatch;
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#endif
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break;
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case AR71XX_SOC_AR9130:
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@ -56,6 +56,13 @@
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#define AR71XX_DMA_SIZE 0x10000
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#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
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#define AR71XX_STEREO_SIZE 0x10000
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#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
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#define AR724X_PCI_CRP_SIZE 0x100
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#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
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#define AR724X_PCI_CTRL_SIZE 0x100
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#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
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#define AR91XX_WMAC_SIZE 0x30000
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@ -338,6 +345,34 @@ void ar71xx_ddr_flush(u32 reg);
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#define PCI_IDSEL_ADL_START 17
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#define AR7240_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN4_OFFS)
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#define AR7240_PCI_CFG_SIZE 0x100
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#define AR724X_PCI_REG_INT_STATUS 0x4c
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#define AR724X_PCI_REG_INT_MASK 0x50
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#define AR724X_PCI_INT_DEV0 BIT(14)
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static inline void ar724x_pci_wr(unsigned reg, u32 val)
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{
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void __iomem *base;
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base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
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__raw_writel(val, base + reg);
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iounmap(base);
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}
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static inline u32 ar724x_pci_rr(unsigned reg)
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{
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void __iomem *base;
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u32 ret;
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base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
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ret = __raw_readl(base + reg);
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iounmap(base);
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return ret;
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}
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/*
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* RESET block
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*/
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