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[ar71xx] fix AR7240 PCI IRQ support
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16669 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@@ -56,6 +56,13 @@
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#define AR71XX_DMA_SIZE 0x10000
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#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
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#define AR71XX_STEREO_SIZE 0x10000
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#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
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#define AR724X_PCI_CRP_SIZE 0x100
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#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
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#define AR724X_PCI_CTRL_SIZE 0x100
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#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
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#define AR91XX_WMAC_SIZE 0x30000
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@@ -338,6 +345,34 @@ void ar71xx_ddr_flush(u32 reg);
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#define PCI_IDSEL_ADL_START 17
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#define AR7240_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN4_OFFS)
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#define AR7240_PCI_CFG_SIZE 0x100
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#define AR724X_PCI_REG_INT_STATUS 0x4c
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#define AR724X_PCI_REG_INT_MASK 0x50
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#define AR724X_PCI_INT_DEV0 BIT(14)
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static inline void ar724x_pci_wr(unsigned reg, u32 val)
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{
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void __iomem *base;
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base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
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__raw_writel(val, base + reg);
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iounmap(base);
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}
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static inline u32 ar724x_pci_rr(unsigned reg)
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{
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void __iomem *base;
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u32 ret;
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base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
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ret = __raw_readl(base + reg);
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iounmap(base);
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return ret;
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}
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/*
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* RESET block
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*/
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