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[ar71xx] ag71xx driver: fix RX_STATUS_OF bitmask, and add DMA status register bit descriptions
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13463 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -37,7 +37,7 @@
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#define ETH_FCS_LEN 4
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#define AG71XX_DRV_NAME "ag71xx"
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#define AG71XX_DRV_VERSION "0.5.4"
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#define AG71XX_DRV_VERSION "0.5.5"
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#define AG71XX_NAPI_TX 1
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@ -287,17 +287,17 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
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#define MII_IND_BUSY BIT(0)
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#define MII_IND_INVALID BIT(2)
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#define TX_CTRL_TXE BIT(0)
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#define TX_CTRL_TXE BIT(0) /* Tx Enable */
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#define TX_STATUS_PS BIT(0)
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#define TX_STATUS_UR BIT(1)
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#define TX_STATUS_BE BIT(3)
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#define TX_STATUS_PS BIT(0) /* Packet Sent */
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#define TX_STATUS_UR BIT(1) /* Tx Underrun */
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#define TX_STATUS_BE BIT(3) /* Bus Error */
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#define RX_CTRL_RXE BIT(0)
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#define RX_CTRL_RXE BIT(0) /* Rx Enable */
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#define RX_STATUS_PR BIT(0)
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#define RX_STATUS_OF BIT(1)
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#define RX_STATUS_BE BIT(3)
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#define RX_STATUS_PR BIT(0) /* Packet Received */
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#define RX_STATUS_OF BIT(2) /* Rx Overflow */
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#define RX_STATUS_BE BIT(3) /* Bus Error */
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#define MII_CTRL_IF_MASK 3
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#define MII_CTRL_SPEED_SHIFT 4
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