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Code

change danube 2 ifxmips

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9821 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic 2007-12-22 00:17:22 +00:00
parent 9f57cb9722
commit cf6dac9a38
31 changed files with 1846 additions and 1845 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
target/linux/ifxmips/config-2.6.23
View File

@ -39,15 +39,6 @@ CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_DANUBE=y
CONFIG_DANUBE_ASC_UART=y
CONFIG_DANUBE_EEPROM=y
CONFIG_DANUBE_GPIO=y
CONFIG_DANUBE_LED=y
CONFIG_DANUBE_MII0=y
CONFIG_DANUBE_MII1=y
CONFIG_DANUBE_SSC=y
CONFIG_DANUBE_WDT=y
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
@ -65,9 +56,19 @@ CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
# CONFIG_I2C is not set
# CONFIG_IDE is not set
CONFIG_IFXMIPS=y
CONFIG_IFXMIPS_ASC_UART=y
CONFIG_IFXMIPS_EEPROM=y
CONFIG_IFXMIPS_GPIO=y
CONFIG_IFXMIPS_LED=y
# CONFIG_IFXMIPS_MII0 is not set
# CONFIG_IFXMIPS_MII1 is not set
CONFIG_IFXMIPS_SSC=y
CONFIG_IFXMIPS_WDT=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQ_CPU=y
CONFIG_KALLSYMS=y
# CONFIG_LEDS_ALIX is not set
# CONFIG_LEMOTE_FULONG is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
@ -106,12 +107,12 @@ CONFIG_MTD_CHAR=y
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_DANUBE=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_IFXMIPS=y
# CONFIG_MTD_JEDECPROBE is not set
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
@ -153,7 +154,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_DANUBE=y
# CONFIG_SERIAL_IFXMIPS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set

14
target/linux/ifxmips/files/arch/mips/danube/Kconfig
View File

@ -2,33 +2,33 @@
menu "Danube built-in"
config DANUBE_ASC_UART
config IFXMIPS_ASC_UART
bool "Danube asc uart"
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
default y
config MTD_DANUBE
config MTD_IFXMIPS
bool "Danube flash map"
default y
config DANUBE_WDT
config IFXMIPS_WDT
bool "Danube watchdog"
default y
config DANUBE_LED
config IFXMIPS_LED
bool "Danube led"
default y
config DANUBE_GPIO
config IFXMIPS_GPIO
bool "Danube gpio"
default y
config DANUBE_SSC
config IFXMIPS_SSC
bool "Danube ssc"
default y
config DANUBE_EEPROM
config IFXMIPS_EEPROM
bool "Danube eeprom"
default y

2
target/linux/ifxmips/files/arch/mips/danube/Makefile
View File

@ -4,7 +4,7 @@
#
# Makefile for Infineon Danube
#
obj-y := reset.o prom.o setup.o interrupt.o dma-core.o
obj-y := reset.o prom.o setup.o interrupt.o dma-core.o pmu.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_KGDB) += kgdb_serial.o

204
target/linux/ifxmips/files/arch/mips/danube/dma-core.c
View File

@ -25,7 +25,7 @@
#include <asm/danube/danube_pmu.h>
/*25 descriptors for each dma channel,4096/8/20=25.xx*/
#define DANUBE_DMA_DESCRIPTOR_OFFSET 25
#define IFXMIPS_DMA_DESCRIPTOR_OFFSET 25
#define MAX_DMA_DEVICE_NUM 6 /*max ports connecting to dma */
#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */
@ -44,26 +44,26 @@ char global_device_name[MAX_DMA_DEVICE_NUM][20] =
{ {"PPE"}, {"DEU"}, {"SPI"}, {"SDIO"}, {"MCTRL0"}, {"MCTRL1"} };
_dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
{"PPE", DANUBE_DMA_RX, 0, DANUBE_DMA_CH0_INT, 0},
{"PPE", DANUBE_DMA_TX, 0, DANUBE_DMA_CH1_INT, 0},
{"PPE", DANUBE_DMA_RX, 1, DANUBE_DMA_CH2_INT, 1},
{"PPE", DANUBE_DMA_TX, 1, DANUBE_DMA_CH3_INT, 1},
{"PPE", DANUBE_DMA_RX, 2, DANUBE_DMA_CH4_INT, 2},
{"PPE", DANUBE_DMA_TX, 2, DANUBE_DMA_CH5_INT, 2},
{"PPE", DANUBE_DMA_RX, 3, DANUBE_DMA_CH6_INT, 3},
{"PPE", DANUBE_DMA_TX, 3, DANUBE_DMA_CH7_INT, 3},
{"DEU", DANUBE_DMA_RX, 0, DANUBE_DMA_CH8_INT, 0},
{"DEU", DANUBE_DMA_TX, 0, DANUBE_DMA_CH9_INT, 0},
{"DEU", DANUBE_DMA_RX, 1, DANUBE_DMA_CH10_INT, 1},
{"DEU", DANUBE_DMA_TX, 1, DANUBE_DMA_CH11_INT, 1},
{"SPI", DANUBE_DMA_RX, 0, DANUBE_DMA_CH12_INT, 0},
{"SPI", DANUBE_DMA_TX, 0, DANUBE_DMA_CH13_INT, 0},
{"SDIO", DANUBE_DMA_RX, 0, DANUBE_DMA_CH14_INT, 0},
{"SDIO", DANUBE_DMA_TX, 0, DANUBE_DMA_CH15_INT, 0},
{"MCTRL0", DANUBE_DMA_RX, 0, DANUBE_DMA_CH16_INT, 0},
{"MCTRL0", DANUBE_DMA_TX, 0, DANUBE_DMA_CH17_INT, 0},
{"MCTRL1", DANUBE_DMA_RX, 1, DANUBE_DMA_CH18_INT, 1},
{"MCTRL1", DANUBE_DMA_TX, 1, DANUBE_DMA_CH19_INT, 1}
{"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0},
{"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0},
{"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1},
{"PPE", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH3_INT, 1},
{"PPE", IFXMIPS_DMA_RX, 2, IFXMIPS_DMA_CH4_INT, 2},
{"PPE", IFXMIPS_DMA_TX, 2, IFXMIPS_DMA_CH5_INT, 2},
{"PPE", IFXMIPS_DMA_RX, 3, IFXMIPS_DMA_CH6_INT, 3},
{"PPE", IFXMIPS_DMA_TX, 3, IFXMIPS_DMA_CH7_INT, 3},
{"DEU", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH8_INT, 0},
{"DEU", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH9_INT, 0},
{"DEU", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH10_INT, 1},
{"DEU", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH11_INT, 1},
{"SPI", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH12_INT, 0},
{"SPI", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH13_INT, 0},
{"SDIO", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH14_INT, 0},
{"SDIO", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH15_INT, 0},
{"MCTRL0", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH16_INT, 0},
{"MCTRL0", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH17_INT, 0},
{"MCTRL1", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH18_INT, 1},
{"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1}
};
_dma_chan_map *chan_map = default_dma_map;
@ -97,9 +97,9 @@ enable_ch_irq (_dma_channel_info *pCh)
int flag;
local_irq_save(flag);
writel(chan_no, DANUBE_DMA_CS);
writel(0x4a, DANUBE_DMA_CIE);
writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
writel(chan_no, IFXMIPS_DMA_CS);
writel(0x4a, IFXMIPS_DMA_CIE);
writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
local_irq_restore(flag);
enable_danube_irq(pCh->irq);
}
@ -112,9 +112,9 @@ disable_ch_irq (_dma_channel_info *pCh)
local_irq_save(flag);
g_danube_dma_int_status &= ~(1 << chan_no);
writel(chan_no, DANUBE_DMA_CS);
writel(0, DANUBE_DMA_CIE);
writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN);
writel(chan_no, IFXMIPS_DMA_CS);
writel(0, IFXMIPS_DMA_CIE);
writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
local_irq_restore(flag);
mask_and_ack_danube_irq(pCh->irq);
}
@ -126,9 +126,9 @@ open_chan (_dma_channel_info *pCh)
int chan_no = (int)(pCh - dma_chan);
local_irq_save(flag);
writel(chan_no, DANUBE_DMA_CS);
writel(readl(DANUBE_DMA_CCTRL) | 1, DANUBE_DMA_CCTRL);
if(pCh->dir == DANUBE_DMA_RX)
writel(chan_no, IFXMIPS_DMA_CS);
writel(readl(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL);
if(pCh->dir == IFXMIPS_DMA_RX)
enable_ch_irq(pCh);
local_irq_restore(flag);
}
@ -140,8 +140,8 @@ close_chan(_dma_channel_info *pCh)
int chan_no = (int) (pCh - dma_chan);
local_irq_save(flag);
writel(chan_no, DANUBE_DMA_CS);
writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
writel(chan_no, IFXMIPS_DMA_CS);
writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
disable_ch_irq(pCh);
local_irq_restore(flag);
}
@ -151,8 +151,8 @@ reset_chan (_dma_channel_info *pCh)
{
int chan_no = (int) (pCh - dma_chan);
writel(chan_no, DANUBE_DMA_CS);
writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
writel(chan_no, IFXMIPS_DMA_CS);
writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
}
void
@ -176,10 +176,10 @@ rx_chan_intr_handler (int chan_no)
pCh->weight--;
} else {
local_irq_save(flag);
tmp = readl(DANUBE_DMA_CS);
writel(chan_no, DANUBE_DMA_CS);
writel(readl(DANUBE_DMA_CIS) | 0x7e, DANUBE_DMA_CIS);
writel(tmp, DANUBE_DMA_CS);
tmp = readl(IFXMIPS_DMA_CS);
writel(chan_no, IFXMIPS_DMA_CS);
writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
writel(tmp, IFXMIPS_DMA_CS);
g_danube_dma_int_status &= ~(1 << chan_no);
local_irq_restore(flag);
enable_danube_irq(dma_chan[chan_no].irq);
@ -195,10 +195,10 @@ tx_chan_intr_handler (int chan_no)
int flag;
local_irq_save(flag);
tmp = readl(DANUBE_DMA_CS);
writel(chan_no, DANUBE_DMA_CS);
writel(readl(DANUBE_DMA_CIS) | 0x7e, DANUBE_DMA_CIS);
writel(tmp, DANUBE_DMA_CS);
tmp = readl(IFXMIPS_DMA_CS);
writel(chan_no, IFXMIPS_DMA_CS);
writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
writel(tmp, IFXMIPS_DMA_CS);
g_danube_dma_int_status &= ~(1 << chan_no);
local_irq_restore(flag);
pDev->current_tx_chan = pCh->rel_chan_no;
@ -238,7 +238,7 @@ do_dma_tasklet (unsigned long unused)
if (chan_no >= 0)
{
if (chan_map[chan_no].dir == DANUBE_DMA_RX)
if (chan_map[chan_no].dir == IFXMIPS_DMA_RX)
rx_chan_intr_handler(chan_no);
else
tx_chan_intr_handler(chan_no);
@ -272,10 +272,10 @@ dma_interrupt (int irq, void *dev_id)
if (chan_no < 0 || chan_no > 19)
BUG();
tmp = readl(DANUBE_DMA_IRNEN);
writel(0, DANUBE_DMA_IRNEN);
tmp = readl(IFXMIPS_DMA_IRNEN);
writel(0, IFXMIPS_DMA_IRNEN);
g_danube_dma_int_status |= 1 << chan_no;
writel(tmp, DANUBE_DMA_IRNEN);
writel(tmp, IFXMIPS_DMA_IRNEN);
mask_and_ack_danube_irq(irq);
if (!g_danube_dma_in_process)
@ -328,7 +328,7 @@ dma_device_register(_dma_device_info *dev)
for (i = 0; i < dev->max_tx_chan_num; i++)
{
pCh = dev->tx_chan[i];
if (pCh->control == DANUBE_DMA_CH_ON)
if (pCh->control == IFXMIPS_DMA_CH_ON)
{
chan_no = (int)(pCh - dma_chan);
for (j = 0; j < pCh->desc_len; j++)
@ -337,16 +337,16 @@ dma_device_register(_dma_device_info *dev)
memset(tx_desc_p, 0, sizeof(struct tx_desc));
}
local_irq_save(flag);
writel(chan_no, DANUBE_DMA_CS);
writel(chan_no, IFXMIPS_DMA_CS);
/*check if the descriptor length is changed */
if (readl(DANUBE_DMA_CDLEN) != pCh->desc_len)
writel(pCh->desc_len, DANUBE_DMA_CDLEN);
if (readl(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
writel(pCh->desc_len, IFXMIPS_DMA_CDLEN);
writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
while (readl(DANUBE_DMA_CCTRL) & 2){};
writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
writel(0x30100, DANUBE_DMA_CCTRL); /*reset and enable channel,enable channel later */
writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
while (readl(IFXMIPS_DMA_CCTRL) & 2){};
writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
writel(0x30100, IFXMIPS_DMA_CCTRL); /*reset and enable channel,enable channel later */
local_irq_restore(flag);
}
}
@ -354,7 +354,7 @@ dma_device_register(_dma_device_info *dev)
for (i = 0; i < dev->max_rx_chan_num; i++)
{
pCh = dev->rx_chan[i];
if (pCh->control == DANUBE_DMA_CH_ON)
if (pCh->control == IFXMIPS_DMA_CH_ON)
{
chan_no = (int)(pCh - dma_chan);
@ -376,16 +376,16 @@ dma_device_register(_dma_device_info *dev)
}
local_irq_save(flag);
writel(chan_no, DANUBE_DMA_CS);
writel(chan_no, IFXMIPS_DMA_CS);
/*check if the descriptor length is changed */
if (readl(DANUBE_DMA_CDLEN) != pCh->desc_len)
writel(pCh->desc_len, DANUBE_DMA_CDLEN);
writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
while (readl(DANUBE_DMA_CCTRL) & 2){};
writel(0x0a, DANUBE_DMA_CIE); /*fix me, should enable all the interrupts here? */
writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
writel(0x30000, DANUBE_DMA_CCTRL);
if (readl(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
writel(pCh->desc_len, IFXMIPS_DMA_CDLEN);
writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
while (readl(IFXMIPS_DMA_CCTRL) & 2){};
writel(0x0a, IFXMIPS_DMA_CIE); /*fix me, should enable all the interrupts here? */
writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
writel(0x30000, IFXMIPS_DMA_CCTRL);
local_irq_restore(flag);
enable_danube_irq(dma_chan[chan_no].irq);
}
@ -405,18 +405,18 @@ dma_device_unregister (_dma_device_info *dev)
for (i = 0; i < dev->max_tx_chan_num; i++)
{
pCh = dev->tx_chan[i];
if (pCh->control == DANUBE_DMA_CH_ON)
if (pCh->control == IFXMIPS_DMA_CH_ON)
{
chan_no = (int)(dev->tx_chan[i] - dma_chan);
local_irq_save (flag);
writel(chan_no, DANUBE_DMA_CS);
writel(chan_no, IFXMIPS_DMA_CS);
pCh->curr_desc = 0;
pCh->prev_desc = 0;
pCh->control = DANUBE_DMA_CH_OFF;
writel(0, DANUBE_DMA_CIE); /*fix me, should disable all the interrupts here? */
writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN); /*disable interrupts */
writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
while (readl(DANUBE_DMA_CCTRL) & 1) {};
pCh->control = IFXMIPS_DMA_CH_OFF;
writel(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */
writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */
writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
while (readl(IFXMIPS_DMA_CCTRL) & 1) {};
local_irq_restore (flag);
for (j = 0; j < pCh->desc_len; j++)
@ -444,13 +444,13 @@ dma_device_unregister (_dma_device_info *dev)
g_danube_dma_int_status &= ~(1 << chan_no);
pCh->curr_desc = 0;
pCh->prev_desc = 0;
pCh->control = DANUBE_DMA_CH_OFF;
pCh->control = IFXMIPS_DMA_CH_OFF;
writel(chan_no, DANUBE_DMA_CS);
writel(0, DANUBE_DMA_CIE); /*fix me, should disable all the interrupts here? */
writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN); /*disable interrupts */
writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
while (readl(DANUBE_DMA_CCTRL) & 1) {};
writel(chan_no, IFXMIPS_DMA_CS);
writel(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */
writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */
writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
while (readl(IFXMIPS_DMA_CCTRL) & 1) {};
local_irq_restore (flag);
for (j = 0; j < pCh->desc_len; j++)
@ -577,8 +577,8 @@ dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void *
dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
}
writel(chan_no, DANUBE_DMA_CS);
tmp = readl(DANUBE_DMA_CCTRL);
writel(chan_no, IFXMIPS_DMA_CS);
tmp = readl(IFXMIPS_DMA_CCTRL);
if (!(tmp & 1))
pCh->open (pCh);
@ -625,14 +625,14 @@ map_dma_chan(_dma_chan_map *map)
dma_devs[i].rx_burst_len = 4;
if (i == 0)
{
writel(0, DANUBE_DMA_PS);
writel(readl(DANUBE_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), DANUBE_DMA_PCTRL); /*enable dma drop */
writel(0, IFXMIPS_DMA_PS);
writel(readl(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL); /*enable dma drop */
}
if (i == 1)
{
writel(1, DANUBE_DMA_PS);
writel(0x14, DANUBE_DMA_PCTRL); /*deu port setting */
writel(1, IFXMIPS_DMA_PS);
writel(0x14, IFXMIPS_DMA_PCTRL); /*deu port setting */
}
for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++)
@ -644,8 +644,8 @@ map_dma_chan(_dma_chan_map *map)
dma_chan[j].enable_irq = &enable_ch_irq;
dma_chan[j].disable_irq = &disable_ch_irq;
dma_chan[j].rel_chan_no = map[j].rel_chan_no;
dma_chan[j].control = DANUBE_DMA_CH_OFF;
dma_chan[j].default_weight = DANUBE_DMA_CH_DEFAULT_WEIGHT;
dma_chan[j].control = IFXMIPS_DMA_CH_OFF;
dma_chan[j].default_weight = IFXMIPS_DMA_CH_DEFAULT_WEIGHT;
dma_chan[j].weight = dma_chan[j].default_weight;
dma_chan[j].curr_desc = 0;
dma_chan[j].prev_desc = 0;
@ -655,16 +655,16 @@ map_dma_chan(_dma_chan_map *map)
{
if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0)
{
if (map[j].dir == DANUBE_DMA_RX)
if (map[j].dir == IFXMIPS_DMA_RX)
{
dma_chan[j].dir = DANUBE_DMA_RX;
dma_chan[j].dir = IFXMIPS_DMA_RX;
dma_devs[i].max_rx_chan_num++;
dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
dma_chan[j].dma_dev = (void*)&dma_devs[i];
} else if(map[j].dir == DANUBE_DMA_TX)
} else if(map[j].dir == IFXMIPS_DMA_TX)
{ /*TX direction */
dma_chan[j].dir = DANUBE_DMA_TX;
dma_chan[j].dir = IFXMIPS_DMA_TX;
dma_devs[i].max_tx_chan_num++;
dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
@ -685,20 +685,20 @@ dma_chip_init(void)
int i;
// enable DMA from PMU
danube_pmu_enable(DANUBE_PMU_PWDCR_DMA);
danube_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
// reset DMA
writel(readl(DANUBE_DMA_CTRL) | 1, DANUBE_DMA_CTRL);
writel(readl(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
// diable all interrupts
writel(0, DANUBE_DMA_IRNEN);
writel(0, IFXMIPS_DMA_IRNEN);
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
{
writel(i, DANUBE_DMA_CS);
writel(0x2, DANUBE_DMA_CCTRL);
writel(0x80000040, DANUBE_DMA_CPOLL);
writel(readl(DANUBE_DMA_CCTRL) & ~0x1, DANUBE_DMA_CCTRL);
writel(i, IFXMIPS_DMA_CS);
writel(0x2, IFXMIPS_DMA_CCTRL);
writel(0x80000040, IFXMIPS_DMA_CPOLL);
writel(readl(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL);
}
}
@ -724,13 +724,13 @@ danube_dma_init (void)
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
{
dma_chan[i].desc_base = (u32)g_desc_list + i * DANUBE_DMA_DESCRIPTOR_OFFSET * 8;
dma_chan[i].desc_base = (u32)g_desc_list + i * IFXMIPS_DMA_DESCRIPTOR_OFFSET * 8;
dma_chan[i].curr_desc = 0;
dma_chan[i].desc_len = DANUBE_DMA_DESCRIPTOR_OFFSET;
dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET;
writel(i, DANUBE_DMA_CS);
writel((u32)CPHYSADDR(dma_chan[i].desc_base), DANUBE_DMA_CDBA);
writel(dma_chan[i].desc_len, DANUBE_DMA_CDLEN);
writel(i, IFXMIPS_DMA_CS);
writel((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA);
writel(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN);
}
return 0;

24
target/linux/ifxmips/files/arch/mips/danube/interrupt.c
View File

@ -42,7 +42,7 @@ void
disable_danube_irq (unsigned int irq_nr)
{
int i;
u32 *danube_ier = DANUBE_ICU_IM0_IER;
u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
@ -51,7 +51,7 @@ disable_danube_irq (unsigned int irq_nr)
writel(readl(danube_ier) & ~(1 << irq_nr ), danube_ier);
return;
}
danube_ier += DANUBE_ICU_OFFSET;
danube_ier += IFXMIPS_ICU_OFFSET;
irq_nr -= INT_NUM_IM_OFFSET;
}
}
@ -61,8 +61,8 @@ void
mask_and_ack_danube_irq (unsigned int irq_nr)
{
int i;
u32 *danube_ier = DANUBE_ICU_IM0_IER;
u32 *danube_isr = DANUBE_ICU_IM0_ISR;
u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
u32 *danube_isr = IFXMIPS_ICU_IM0_ISR;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
@ -73,8 +73,8 @@ mask_and_ack_danube_irq (unsigned int irq_nr)
writel((1 << irq_nr ), danube_isr);
return;
}
danube_ier += DANUBE_ICU_OFFSET;
danube_isr += DANUBE_ICU_OFFSET;
danube_ier += IFXMIPS_ICU_OFFSET;
danube_isr += IFXMIPS_ICU_OFFSET;
irq_nr -= INT_NUM_IM_OFFSET;
}
}
@ -84,7 +84,7 @@ void
enable_danube_irq (unsigned int irq_nr)
{
int i;
u32 *danube_ier = DANUBE_ICU_IM0_IER;
u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
@ -94,7 +94,7 @@ enable_danube_irq (unsigned int irq_nr)
writel(readl(danube_ier) | (1 << irq_nr ), danube_ier);
return;
}
danube_ier += DANUBE_ICU_OFFSET;
danube_ier += IFXMIPS_ICU_OFFSET;
irq_nr -= INT_NUM_IM_OFFSET;
}
}
@ -115,7 +115,7 @@ end_danube_irq (unsigned int irq)
}
static struct hw_interrupt_type danube_irq_type = {
"DANUBE",
"IFXMIPS",
.startup = startup_danube_irq,
.enable = enable_danube_irq,
.disable = disable_danube_irq,
@ -145,7 +145,7 @@ danube_hw_irqdispatch (int module)
{
u32 irq;
irq = readl(DANUBE_ICU_IM0_IOSR + (module * DANUBE_ICU_OFFSET));
irq = readl(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
if (irq == 0)
return;
@ -153,7 +153,7 @@ danube_hw_irqdispatch (int module)
do_IRQ ((int) irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
if ((irq == 22) && (module == 0)){
writel(readl(DANUBE_EBU_PCC_ISTAT) | 0x10, DANUBE_EBU_PCC_ISTAT);
writel(readl(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT);
}
}
@ -195,7 +195,7 @@ arch_init_irq(void)
for (i = 0; i < 5; i++)
{
writel(0, DANUBE_ICU_IM0_IER + (i * DANUBE_ICU_OFFSET));
writel(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
}
mips_cpu_irq_init();

78
target/linux/ifxmips/files/arch/mips/danube/pci.c
View File

@ -9,14 +9,14 @@
#include <asm/addrspace.h>
#include <linux/vmalloc.h>
#define DANUBE_PCI_MEM_BASE 0x18000000
#define DANUBE_PCI_MEM_SIZE 0x02000000
#define DANUBE_PCI_IO_BASE 0x1AE00000
#define DANUBE_PCI_IO_SIZE 0x00200000
#define IFXMIPS_PCI_MEM_BASE 0x18000000
#define IFXMIPS_PCI_MEM_SIZE 0x02000000
#define IFXMIPS_PCI_IO_BASE 0x1AE00000
#define IFXMIPS_PCI_IO_SIZE 0x00200000
#define DANUBE_PCI_CFG_BUSNUM_SHF 16
#define DANUBE_PCI_CFG_DEVNUM_SHF 11
#define DANUBE_PCI_CFG_FUNNUM_SHF 8
#define IFXMIPS_PCI_CFG_BUSNUM_SHF 16
#define IFXMIPS_PCI_CFG_DEVNUM_SHF 11
#define IFXMIPS_PCI_CFG_FUNNUM_SHF 8
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
@ -31,15 +31,15 @@ struct pci_ops danube_pci_ops = {
static struct resource pci_io_resource = {
.name = "io pci IO space",
.start = DANUBE_PCI_IO_BASE,
.end = DANUBE_PCI_IO_BASE + DANUBE_PCI_IO_SIZE - 1,
.start = IFXMIPS_PCI_IO_BASE,
.end = IFXMIPS_PCI_IO_BASE + IFXMIPS_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource pci_mem_resource = {
.name = "ext pci memory space",
.start = DANUBE_PCI_MEM_BASE,
.end = DANUBE_PCI_MEM_BASE + DANUBE_PCI_MEM_SIZE - 1,
.start = IFXMIPS_PCI_MEM_BASE,
.end = IFXMIPS_PCI_MEM_BASE + IFXMIPS_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
@ -71,32 +71,32 @@ danube_pci_config_access(unsigned char access_type,
local_irq_save(flags);
cfg_base = danube_pci_mapped_cfg;
cfg_base |= (bus->number << DANUBE_PCI_CFG_BUSNUM_SHF) | (devfn <<
DANUBE_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
cfg_base |= (bus->number << IFXMIPS_PCI_CFG_BUSNUM_SHF) | (devfn <<
IFXMIPS_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
/* Perform access */
if (access_type == PCI_ACCESS_WRITE)
{
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
writel(swab32(*data), ((u32*)cfg_base));
#else
writel(*data, ((u32*)cfg_base));
#endif
} else {
*data = readl(((u32*)(cfg_base)));
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
*data = swab32(*data);
#endif
}
wmb();
/* clean possible Master abort */
cfg_base = (danube_pci_mapped_cfg | (0x0 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
cfg_base = (danube_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
temp = readl(((u32*)(cfg_base)));
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
temp = swab32 (temp);
#endif
cfg_base = (danube_pci_mapped_cfg | (0x68 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
cfg_base = (danube_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
writel(temp, ((u32*)cfg_base));
local_irq_restore(flags);
@ -163,8 +163,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev){
case 1:
//falling edge level triggered:0x4, low level:0xc, rising edge:0x2
printk("%s:%s[%d] %08X \n", __FILE__, __func__, __LINE__, dev->irq);
writel(readl(DANUBE_EBU_PCC_CON) | 0xc, DANUBE_EBU_PCC_CON);
writel(readl(DANUBE_EBU_PCC_IEN) | 0x10, DANUBE_EBU_PCC_IEN);
writel(readl(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
writel(readl(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
break;
case 2:
case 3:
@ -182,31 +182,31 @@ static void __init danube_pci_startup (void){
/*initialize the first PCI device--danube itself */
u32 temp_buffer;
/*TODO: trigger reset */
writel(readl(DANUBE_CGU_IFCCR) & ~0xf00000, DANUBE_CGU_IFCCR);
writel(readl(DANUBE_CGU_IFCCR) | 0x800000, DANUBE_CGU_IFCCR);
writel(readl(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
writel(readl(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
/* PCIS of IF_CLK of CGU : 1 =>PCI Clock output
0 =>clock input
PADsel of PCI_CR of CGU : 1 =>From CGU
: 0 =>From pad
*/
writel(readl(DANUBE_CGU_IFCCR) | (1 << 16), DANUBE_CGU_IFCCR);
writel((1 << 31) | (1 << 30), DANUBE_CGU_PCICR);
writel(readl(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
writel((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
/* prepare GPIO */
/* PCI_RST: P1.5 ALT 01 */
//pliu20060613: start
writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
writel(readl(DANUBE_GPIO_P1_OD) | (1 << 5), DANUBE_GPIO_P1_OD);
writel(readl(DANUBE_GPIO_P1_DIR) | (1 << 5), DANUBE_GPIO_P1_DIR);
writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL1);
writel(readl(DANUBE_GPIO_P1_ALTSEL0) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL0);
writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
writel(readl(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
writel(readl(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
//pliu20060613: end
/* PCI_REQ1: P1.13 ALT 01 */
/* PCI_GNT1: P1.14 ALT 01 */
writel(readl(DANUBE_GPIO_P1_DIR) & ~0x2000, DANUBE_GPIO_P1_DIR);
writel(readl(DANUBE_GPIO_P1_DIR) | 0x4000, DANUBE_GPIO_P1_DIR);
writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~0x6000, DANUBE_GPIO_P1_ALTSEL1);
writel(readl(DANUBE_GPIO_P1_ALTSEL0) | 0x6000, DANUBE_GPIO_P1_ALTSEL0);
writel(readl(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
writel(readl(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
/* PCI_REQ2: P1.15 ALT 10 */
/* PCI_GNT2: P1.7 ALT 10 */
@ -260,9 +260,9 @@ static void __init danube_pci_startup (void){
writel(0x0e000008, PCI_CR_BAR11MASK);
writel(0, PCI_CR_PCI_ADDR_MAP11);
writel(0, PCI_CS_BASE_ADDR1);
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
/* both TX and RX endian swap are enabled */
DANUBE_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
IFXMIPS_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
wmb ();
#endif
/*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
@ -273,10 +273,10 @@ static void __init danube_pci_startup (void){
writel(readl(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
wmb();
writel(readl(DANUBE_GPIO_P1_OUT) & ~(1 << 5), DANUBE_GPIO_P1_OUT);
writel(readl(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
wmb();
mdelay (1);
writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
}
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
@ -303,11 +303,11 @@ int pcibios_init(void){
danube_pci_startup ();
// DANUBE_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
// IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
danube_pci_mapped_cfg = ioremap_nocache(0x17000000, 0x800 * 16);
printk("Danube PCI mapped to 0x%08X\n", (unsigned long)danube_pci_mapped_cfg);
danube_pci_controller.io_map_base = (unsigned long)ioremap(DANUBE_PCI_IO_BASE, DANUBE_PCI_IO_SIZE - 1);
danube_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
printk("Danube PCI I/O mapped to 0x%08X\n", (unsigned long)danube_pci_controller.io_map_base);

6
target/linux/ifxmips/files/arch/mips/danube/pmu.c
View File

@ -29,8 +29,8 @@ danube_pmu_enable (unsigned int module)
{
int err = 1000000;
writel(readl(DANUBE_PMU_PWDCR) & ~module, DANUBE_PMU_PWDCR);
while (--err && (readl(DANUBE_PMU_PWDSR) & module)) {}
writel(readl(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR);
while (--err && (readl(IFXMIPS_PMU_PWDSR) & module)) {}
if (!err)
panic("activating PMU module failed!");
@ -40,6 +40,6 @@ EXPORT_SYMBOL(danube_pmu_enable);
void
danube_pmu_disable (unsigned int module)
{
writel(readl(DANUBE_PMU_PWDCR) | module, DANUBE_PMU_PWDCR);
writel(readl(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
}
EXPORT_SYMBOL(danube_pmu_disable);

10
target/linux/ifxmips/files/arch/mips/danube/prom.c
View File

@ -45,11 +45,11 @@ get_system_type (void)
void
prom_putchar (char c)
{
while ((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
while ((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
if (c == '\n')
writel('\r', DANUBE_ASC1_TBUF);
writel(c, DANUBE_ASC1_TBUF);
writel('\r', IFXMIPS_ASC1_TBUF);
writel(c, IFXMIPS_ASC1_TBUF);
}
void
@ -73,8 +73,8 @@ prom_printf (const char * fmt, ...)
void __init
prom_init(void)
{
mips_machgroup = MACH_GROUP_DANUBE;
mips_machtype = MACH_INFINEON_DANUBE;
mips_machgroup = MACH_GROUP_IFXMIPS;
mips_machtype = MACH_INFINEON_IFXMIPS;
strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
add_memory_region (0x00000000, 0x2000000, BOOT_MEM_RAM);

2
target/linux/ifxmips/files/arch/mips/danube/reset.c
View File

@ -37,7 +37,7 @@ danube_machine_restart (char *command)
printk (KERN_NOTICE "System restart\n");
local_irq_disable ();
writel(readl(DANUBE_RCU_REQ) | DANUBE_RST_ALL, DANUBE_RCU_REQ);
writel(readl(IFXMIPS_RCU_REQ) | IFXMIPS_RST_ALL, IFXMIPS_RCU_REQ);
for (;;);
}

22
target/linux/ifxmips/files/arch/mips/danube/setup.c
View File

@ -49,7 +49,7 @@ __init bus_error_init (void)
unsigned int
danube_get_ddr_hz (void)
{
switch (readl(DANUBE_CGU_SYS) & 0x3)
switch (readl(IFXMIPS_CGU_SYS) & 0x3)
{
case 0:
return CLOCK_167M;
@ -66,7 +66,7 @@ unsigned int
danube_get_cpu_hz (void)
{
unsigned int ddr_clock = danube_get_ddr_hz();
switch (readl(DANUBE_CGU_SYS) & 0xc)
switch (readl(IFXMIPS_CGU_SYS) & 0xc)
{
case 0:
return CLOCK_333M;
@ -81,7 +81,7 @@ unsigned int
danube_get_fpi_hz (void)
{
unsigned int ddr_clock = danube_get_ddr_hz();
if (readl(DANUBE_CGU_SYS) & 0x40)
if (readl(IFXMIPS_CGU_SYS) & 0x40)
{
return ddr_clock >> 1;
}
@ -92,7 +92,7 @@ EXPORT_SYMBOL(danube_get_fpi_hz);
unsigned int
danube_get_cpu_ver (void)
{
return readl(DANUBE_MCD_CHIPID) & 0xFFFFF000;
return readl(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
}
EXPORT_SYMBOL(danube_get_cpu_ver);
@ -118,7 +118,7 @@ danube_be_handler(struct pt_regs *regs, int is_fixup)
static irqreturn_t
danube_timer6_interrupt(int irq, void *dev_id)
{
timer_interrupt(DANUBE_TIMER6_INT, NULL);
timer_interrupt(IFXMIPS_TIMER6_INT, NULL);
return IRQ_HANDLED;
}
@ -139,18 +139,18 @@ plat_timer_setup (struct irqaction *irq)
r4k_cur = (read_c0_count() + r4k_offset);
write_c0_compare(r4k_cur);
danube_pmu_enable(DANUBE_PMU_PWDCR_GPT | DANUBE_PMU_PWDCR_FPI);
danube_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
writel(0x100, DANUBE_GPTU_GPT_CLC);
writel(0x100, IFXMIPS_GPTU_GPT_CLC);
writel(0xffff, DANUBE_GPTU_GPT_CAPREL);
writel(0x80C0, DANUBE_GPTU_GPT_T6CON);
writel(0xffff, IFXMIPS_GPTU_GPT_CAPREL);
writel(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
retval = setup_irq(DANUBE_TIMER6_INT, &hrt_irqaction);
retval = setup_irq(IFXMIPS_TIMER6_INT, &hrt_irqaction);
if (retval)
{
prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n", DANUBE_TIMER6_INT);
prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n", IFXMIPS_TIMER6_INT);
}
}

130
target/linux/ifxmips/files/drivers/char/danube_gpio.c
View File

@ -38,12 +38,12 @@ static unsigned int danube_gpio_major = 0;
static struct semaphore port_sem;
/* TODO do we really need this ? return in a define is forbidden by coding style */
#define DANUBE_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
#define IFXMIPS_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
int
danube_port_reserve_pin (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__);
return 0;
@ -53,7 +53,7 @@ EXPORT_SYMBOL(danube_port_reserve_pin);
int
danube_port_free_pin (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__);
return 0;
@ -63,8 +63,8 @@ EXPORT_SYMBOL(danube_port_free_pin);
int
danube_port_set_open_drain (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_OD + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_OD);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_OD + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_OD);
return 0;
}
@ -73,8 +73,8 @@ EXPORT_SYMBOL(danube_port_set_open_drain);
int
danube_port_clear_open_drain (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_OD + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_OD);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_OD + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_OD);
return 0;
}
@ -83,8 +83,8 @@ EXPORT_SYMBOL(danube_port_clear_open_drain);
int
danube_port_set_pudsel (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_PUDSEL + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_PUDSEL);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_PUDSEL + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_PUDSEL);
return 0;
}
@ -93,8 +93,8 @@ EXPORT_SYMBOL(danube_port_set_pudsel);
int
danube_port_clear_pudsel (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_PUDSEL + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_PUDSEL);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_PUDSEL + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDSEL);
return 0;
}
@ -103,8 +103,8 @@ EXPORT_SYMBOL(danube_port_clear_pudsel);
int
danube_port_set_puden (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_PUDEN + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_PUDEN);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_PUDEN + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_PUDEN);
return 0;
}
@ -113,8 +113,8 @@ EXPORT_SYMBOL(danube_port_set_puden);
int
danube_port_clear_puden (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_PUDEN + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_PUDEN);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_PUDEN + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDEN);
return 0;
}
@ -123,8 +123,8 @@ EXPORT_SYMBOL(danube_port_clear_puden);
int
danube_port_set_stoff (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_STOFF + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_STOFF);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_STOFF + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_STOFF);
return 0;
}
@ -133,8 +133,8 @@ EXPORT_SYMBOL(danube_port_set_stoff);
int
danube_port_clear_stoff (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_STOFF + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_STOFF);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_STOFF + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_STOFF);
return 0;
}
@ -143,8 +143,8 @@ EXPORT_SYMBOL(danube_port_clear_stoff);
int
danube_port_set_dir_out (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_DIR + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_DIR);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_DIR + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_DIR);
return 0;
}
@ -153,8 +153,8 @@ EXPORT_SYMBOL(danube_port_set_dir_out);
int
danube_port_set_dir_in (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_DIR + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_DIR);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_DIR + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_DIR);
return 0;
}
@ -163,8 +163,8 @@ EXPORT_SYMBOL(danube_port_set_dir_in);
int
danube_port_set_output (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_OUT + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_OUT);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_OUT + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_OUT);
return 0;
}
@ -173,8 +173,8 @@ EXPORT_SYMBOL(danube_port_set_output);
int
danube_port_clear_output (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_OUT + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_OUT);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_OUT + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_OUT);
return 0;
}
@ -183,9 +183,9 @@ EXPORT_SYMBOL(danube_port_clear_output);
int
danube_port_get_input (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
IFXMIPS_GPIO_SANITY;
if (readl(DANUBE_GPIO_P0_IN + (port * 0x30)) & (1 << pin))
if (readl(IFXMIPS_GPIO_P0_IN + (port * 0x30)) & (1 << pin))
return 0;
else
return 1;
@ -195,8 +195,8 @@ EXPORT_SYMBOL(danube_port_get_input);
int
danube_port_set_altsel0 (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_ALTSEL0 + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_ALTSEL0);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL0);
return 0;
}
@ -205,8 +205,8 @@ EXPORT_SYMBOL(danube_port_set_altsel0);
int
danube_port_clear_altsel0 (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_ALTSEL0 + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_ALTSEL0);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL0);
return 0;
}
@ -215,8 +215,8 @@ EXPORT_SYMBOL(danube_port_clear_altsel0);
int
danube_port_set_altsel1 (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_ALTSEL1 + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_ALTSEL1);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL1);
return 0;
}
@ -225,8 +225,8 @@ EXPORT_SYMBOL(danube_port_set_altsel1);
int
danube_port_clear_altsel1 (unsigned int port, unsigned int pin)
{
DANUBE_GPIO_SANITY;
writel(readl(DANUBE_GPIO_P0_ALTSEL1 + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_ALTSEL1);
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL1);
return 0;
}
@ -264,24 +264,24 @@ danube_port_read_procmem (char *buf, char **start, off_t offset, int count,
len += sprintf (buf + len,
"----------------------------------------\n");
len += danube_port_read_procmem_helper("P0-OUT", DANUBE_GPIO_P0_OUT, &buf[len]);
len += danube_port_read_procmem_helper("P1-OUT", DANUBE_GPIO_P1_OUT, &buf[len]);
len += danube_port_read_procmem_helper("P0-IN ", DANUBE_GPIO_P0_IN, &buf[len]);
len += danube_port_read_procmem_helper("P1-IN ", DANUBE_GPIO_P1_IN, &buf[len]);
len += danube_port_read_procmem_helper("P0-DIR", DANUBE_GPIO_P0_DIR, &buf[len]);
len += danube_port_read_procmem_helper("P1-DIR", DANUBE_GPIO_P1_DIR, &buf[len]);
len += danube_port_read_procmem_helper("P0-STO ", DANUBE_GPIO_P0_STOFF, &buf[len]);
len += danube_port_read_procmem_helper("P1-STO ", DANUBE_GPIO_P1_STOFF, &buf[len]);
len += danube_port_read_procmem_helper("P0-PUDE", DANUBE_GPIO_P0_PUDEN, &buf[len]);
len += danube_port_read_procmem_helper("P1-PUDE", DANUBE_GPIO_P1_PUDEN, &buf[len]);
len += danube_port_read_procmem_helper("P0-OD ", DANUBE_GPIO_P0_OD, &buf[len]);
len += danube_port_read_procmem_helper("P1-OD ", DANUBE_GPIO_P1_OD, &buf[len]);
len += danube_port_read_procmem_helper("P0-PUDS", DANUBE_GPIO_P0_PUDSEL, &buf[len]);
len += danube_port_read_procmem_helper("P1-PUDS", DANUBE_GPIO_P1_PUDSEL, &buf[len]);
len += danube_port_read_procmem_helper("P0-ALT0", DANUBE_GPIO_P0_ALTSEL0, &buf[len]);
len += danube_port_read_procmem_helper("P1-ALT0", DANUBE_GPIO_P1_ALTSEL0, &buf[len]);
len += danube_port_read_procmem_helper("P0-ALT1", DANUBE_GPIO_P0_ALTSEL1, &buf[len]);
len += danube_port_read_procmem_helper("P1-ALT1", DANUBE_GPIO_P1_ALTSEL1, &buf[len]);
len += danube_port_read_procmem_helper("P0-OUT", IFXMIPS_GPIO_P0_OUT, &buf[len]);
len += danube_port_read_procmem_helper("P1-OUT", IFXMIPS_GPIO_P1_OUT, &buf[len]);
len += danube_port_read_procmem_helper("P0-IN ", IFXMIPS_GPIO_P0_IN, &buf[len]);
len += danube_port_read_procmem_helper("P1-IN ", IFXMIPS_GPIO_P1_IN, &buf[len]);
len += danube_port_read_procmem_helper("P0-DIR", IFXMIPS_GPIO_P0_DIR, &buf[len]);
len += danube_port_read_procmem_helper("P1-DIR", IFXMIPS_GPIO_P1_DIR, &buf[len]);
len += danube_port_read_procmem_helper("P0-STO ", IFXMIPS_GPIO_P0_STOFF, &buf[len]);
len += danube_port_read_procmem_helper("P1-STO ", IFXMIPS_GPIO_P1_STOFF, &buf[len]);
len += danube_port_read_procmem_helper("P0-PUDE", IFXMIPS_GPIO_P0_PUDEN, &buf[len]);
len += danube_port_read_procmem_helper("P1-PUDE", IFXMIPS_GPIO_P1_PUDEN, &buf[len]);
len += danube_port_read_procmem_helper("P0-OD ", IFXMIPS_GPIO_P0_OD, &buf[len]);
len += danube_port_read_procmem_helper("P1-OD ", IFXMIPS_GPIO_P1_OD, &buf[len]);
len += danube_port_read_procmem_helper("P0-PUDS", IFXMIPS_GPIO_P0_PUDSEL, &buf[len]);
len += danube_port_read_procmem_helper("P1-PUDS", IFXMIPS_GPIO_P1_PUDSEL, &buf[len]);
len += danube_port_read_procmem_helper("P0-ALT0", IFXMIPS_GPIO_P0_ALTSEL0, &buf[len]);
len += danube_port_read_procmem_helper("P1-ALT0", IFXMIPS_GPIO_P1_ALTSEL0, &buf[len]);
len += danube_port_read_procmem_helper("P0-ALT1", IFXMIPS_GPIO_P0_ALTSEL1, &buf[len]);
len += danube_port_read_procmem_helper("P1-ALT1", IFXMIPS_GPIO_P1_ALTSEL1, &buf[len]);
len = len + sprintf (buf + len, "\n\n");
*eof = 1;
@ -308,7 +308,7 @@ danube_port_ioctl (struct inode *inode, struct file *filp,
int ret = 0;
volatile struct danube_port_ioctl_parm parm;
if (_IOC_TYPE (cmd) != DANUBE_PORT_IOC_MAGIC)
if (_IOC_TYPE (cmd) != IFXMIPS_PORT_IOC_MAGIC)
return -EINVAL;
if (_IOC_DIR (cmd) & _IOC_WRITE) {
@ -330,63 +330,63 @@ danube_port_ioctl (struct inode *inode, struct file *filp,
return -EBUSY;
switch (cmd) {
case DANUBE_PORT_IOCOD:
case IFXMIPS_PORT_IOCOD:
if (parm.value == 0x00)
danube_port_clear_open_drain(parm.port, parm.pin);
else
danube_port_set_open_drain(parm.port, parm.pin);
break;
case DANUBE_PORT_IOCPUDSEL:
case IFXMIPS_PORT_IOCPUDSEL:
if (parm.value == 0x00)
danube_port_clear_pudsel(parm.port, parm.pin);
else
danube_port_set_pudsel(parm.port, parm.pin);
break;
case DANUBE_PORT_IOCPUDEN:
case IFXMIPS_PORT_IOCPUDEN:
if (parm.value == 0x00)
danube_port_clear_puden(parm.port, parm.pin);
else
danube_port_set_puden(parm.port, parm.pin);
break;
case DANUBE_PORT_IOCSTOFF:
case IFXMIPS_PORT_IOCSTOFF:
if (parm.value == 0x00)
danube_port_clear_stoff(parm.port, parm.pin);
else
danube_port_set_stoff(parm.port, parm.pin);
break;
case DANUBE_PORT_IOCDIR:
case IFXMIPS_PORT_IOCDIR:
if (parm.value == 0x00)
danube_port_set_dir_in(parm.port, parm.pin);
else
danube_port_set_dir_out(parm.port, parm.pin);
break;
case DANUBE_PORT_IOCOUTPUT:
case IFXMIPS_PORT_IOCOUTPUT:
if (parm.value == 0x00)
danube_port_clear_output(parm.port, parm.pin);
else
danube_port_set_output(parm.port, parm.pin);
break;
case DANUBE_PORT_IOCALTSEL0:
case IFXMIPS_PORT_IOCALTSEL0:
if (parm.value == 0x00)
danube_port_clear_altsel0(parm.port, parm.pin);
else
danube_port_set_altsel0(parm.port, parm.pin);
break;
case DANUBE_PORT_IOCALTSEL1:
case IFXMIPS_PORT_IOCALTSEL1:
if (parm.value == 0x00)
danube_port_clear_altsel1(parm.port, parm.pin);
else
danube_port_set_altsel1(parm.port, parm.pin);
break;
case DANUBE_PORT_IOCINPUT:
case IFXMIPS_PORT_IOCINPUT:
parm.value = danube_port_get_input(parm.port, parm.pin);
copy_to_user((void*)arg, (void*)&parm,
sizeof(struct danube_port_ioctl_parm));

52
target/linux/ifxmips/files/drivers/char/danube_led.c
View File

@ -31,12 +31,12 @@
#include <asm/danube/danube_gpio.h>
#include <asm/danube/danube_pmu.h>
#define DANUBE_LED_CLK_EDGE DANUBE_LED_FALLING
//#define DANUBE_LED_CLK_EDGE DANUBE_LED_RISING
#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_FALLING
//#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_RISING
#define DANUBE_LED_SPEED DANUBE_LED_8HZ
#define IFXMIPS_LED_SPEED IFXMIPS_LED_8HZ
#define DANUBE_LED_GPIO_PORT 0
#define IFXMIPS_LED_GPIO_PORT 0
static int danube_led_major;
@ -44,7 +44,7 @@ void
danube_led_set (unsigned int led)
{
led &= 0xffffff;
writel(readl(DANUBE_LED_CPU0) | led, DANUBE_LED_CPU0);
writel(readl(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0);
}
EXPORT_SYMBOL(danube_led_set);
@ -52,7 +52,7 @@ void
danube_led_clear (unsigned int led)
{
led = ~(led & 0xffffff);
writel(readl(DANUBE_LED_CPU0) & led, DANUBE_LED_CPU0);
writel(readl(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0);
}
EXPORT_SYMBOL(danube_led_clear);
@ -60,7 +60,7 @@ void
danube_led_blink_set (unsigned int led)
{
led &= 0xffffff;
writel(readl(DANUBE_LED_CON0) | led, DANUBE_LED_CON0);
writel(readl(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0);
}
EXPORT_SYMBOL(danube_led_blink_set);
@ -68,7 +68,7 @@ void
danube_led_blink_clear (unsigned int led)
{
led = ~(led & 0xffffff);
writel(readl(DANUBE_LED_CON0) & led, DANUBE_LED_CON0);
writel(readl(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0);
}
EXPORT_SYMBOL(danube_led_blink_clear);
@ -80,10 +80,10 @@ danube_led_setup_gpio (void)
/* we need to setup pins SH,D,ST (4,5,6) */
for (i = 4; i < 7; i++)
{
danube_port_set_altsel0(DANUBE_LED_GPIO_PORT, i);
danube_port_clear_altsel1(DANUBE_LED_GPIO_PORT, i);
danube_port_set_dir_out(DANUBE_LED_GPIO_PORT, i);
danube_port_set_open_drain(DANUBE_LED_GPIO_PORT, i);
danube_port_set_altsel0(IFXMIPS_LED_GPIO_PORT, i);
danube_port_clear_altsel1(IFXMIPS_LED_GPIO_PORT, i);
danube_port_set_dir_out(IFXMIPS_LED_GPIO_PORT, i);
danube_port_set_open_drain(IFXMIPS_LED_GPIO_PORT, i);
}
}
@ -144,32 +144,32 @@ danube_led_init (void)
danube_led_setup_gpio();
writel(0, DANUBE_LED_AR);
writel(0, DANUBE_LED_CPU0);
writel(0, DANUBE_LED_CPU1);
writel(LED_CON0_SWU, DANUBE_LED_CON0);
writel(0, DANUBE_LED_CON1);
writel(0, IFXMIPS_LED_AR);
writel(0, IFXMIPS_LED_CPU0);
writel(0, IFXMIPS_LED_CPU1);
writel(LED_CON0_SWU, IFXMIPS_LED_CON0);
writel(0, IFXMIPS_LED_CON1);
/* setup the clock edge that the shift register is triggered on */
writel(readl(DANUBE_LED_CON0) & ~DANUBE_LED_EDGE_MASK, DANUBE_LED_CON0);
writel(readl(DANUBE_LED_CON0) | DANUBE_LED_CLK_EDGE, DANUBE_LED_CON0);
writel(readl(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK, IFXMIPS_LED_CON0);
writel(readl(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE, IFXMIPS_LED_CON0);
/* per default leds 15-0 are set */
writel(DANUBE_LED_GROUP1 | DANUBE_LED_GROUP0, DANUBE_LED_CON1);
writel(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1);
/* leds are update periodically by the FPID */
writel(readl(DANUBE_LED_CON1) & ~DANUBE_LED_UPD_MASK, DANUBE_LED_CON1);
writel(readl(DANUBE_LED_CON1) | DANUBE_LED_UPD_SRC_FPI, DANUBE_LED_CON1);
writel(readl(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK, IFXMIPS_LED_CON1);
writel(readl(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI, IFXMIPS_LED_CON1);
/* set led update speed */
writel(readl(DANUBE_LED_CON1) & ~DANUBE_LED_MASK, DANUBE_LED_CON1);
writel(readl(DANUBE_LED_CON1) | DANUBE_LED_SPEED, DANUBE_LED_CON1);
writel(readl(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK, IFXMIPS_LED_CON1);
writel(readl(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED, IFXMIPS_LED_CON1);
/* adsl 0 and 1 leds are updated by the arc */
writel(readl(DANUBE_LED_CON0) | DANUBE_LED_ADSL_SRC, DANUBE_LED_CON0);
writel(readl(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC, IFXMIPS_LED_CON0);
/* per default, the leds are turned on */
danube_pmu_enable(DANUBE_PMU_PWDCR_LED);
danube_pmu_enable(IFXMIPS_PMU_PWDCR_LED);
danube_led_major = register_chrdev(0, "danube_led", &danube_led_fops);

26
target/linux/ifxmips/files/drivers/char/danube_ssc.c
View File

@ -872,20 +872,20 @@ ifx_ssc_sethwopts (struct ifx_ssc_port *info)
/* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
/* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
/* Set p0.15 to alternative 01, others to 00 (In/OUT) */
*(DANUBE_GPIO_P0_DIR) = (*DANUBE_GPIO_P0_DIR) | (0xA000);
*(DANUBE_GPIO_P0_ALTSEL0) = (((*DANUBE_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
*(DANUBE_GPIO_P0_ALTSEL1) = (((*DANUBE_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
*(DANUBE_GPIO_P0_OD) = (*DANUBE_GPIO_P0_OD) | 0xA000;
*(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000);
*(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
*(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
*(IFXMIPS_GPIO_P0_OD) = (*IFXMIPS_GPIO_P0_OD) | 0xA000;
/* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
*(DANUBE_GPIO_P1_DIR) = ((*DANUBE_GPIO_P1_DIR) | (0x46)) & (~1);
*(DANUBE_GPIO_P1_ALTSEL0) = ((*DANUBE_GPIO_P1_ALTSEL0) | (0x47));
*(DANUBE_GPIO_P1_ALTSEL1) = (*DANUBE_GPIO_P1_ALTSEL1) & (~0x47);
*(DANUBE_GPIO_P1_OD) = (*DANUBE_GPIO_P1_OD) | 0x0046;
*(IFXMIPS_GPIO_P1_DIR) = ((*IFXMIPS_GPIO_P1_DIR) | (0x46)) & (~1);
*(IFXMIPS_GPIO_P1_ALTSEL0) = ((*IFXMIPS_GPIO_P1_ALTSEL0) | (0x47));
*(IFXMIPS_GPIO_P1_ALTSEL1) = (*IFXMIPS_GPIO_P1_ALTSEL1) & (~0x47);
*(IFXMIPS_GPIO_P1_OD) = (*IFXMIPS_GPIO_P1_OD) | 0x0046;
/*CS3 */
/*TODO: CS4 CS5 CS6 */
*DANUBE_GPIO_P0_OUT = ((*DANUBE_GPIO_P0_OUT) | 0x2000);
*IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000);
local_irq_restore (flags);
@ -1273,10 +1273,10 @@ ifx_ssc_init (void)
info->txbuf = NULL;
/* values specific to SSC1 */
if (i == 0) {
info->mapbase = DANUBE_SSC1_BASE_ADDR;
info->txirq = DANUBE_SSC_TIR;
info->rxirq = DANUBE_SSC_RIR;
info->errirq = DANUBE_SSC_EIR;
info->mapbase = IFXMIPS_SSC1_BASE_ADDR;
info->txirq = IFXMIPS_SSC_TIR;
info->rxirq = IFXMIPS_SSC_RIR;
info->errirq = IFXMIPS_SSC_EIR;
}
WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, info->mapbase + IFX_SSC_CLC);

96
target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c
View File

@ -43,8 +43,8 @@ danube_wdt_enable (unsigned int timeout)
int retval = 0;
/* clock divider & prewarning limit */
wdt_clkdiv = 1 << (7 * DANUBE_BIU_WDT_CR_CLKDIV_GET(readl(DANUBE_BIU_WDT_CR)));
wdt_pwl = 0x8000 >> DANUBE_BIU_WDT_CR_PWL_GET(readl(DANUBE_BIU_WDT_CR));
wdt_clkdiv = 1 << (7 * IFXMIPS_BIU_WDT_CR_CLKDIV_GET(readl(IFXMIPS_BIU_WDT_CR)));
wdt_pwl = 0x8000 >> IFXMIPS_BIU_WDT_CR_PWL_GET(readl(IFXMIPS_BIU_WDT_CR));
//TODO
printk("WARNING FUNCTION CALL MISSING!!!");
@ -65,21 +65,21 @@ danube_wdt_enable (unsigned int timeout)
}
/* Write first part of password access */
writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr = readl(DANUBE_BIU_WDT_CR);
wdt_cr &= (!DANUBE_BIU_WDT_CR_PW_SET(0xff) &
!DANUBE_BIU_WDT_CR_PWL_SET(0x3) &
!DANUBE_BIU_WDT_CR_CLKDIV_SET(0x3) &
!DANUBE_BIU_WDT_CR_RELOAD_SET(0xffff));
wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
wdt_cr &= (!IFXMIPS_BIU_WDT_CR_PW_SET(0xff) &
!IFXMIPS_BIU_WDT_CR_PWL_SET(0x3) &
!IFXMIPS_BIU_WDT_CR_CLKDIV_SET(0x3) &
!IFXMIPS_BIU_WDT_CR_RELOAD_SET(0xffff));
wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) |
DANUBE_BIU_WDT_CR_PWL_SET(DANUBE_BIU_WDT_CR_PWL_GET(readl(DANUBE_BIU_WDT_CR))) |
DANUBE_BIU_WDT_CR_CLKDIV_SET(DANUBE_BIU_WDT_CR_CLKDIV_GET(readl(DANUBE_BIU_WDT_CR))) |
DANUBE_BIU_WDT_CR_RELOAD_SET(wdt_reload) |
DANUBE_BIU_WDT_CR_GEN);
wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) |
IFXMIPS_BIU_WDT_CR_PWL_SET(IFXMIPS_BIU_WDT_CR_PWL_GET(readl(IFXMIPS_BIU_WDT_CR))) |
IFXMIPS_BIU_WDT_CR_CLKDIV_SET(IFXMIPS_BIU_WDT_CR_CLKDIV_GET(readl(IFXMIPS_BIU_WDT_CR))) |
IFXMIPS_BIU_WDT_CR_RELOAD_SET(wdt_reload) |
IFXMIPS_BIU_WDT_CR_GEN);
writel(wdt_cr, DANUBE_BIU_WDT_CR);
writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
printk("watchdog enabled\n");
@ -90,8 +90,8 @@ out:
void
danube_wdt_disable (void)
{
writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2), DANUBE_BIU_WDT_CR);
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2), IFXMIPS_BIU_WDT_CR);
printk("watchdog disabled\n");
}
@ -102,20 +102,20 @@ danube_wdt_enable_feature (int en, int type)
{
unsigned int wdt_cr = 0;
writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr = readl(DANUBE_BIU_WDT_CR);
wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
if (en)
{
wdt_cr &= (~DANUBE_BIU_WDT_CR_PW_SET(0xff));
wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | type);
wdt_cr &= (~IFXMIPS_BIU_WDT_CR_PW_SET(0xff));
wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | type);
} else {
wdt_cr &= (~DANUBE_BIU_WDT_CR_PW_SET(0xff) & ~type);
wdt_cr |= DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2);
wdt_cr &= (~IFXMIPS_BIU_WDT_CR_PW_SET(0xff) & ~type);
wdt_cr |= IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2);
}
writel(wdt_cr, DANUBE_BIU_WDT_CR);
writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
void
@ -123,14 +123,14 @@ danube_wdt_prewarning_limit (int pwl)
{
unsigned int wdt_cr = 0;
wdt_cr = readl(DANUBE_BIU_WDT_CR);
writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr &= 0xf300ffff;
wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | DANUBE_BIU_WDT_CR_PWL_SET(pwl));
wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | IFXMIPS_BIU_WDT_CR_PWL_SET(pwl));
/* Set reload value in second password access */
writel(wdt_cr, DANUBE_BIU_WDT_CR);
writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
void
@ -138,14 +138,14 @@ danube_wdt_set_clkdiv (int clkdiv)
{
unsigned int wdt_cr = 0;
wdt_cr = readl(DANUBE_BIU_WDT_CR);
writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr &= 0xfc00ffff;
wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | DANUBE_BIU_WDT_CR_CLKDIV_SET(clkdiv));
wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | IFXMIPS_BIU_WDT_CR_CLKDIV_SET(clkdiv));
/* Set reload value in second password access */
writel(wdt_cr, DANUBE_BIU_WDT_CR);
writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
static int
@ -156,7 +156,7 @@ danube_wdt_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
static int timeout = -1;
unsigned int user_arg;
if ((cmd != DANUBE_WDT_IOC_STOP) && (cmd != DANUBE_WDT_IOC_PING) && (cmd != DANUBE_WDT_IOC_GET_STATUS))
if ((cmd != IFXMIPS_WDT_IOC_STOP) && (cmd != IFXMIPS_WDT_IOC_PING) && (cmd != IFXMIPS_WDT_IOC_GET_STATUS))
{
if (copy_from_user((void *) &user_arg, (void *) arg, sizeof (int))){
result = -EINVAL;
@ -166,43 +166,43 @@ danube_wdt_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
switch (cmd)
{
case DANUBE_WDT_IOC_START:
case IFXMIPS_WDT_IOC_START:
if ((result = danube_wdt_enable(user_arg)) < 0)
timeout = -1;
else
timeout = user_arg;
break;
case DANUBE_WDT_IOC_STOP:
case IFXMIPS_WDT_IOC_STOP:
printk("disable watch dog timer\n");
danube_wdt_disable();
break;
case DANUBE_WDT_IOC_PING:
case IFXMIPS_WDT_IOC_PING:
if (timeout < 0)
result = -EIO;
else
result = danube_wdt_enable(timeout);
break;
case DANUBE_WDT_IOC_GET_STATUS:
user_arg = readl(DANUBE_BIU_WDT_SR);
case IFXMIPS_WDT_IOC_GET_STATUS:
user_arg = readl(IFXMIPS_BIU_WDT_SR);
copy_to_user((int*)arg, (int*)&user_arg, sizeof(int));
break;
case DANUBE_WDT_IOC_SET_PWL:
case IFXMIPS_WDT_IOC_SET_PWL:
danube_wdt_prewarning_limit(user_arg);
break;
case DANUBE_WDT_IOC_SET_DSEN:
danube_wdt_enable_feature(user_arg, DANUBE_BIU_WDT_CR_DSEN);
case IFXMIPS_WDT_IOC_SET_DSEN:
danube_wdt_enable_feature(user_arg, IFXMIPS_BIU_WDT_CR_DSEN);
break;
case DANUBE_WDT_IOC_SET_LPEN:
danube_wdt_enable_feature(user_arg, DANUBE_BIU_WDT_CR_LPEN);
case IFXMIPS_WDT_IOC_SET_LPEN:
danube_wdt_enable_feature(user_arg, IFXMIPS_BIU_WDT_CR_LPEN);
break;
case DANUBE_WDT_IOC_SET_CLKDIV:
case IFXMIPS_WDT_IOC_SET_CLKDIV:
danube_wdt_set_clkdiv(user_arg);
break;
@ -239,11 +239,11 @@ danube_wdt_register_proc_read (char *buf, char **start, off_t offset, int count,
{
int len = 0;
len += sprintf (buf + len, "DANUBE_BIU_WDT_PROC_READ\n");
len += sprintf (buf + len, "DANUBE_BIU_WDT_CR(0x%08x) : 0x%08x\n",
(unsigned int)DANUBE_BIU_WDT_CR, readl(DANUBE_BIU_WDT_CR));
len += sprintf (buf + len, "DANUBE_BIU_WDT_SR(0x%08x) : 0x%08x\n",
(unsigned int)DANUBE_BIU_WDT_SR, readl(DANUBE_BIU_WDT_SR));
len += sprintf (buf + len, "IFXMIPS_BIU_WDT_PROC_READ\n");
len += sprintf (buf + len, "IFXMIPS_BIU_WDT_CR(0x%08x) : 0x%08x\n",
(unsigned int)IFXMIPS_BIU_WDT_CR, readl(IFXMIPS_BIU_WDT_CR));
len += sprintf (buf + len, "IFXMIPS_BIU_WDT_SR(0x%08x) : 0x%08x\n",
(unsigned int)IFXMIPS_BIU_WDT_SR, readl(IFXMIPS_BIU_WDT_SR));
*eof = 1;

18
target/linux/ifxmips/files/drivers/mtd/maps/danube.c
View File

@ -1,5 +1,5 @@
/*
* Driver for DANUBE flashmap
* Driver for IFXMIPS flashmap
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -34,7 +34,7 @@
static struct map_info
danube_map = {
.name = "DANUBE_FLASH",
.name = "IFXMIPS_FLASH",
.bankwidth = 2,
.size = 0x400000,
};
@ -108,8 +108,8 @@ danube_partitions[4] = {
},
};
#define DANUBE_FLASH_START 0x10000000
#define DANUBE_FLASH_MAX 0x2000000
#define IFXMIPS_FLASH_START 0x10000000
#define IFXMIPS_FLASH_MAX 0x2000000
int
find_uImage_size (unsigned long start_offset){
@ -136,16 +136,16 @@ init_danube_mtd (void)
struct mtd_partition *parts = NULL;
unsigned long uimage_size;
writel(0x1d7ff, DANUBE_EBU_BUSCON0);
writel(0x1d7ff, IFXMIPS_EBU_BUSCON0);
danube_map.read = danube_read16;
danube_map.write = danube_write16;
danube_map.copy_from = danube_copy_from;
danube_map.copy_to = danube_copy_to;
danube_map.phys = DANUBE_FLASH_START;
danube_map.virt = ioremap_nocache(DANUBE_FLASH_START, DANUBE_FLASH_MAX);
danube_map.size = DANUBE_FLASH_MAX;
danube_map.phys = IFXMIPS_FLASH_START;
danube_map.virt = ioremap_nocache(IFXMIPS_FLASH_START, IFXMIPS_FLASH_MAX);
danube_map.size = IFXMIPS_FLASH_MAX;
if (!danube_map.virt) {
printk(KERN_WARNING "Failed to ioremap!\n");
return -EIO;
@ -191,4 +191,4 @@ module_exit (cleanup_danube_mtd);
MODULE_LICENSE ("GPL");
MODULE_AUTHOR ("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION ("MTD map driver for DANUBE boards");
MODULE_DESCRIPTION ("MTD map driver for IFXMIPS boards");

32
target/linux/ifxmips/files/drivers/net/danube_mii0.c
View File

@ -57,8 +57,8 @@ danube_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
phy_data;
while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
writel(val, DANUBE_PPE32_MDIO_ACC);
while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
writel(val, IFXMIPS_PPE32_MDIO_ACC);
}
unsigned short
@ -68,9 +68,9 @@ danube_read_mdio (u32 phy_addr, u32 phy_reg)
((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
writel(val, DANUBE_PPE32_MDIO_ACC);
while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
val = readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
writel(val, IFXMIPS_PPE32_MDIO_ACC);
while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
val = readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
return val;
}
@ -84,7 +84,7 @@ danube_switch_open (struct net_device *dev)
for (i = 0; i < dma_dev->max_rx_chan_num; i++)
{
if ((dma_dev->rx_chan[i])->control == DANUBE_DMA_CH_ON)
if ((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON)
(dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
}
@ -238,7 +238,7 @@ dma_intr_handler (struct dma_device_info* dma_dev, int status)
netif_stop_queue(&danube_mii0_dev);
for (i = 0; i < dma_dev->max_tx_chan_num; i++)
{
if ((dma_dev->tx_chan[i])->control==DANUBE_DMA_CH_ON)
if ((dma_dev->tx_chan[i])->control==IFXMIPS_DMA_CH_ON)
dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
}
break;
@ -332,15 +332,15 @@ switch_init (struct net_device *dev)
for (i = 0; i < priv->dma_device->max_rx_chan_num; i++)
{
priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
priv->dma_device->rx_chan[i]->control = DANUBE_DMA_CH_ON;
priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON;
}
for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
{
if(i == 0)
priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_ON;
priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON;
else
priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_OFF;
priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF;
}
dma_device_register(priv->dma_device);
@ -373,17 +373,17 @@ switch_init (struct net_device *dev)
static void
danube_sw_chip_init (int mode)
{
danube_pmu_enable(DANUBE_PMU_PWDCR_DMA);
danube_pmu_enable(DANUBE_PMU_PWDCR_PPE);
danube_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
danube_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
if(mode == REV_MII_MODE)
writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, DANUBE_PPE32_CFG);
writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
else if(mode == MII_MODE)
writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, DANUBE_PPE32_CFG);
writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, DANUBE_PPE32_IG_PLEN_CTRL);
writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
writel(PPE32_CGEN, DANUBE_PPE32_ENET_MAC_CFG);
writel(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
wmb();
}

126
target/linux/ifxmips/files/drivers/serial/danube_asc.c
View File

@ -1,5 +1,5 @@
/*
* Driver for DANUBEASC serial ports
* Driver for IFXMIPSASC serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
@ -52,7 +52,7 @@
#include <asm/danube/danube_irq.h>
#include <asm/danube/danube_serial.h>
#define PORT_DANUBEASC 111
#define PORT_IFXMIPSASC 111
#include <linux/serial_core.h>
@ -88,7 +88,7 @@ static void
danubeasc_stop_rx (struct uart_port *port)
{
/* clear the RX enable bit */
writel(ASCWHBSTATE_CLRREN, DANUBE_ASC1_WHBSTATE);
writel(ASCWHBSTATE_CLRREN, IFXMIPS_ASC1_WHBSTATE);
}
static void
@ -104,12 +104,12 @@ danubeasc_rx_chars (struct uart_port *port)
struct tty_struct *tty = port->info->tty;
unsigned int ch = 0, rsr = 0, fifocnt;
fifocnt = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
fifocnt = readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
while (fifocnt--)
{
u8 flag = TTY_NORMAL;
ch = readl(DANUBE_ASC1_RBUF);
rsr = (readl(DANUBE_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
ch = readl(IFXMIPS_ASC1_RBUF);
rsr = (readl(IFXMIPS_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
tty_flip_buffer_push(tty);
port->icount.rx++;
@ -120,14 +120,14 @@ danubeasc_rx_chars (struct uart_port *port)
if (rsr & ASCSTATE_ANY) {
if (rsr & ASCSTATE_PE) {
port->icount.parity++;
writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, DANUBE_ASC1_WHBSTATE);
writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, IFXMIPS_ASC1_WHBSTATE);
} else if (rsr & ASCSTATE_FE) {
port->icount.frame++;
writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, DANUBE_ASC1_WHBSTATE);
writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, IFXMIPS_ASC1_WHBSTATE);
}
if (rsr & ASCSTATE_ROE) {
port->icount.overrun++;
writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
}
rsr &= port->read_status_mask;
@ -166,11 +166,11 @@ danubeasc_tx_chars (struct uart_port *port)
return;
}
while(((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF) != DANUBEASC_TXFIFO_FULL)
while(((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF) != IFXMIPSASC_TXFIFO_FULL)
{
if (port->x_char) {
writel(port->x_char, DANUBE_ASC1_TBUF);
writel(port->x_char, IFXMIPS_ASC1_TBUF);
port->icount.tx++;
port->x_char = 0;
continue;
@ -179,7 +179,7 @@ danubeasc_tx_chars (struct uart_port *port)
if (uart_circ_empty(xmit))
break;
writel(port->info->xmit.buf[port->info->xmit.tail], DANUBE_ASC1_TBUF);
writel(port->info->xmit.buf[port->info->xmit.tail], IFXMIPS_ASC1_TBUF);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
}
@ -191,7 +191,7 @@ danubeasc_tx_chars (struct uart_port *port)
static irqreturn_t
danubeasc_tx_int (int irq, void *port)
{
writel(ASC_IRNCR_TIR, DANUBE_ASC1_IRNCR);
writel(ASC_IRNCR_TIR, IFXMIPS_ASC1_IRNCR);
danubeasc_start_tx(port);
mask_and_ack_danube_irq(irq);
@ -202,8 +202,8 @@ static irqreturn_t
danubeasc_er_int (int irq, void *port)
{
/* clear any pending interrupts */
writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
return IRQ_HANDLED;
}
@ -211,7 +211,7 @@ danubeasc_er_int (int irq, void *port)
static irqreturn_t
danubeasc_rx_int (int irq, void *port)
{
writel(ASC_IRNCR_RIR, DANUBE_ASC1_IRNCR);
writel(ASC_IRNCR_RIR, IFXMIPS_ASC1_IRNCR);
danubeasc_rx_chars((struct uart_port *) port);
mask_and_ack_danube_irq(irq);
@ -223,7 +223,7 @@ danubeasc_tx_empty (struct uart_port *port)
{
int status;
status = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
status = readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
return status ? 0 : TIOCSER_TEMT;
}
@ -251,18 +251,18 @@ danubeasc1_hw_init (void)
{
/* this setup was probably already done in ROM/u-boot but we do it again*/
/* TODO: GPIO pins are multifunction */
writel(readl(DANUBE_ASC1_CLC) & ~DANUBE_ASC1_CLC_DISS, DANUBE_ASC1_CLC);
writel((readl(DANUBE_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), DANUBE_ASC1_CLC);
writel(0, DANUBE_ASC1_PISEL);
writel(((DANUBEASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
writel(((DANUBEASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
writel(readl(IFXMIPS_ASC1_CLC) & ~IFXMIPS_ASC1_CLC_DISS, IFXMIPS_ASC1_CLC);
writel((readl(IFXMIPS_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), IFXMIPS_ASC1_CLC);
writel(0, IFXMIPS_ASC1_PISEL);
writel(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
writel(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
wmb ();
/*framing, overrun, enable */
writel(readl(DANUBE_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
DANUBE_ASC1_CON);
writel(readl(IFXMIPS_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
IFXMIPS_ASC1_CON);
}
static int
@ -281,36 +281,36 @@ danubeasc_startup (struct uart_port *port)
local_irq_save(flags);
retval = request_irq(DANUBEASC1_RIR, danubeasc_rx_int, IRQF_DISABLED, "asc_rx", port);
retval = request_irq(IFXMIPSASC1_RIR, danubeasc_rx_int, IRQF_DISABLED, "asc_rx", port);
if (retval){
printk("failed to request danubeasc_rx_int\n");
return retval;
}
retval = request_irq(DANUBEASC1_TIR, danubeasc_tx_int, IRQF_DISABLED, "asc_tx", port);
retval = request_irq(IFXMIPSASC1_TIR, danubeasc_tx_int, IRQF_DISABLED, "asc_tx", port);
if (retval){
printk("failed to request danubeasc_tx_int\n");
goto err1;
}
retval = request_irq(DANUBEASC1_EIR, danubeasc_er_int, IRQF_DISABLED, "asc_er", port);
retval = request_irq(IFXMIPSASC1_EIR, danubeasc_er_int, IRQF_DISABLED, "asc_er", port);
if (retval){
printk("failed to request danubeasc_er_int\n");
goto err2;
}
writel(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
DANUBE_ASC1_IRNREN);
IFXMIPS_ASC1_IRNREN);
local_irq_restore(flags);
return 0;
err2:
free_irq(DANUBEASC1_TIR, port);
free_irq(IFXMIPSASC1_TIR, port);
err1:
free_irq(DANUBEASC1_RIR, port);
free_irq(IFXMIPSASC1_RIR, port);
local_irq_restore(flags);
return retval;
@ -319,19 +319,19 @@ err1:
static void
danubeasc_shutdown (struct uart_port *port)
{
free_irq(DANUBEASC1_RIR, port);
free_irq(DANUBEASC1_TIR, port);
free_irq(DANUBEASC1_EIR, port);
free_irq(IFXMIPSASC1_RIR, port);
free_irq(IFXMIPSASC1_TIR, port);
free_irq(IFXMIPSASC1_EIR, port);
/*
* disable the baudrate generator to disable the ASC
*/
writel(0, DANUBE_ASC1_CON);
writel(0, IFXMIPS_ASC1_CON);
/* flush and then disable the fifos */
writel(readl(DANUBE_ASC1_RXFCON) | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
writel(readl(DANUBE_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, DANUBE_ASC1_RXFCON);
writel(readl(DANUBE_ASC1_TXFCON) | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
writel(readl(DANUBE_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, DANUBE_ASC1_TXFCON);
writel(readl(IFXMIPS_ASC1_RXFCON) | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
writel(readl(IFXMIPS_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, IFXMIPS_ASC1_RXFCON);
writel(readl(IFXMIPS_ASC1_TXFCON) | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
writel(readl(IFXMIPS_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, IFXMIPS_ASC1_TXFCON);
}
static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
@ -395,7 +395,7 @@ static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new,
local_irq_save(flags);
/* set up CON */
writel(readl(DANUBE_ASC1_CON) | con, DANUBE_ASC1_CON);
writel(readl(IFXMIPS_ASC1_CON) | con, IFXMIPS_ASC1_CON);
/* Set baud rate - take a divider of 2 into account */
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
@ -403,22 +403,22 @@ static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new,
quot = quot / 2 - 1;
/* disable the baudrate generator */
writel(readl(DANUBE_ASC1_CON) & ~ASCCON_R, DANUBE_ASC1_CON);
writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_R, IFXMIPS_ASC1_CON);
/* make sure the fractional divider is off */
writel(readl(DANUBE_ASC1_CON) & ~ASCCON_FDE, DANUBE_ASC1_CON);
writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_FDE, IFXMIPS_ASC1_CON);
/* set up to use divisor of 2 */
writel(readl(DANUBE_ASC1_CON) & ~ASCCON_BRS, DANUBE_ASC1_CON);
writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_BRS, IFXMIPS_ASC1_CON);
/* now we can write the new baudrate into the register */
writel(quot, DANUBE_ASC1_BG);
writel(quot, IFXMIPS_ASC1_BG);
/* turn the baudrate generator back on */
writel(readl(DANUBE_ASC1_CON) | ASCCON_R, DANUBE_ASC1_CON);
writel(readl(IFXMIPS_ASC1_CON) | ASCCON_R, IFXMIPS_ASC1_CON);
/* enable rx */
writel(ASCWHBSTATE_SETREN, DANUBE_ASC1_WHBSTATE);
writel(ASCWHBSTATE_SETREN, IFXMIPS_ASC1_WHBSTATE);
local_irq_restore(flags);
}
@ -426,7 +426,7 @@ static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new,
static const char*
danubeasc_type (struct uart_port *port)
{
return port->type == PORT_DANUBEASC ? "DANUBEASC" : NULL;
return port->type == PORT_IFXMIPSASC ? "IFXMIPSASC" : NULL;
}
static void
@ -445,7 +445,7 @@ static void
danubeasc_config_port (struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
port->type = PORT_DANUBEASC;
port->type = PORT_IFXMIPSASC;
danubeasc_request_port(port);
}
}
@ -454,7 +454,7 @@ static int
danubeasc_verify_port (struct uart_port *port, struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UNKNOWN && ser->type != PORT_DANUBEASC)
if (ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC)
ret = -EINVAL;
if (ser->irq < 0 || ser->irq >= NR_IRQS)
ret = -EINVAL;
@ -483,14 +483,14 @@ static struct uart_ops danubeasc_pops = {
};
static struct uart_port danubeasc_port = {
membase: (void *)DANUBE_ASC1_BASE_ADDR,
mapbase: DANUBE_ASC1_BASE_ADDR,
membase: (void *)IFXMIPS_ASC1_BASE_ADDR,
mapbase: IFXMIPS_ASC1_BASE_ADDR,
iotype: SERIAL_IO_MEM,
irq: DANUBEASC1_RIR,
irq: IFXMIPSASC1_RIR,
uartclk: 0,
fifosize: 16,
unused: {DANUBEASC1_TIR, DANUBEASC1_EIR},
type: PORT_DANUBEASC,
unused: {IFXMIPSASC1_TIR, IFXMIPSASC1_EIR},
type: PORT_IFXMIPSASC,
ops: &danubeasc_pops,
flags: ASYNC_BOOT_AUTOCONF,
};
@ -507,9 +507,9 @@ danubeasc_console_write (struct console *co, const char *s, u_int count)
/* wait until the FIFO is not full */
do
{
fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
fifocnt = (readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
} while (fifocnt == DANUBEASC_TXFIFO_FULL);
} while (fifocnt == IFXMIPSASC_TXFIFO_FULL);
if (s[i] == '\0')
{
@ -518,14 +518,14 @@ danubeasc_console_write (struct console *co, const char *s, u_int count)
if (s[i] == '\n')
{
writel('\r', DANUBE_ASC1_TBUF);
writel('\r', IFXMIPS_ASC1_TBUF);
do
{
fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
fifocnt = (readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
} while (fifocnt == DANUBEASC_TXFIFO_FULL);
} while (fifocnt == IFXMIPSASC_TXFIFO_FULL);
}
writel(s[i], DANUBE_ASC1_TBUF);
writel(s[i], IFXMIPS_ASC1_TBUF);
}
local_irq_restore(flags);
@ -545,7 +545,7 @@ danubeasc_console_setup (struct console *co, char *options)
co->index = 0;
port = &danubeasc_port;
danubeasc_port.uartclk = uartclk;
danubeasc_port.type = PORT_DANUBEASC;
danubeasc_port.type = PORT_IFXMIPSASC;
if (options){
uart_parse_options(options, &baud, &parity, &bits, &flow);

234
target/linux/ifxmips/files/include/asm-mips/danube/danube.h
View File

@ -17,13 +17,13 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_H__
#define _DANUBE_H__
#ifndef _IFXMIPS_H__
#define _IFXMIPS_H__
/*------------ GENERAL */
#define BOARD_SYSTEM_TYPE "DANUBE"
#define BOARD_SYSTEM_TYPE "IFXMIPS"
#define IOPORT_RESOURCE_START 0x10000000
#define IOPORT_RESOURCE_END 0xffffffff
@ -33,15 +33,15 @@
/*------------ ASC1 */
#define DANUBE_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
#define IFXMIPS_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
/* FIFO status register */
#define DANUBE_ASC1_FSTAT ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0048))
#define IFXMIPS_ASC1_FSTAT ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0048))
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
/* ASC1 transmit buffer */
#define DANUBE_ASC1_TBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0020))
#define IFXMIPS_ASC1_TBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0020))
/* channel operating modes */
#define ASCOPT_CSIZE 0x3
@ -53,43 +53,43 @@
#define ASCOPT_CREAD 0x20
/* hardware modified control register */
#define DANUBE_ASC1_WHBSTATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0018))
#define IFXMIPS_ASC1_WHBSTATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0018))
/* receive buffer register */
#define DANUBE_ASC1_RBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0024))
#define IFXMIPS_ASC1_RBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0024))
/* status register */
#define DANUBE_ASC1_STATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0014))
#define IFXMIPS_ASC1_STATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0014))
/* interrupt control */
#define DANUBE_ASC1_IRNCR ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F8))
#define IFXMIPS_ASC1_IRNCR ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F8))
#define ASC_IRNCR_TIR 0x4
#define ASC_IRNCR_RIR 0x2
#define ASC_IRNCR_EIR 0x4
/* clock control */
#define DANUBE_ASC1_CLC ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0000))
#define IFXMIPS_ASC1_CLC ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0000))
#define DANUBE_ASC1_CLC_DISS 0x2
#define IFXMIPS_ASC1_CLC_DISS 0x2
/* port input select register */
#define DANUBE_ASC1_PISEL ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0004))
#define IFXMIPS_ASC1_PISEL ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0004))
/* tx fifo */
#define DANUBE_ASC1_TXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0044))
#define IFXMIPS_ASC1_TXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0044))
/* rx fifo */
#define DANUBE_ASC1_RXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0040))
#define IFXMIPS_ASC1_RXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
/* control */
#define DANUBE_ASC1_CON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0010))
#define IFXMIPS_ASC1_CON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
/* timer reload */
#define DANUBE_ASC1_BG ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0050))
#define IFXMIPS_ASC1_BG ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
/* int enable */
#define DANUBE_ASC1_IRNREN ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F4))
#define IFXMIPS_ASC1_IRNREN ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F4))
#define ASC_IRNREN_RX_BUF 0x8
#define ASC_IRNREN_TX_BUF 0x4
@ -99,54 +99,54 @@
/*------------ RCU */
#define DANUBE_RCU_BASE_ADDR 0xBF203000
#define IFXMIPS_RCU_BASE_ADDR 0xBF203000
/* reset request */
#define DANUBE_RCU_REQ ((u32*)(DANUBE_RCU_BASE_ADDR + 0x0010))
#define DANUBE_RST_ALL 0x40000000
#define IFXMIPS_RCU_REQ ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
#define IFXMIPS_RST_ALL 0x40000000
/*------------ MCD */
#define DANUBE_MCD_BASE_ADDR (KSEG1 + 0x1F106000)
#define IFXMIPS_MCD_BASE_ADDR (KSEG1 + 0x1F106000)
/* chip id */
#define DANUBE_MCD_CHIPID ((u32*)(DANUBE_MCD_BASE_ADDR + 0x0028))
#define IFXMIPS_MCD_CHIPID ((u32*)(IFXMIPS_MCD_BASE_ADDR + 0x0028))
/*------------ GPTU */
#define DANUBE_GPTU_BASE_ADDR 0xB8000300
#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300
/* clock control register */
#define DANUBE_GPTU_GPT_CLC ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0000))
#define IFXMIPS_GPTU_GPT_CLC ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0000))
/* captur reload register */
#define DANUBE_GPTU_GPT_CAPREL ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0030))
#define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))
/* timer 6 control register */
#define DANUBE_GPTU_GPT_T6CON ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0020))
#define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))
/*------------ EBU */
#define DANUBE_EBU_BASE_ADDR 0xBE105300
#define IFXMIPS_EBU_BASE_ADDR 0xBE105300
/* bus configuration register */
#define DANUBE_EBU_BUSCON0 ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0060))
#define DANUBE_EBU_PCC_CON ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0090))
#define DANUBE_EBU_PCC_IEN ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A4))
#define DANUBE_EBU_PCC_ISTAT ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A0))
#define IFXMIPS_EBU_BUSCON0 ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0060))
#define IFXMIPS_EBU_PCC_CON ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0090))
#define IFXMIPS_EBU_PCC_IEN ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A4))
#define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))
/*------------ CGU */
#define DANUBE_CGU_BASE_ADDR 0xBF103000
#define IFXMIPS_CGU_BASE_ADDR 0xBF103000
/* clock mux */
#define DANUBE_CGU_SYS ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0010))
#define DANUBE_CGU_IFCCR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0018))
#define DANUBE_CGU_PCICR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0034))
#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
#define IFXMIPS_CGU_IFCCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
#define IFXMIPS_CGU_PCICR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
#define CLOCK_60M 60000000
#define CLOCK_83M 83333333
@ -158,42 +158,42 @@
/*------------ CGU */
#define DANUBE_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
#define DANUBE_PMU_PWDCR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C))
#define DANUBE_PMU_PWDSR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x0020))
#define IFXMIPS_PMU_PWDCR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x001C))
#define IFXMIPS_PMU_PWDSR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x0020))
/*------------ ICU */
#define DANUBE_ICU_BASE_ADDR 0xBF880200
#define IFXMIPS_ICU_BASE_ADDR 0xBF880200
#define DANUBE_ICU_IM0_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0000))
#define DANUBE_ICU_IM0_IER ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0008))
#define DANUBE_ICU_IM0_IOSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0010))
#define DANUBE_ICU_IM0_IRSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0018))
#define DANUBE_ICU_IM0_IMR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0020))
#define IFXMIPS_ICU_IM0_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0000))
#define IFXMIPS_ICU_IM0_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0008))
#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
#define IFXMIPS_ICU_IM0_IMR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0020))
#define DANUBE_ICU_IM1_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0028))
#define IFXMIPS_ICU_IM1_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0028))
#define DANUBE_ICU_OFFSET (DANUBE_ICU_IM1_ISR - DANUBE_ICU_IM0_ISR)
#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
/*------------ ETOP */
#define DANUBE_PPE32_BASE_ADDR 0xBE180000
#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000
#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
#define DANUBE_PPE32_MEM_MAP (DANUBE_PPE32_BASE_ADDR + 0x10000 )
#define IFXMIPS_PPE32_MEM_MAP (IFXMIPS_PPE32_BASE_ADDR + 0x10000 )
#define MII_MODE 1
#define REV_MII_MODE 2
/* mdio access */
#define DANUBE_PPE32_MDIO_ACC ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1804))
#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1804))
#define MDIO_ACC_REQUEST 0x80000000
#define MDIO_ACC_READ 0x40000000
@ -204,38 +204,38 @@
#define MDIO_ACC_VAL_MASK 0xffff
/* configuration */
#define DANUBE_PPE32_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1808))
#define IFXMIPS_PPE32_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1808))
#define PPE32_MII_MASK 0xfffffffc
#define PPE32_MII_NORMAL 0x8
#define PPE32_MII_REVERSE 0xe
/* packet length */
#define DANUBE_PPE32_IG_PLEN_CTRL ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1820))
#define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1820))
#define PPE32_PLEN_OVER 0x5ee
#define PPE32_PLEN_UNDER 0x400000
/* enet */
#define DANUBE_PPE32_ENET_MAC_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1840))
#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1840))
#define PPE32_CGEN 0x800
/*------------ DMA */
#define DANUBE_DMA_BASE_ADDR 0xBE104100
#define IFXMIPS_DMA_BASE_ADDR 0xBE104100
#define DANUBE_DMA_CS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x18))
#define DANUBE_DMA_CIE ((u32*)(DANUBE_DMA_BASE_ADDR + 0x2C))
#define DANUBE_DMA_IRNEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0xf4))
#define DANUBE_DMA_CCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x1C))
#define DANUBE_DMA_CIS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x28))
#define DANUBE_DMA_CDLEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0x24))
#define DANUBE_DMA_PS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x40))
#define DANUBE_DMA_PCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x44))
#define DANUBE_DMA_CTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x10))
#define DANUBE_DMA_CPOLL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x14))
#define DANUBE_DMA_CDBA ((u32*)(DANUBE_DMA_BASE_ADDR + 0x20))
#define IFXMIPS_DMA_CS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x18))
#define IFXMIPS_DMA_CIE ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x2C))
#define IFXMIPS_DMA_IRNEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0xf4))
#define IFXMIPS_DMA_CCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x1C))
#define IFXMIPS_DMA_CIS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x28))
#define IFXMIPS_DMA_CDLEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x24))
#define IFXMIPS_DMA_PS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x40))
#define IFXMIPS_DMA_PCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x44))
#define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10))
#define IFXMIPS_DMA_CPOLL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x14))
#define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20))
/*------------ PCI */
@ -273,82 +273,82 @@
/*------------ WDT */
#define DANUBE_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
#define DANUBE_BIU_WDT_CR ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F0))
#define DANUBE_BIU_WDT_SR ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F8))
#define IFXMIPS_BIU_WDT_CR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F0))
#define IFXMIPS_BIU_WDT_SR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F8))
#define DANUBE_BIU_WDT_CR_GEN (1 << 31)
#define DANUBE_BIU_WDT_CR_DSEN (1 << 30)
#define DANUBE_BIU_WDT_CR_LPEN (1 << 29)
#define IFXMIPS_BIU_WDT_CR_GEN (1 << 31)
#define IFXMIPS_BIU_WDT_CR_DSEN (1 << 30)
#define IFXMIPS_BIU_WDT_CR_LPEN (1 << 29)
#define DANUBE_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
#define DANUBE_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
#define DANUBE_BIU_WDT_CR_PWL_SET(value) ((((1 << 2) - 1) & (value)) << 26)
#define DANUBE_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
#define DANUBE_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
#define DANUBE_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
#define IFXMIPS_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
#define IFXMIPS_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
#define IFXMIPS_BIU_WDT_CR_PWL_SET(value) ((((1 << 2) - 1) & (value)) << 26)
#define IFXMIPS_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
#define IFXMIPS_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
#define IFXMIPS_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
/*------------ LED */
#define DANUBE_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
#define DANUBE_LED_CON0 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0000))
#define DANUBE_LED_CON1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0004))
#define DANUBE_LED_CPU0 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0008))
#define DANUBE_LED_CPU1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x000C))
#define DANUBE_LED_AR ((u32*)(DANUBE_LED_BASE_ADDR + 0x0010))
#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
#define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000))
#define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004))
#define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008))
#define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C))
#define IFXMIPS_LED_AR ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0010))
#define LED_CON0_SWU (1 << 31)
#define LED_CON0_AD1 (1 << 25)
#define LED_CON0_AD0 (1 << 24)
#define DANUBE_LED_2HZ (0)
#define DANUBE_LED_4HZ (1 << 23)
#define DANUBE_LED_8HZ (2 << 23)
#define DANUBE_LED_10HZ (3 << 23)
#define DANUBE_LED_MASK (0xf << 23)
#define IFXMIPS_LED_2HZ (0)
#define IFXMIPS_LED_4HZ (1 << 23)
#define IFXMIPS_LED_8HZ (2 << 23)
#define IFXMIPS_LED_10HZ (3 << 23)
#define IFXMIPS_LED_MASK (0xf << 23)
#define DANUBE_LED_UPD_SRC_FPI (1 << 31)
#define DANUBE_LED_UPD_MASK (3 << 30)
#define DANUBE_LED_ADSL_SRC (3 << 24)
#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31)
#define IFXMIPS_LED_UPD_MASK (3 << 30)
#define IFXMIPS_LED_ADSL_SRC (3 << 24)
#define DANUBE_LED_GROUP0 (1 << 0)
#define DANUBE_LED_GROUP1 (1 << 1)
#define DANUBE_LED_GROUP2 (1 << 2)
#define IFXMIPS_LED_GROUP0 (1 << 0)
#define IFXMIPS_LED_GROUP1 (1 << 1)
#define IFXMIPS_LED_GROUP2 (1 << 2)
#define DANUBE_LED_RISING 0
#define DANUBE_LED_FALLING (1 << 26)
#define DANUBE_LED_EDGE_MASK (1 << 26)
#define IFXMIPS_LED_RISING 0
#define IFXMIPS_LED_FALLING (1 << 26)
#define IFXMIPS_LED_EDGE_MASK (1 << 26)
/*------------ GPIO */
#define DANUBE_GPIO_BASE_ADDR (0xBE100B00)
#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
#define DANUBE_GPIO_P0_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0010))
#define DANUBE_GPIO_P1_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040))
#define DANUBE_GPIO_P0_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0014))
#define DANUBE_GPIO_P1_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0044))
#define DANUBE_GPIO_P0_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0018))
#define DANUBE_GPIO_P1_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048))
#define DANUBE_GPIO_P0_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x001C))
#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C))
#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020))
#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050))
#define DANUBE_GPIO_P0_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0024))
#define DANUBE_GPIO_P1_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054))
#define DANUBE_GPIO_P0_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0028))
#define DANUBE_GPIO_P1_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0058))
#define DANUBE_GPIO_P0_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x002C))
#define DANUBE_GPIO_P1_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x005C))
#define DANUBE_GPIO_P0_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0030))
#define DANUBE_GPIO_P1_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0060))
#define IFXMIPS_GPIO_P0_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
#define IFXMIPS_GPIO_P1_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
#define IFXMIPS_GPIO_P0_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
#define IFXMIPS_GPIO_P1_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
#define IFXMIPS_GPIO_P0_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
#define IFXMIPS_GPIO_P1_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
#define IFXMIPS_GPIO_P0_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
#define IFXMIPS_GPIO_P1_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
#define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
#define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
#define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
#define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
#define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
#define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
/*------------ SSC */
#define DANUBE_SSC1_BASE_ADDR (KSEG1 + 0x1e100800)
#define IFXMIPS_SSC1_BASE_ADDR (KSEG1 + 0x1e100800)

16
target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h
View File

@ -17,15 +17,15 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_DMA_H__
#define _DANUBE_DMA_H__
#ifndef _IFXMIPS_DMA_H__
#define _IFXMIPS_DMA_H__
#define RCV_INT 1
#define TX_BUF_FULL_INT 2
#define TRANSMIT_CPT_INT 4
#define DANUBE_DMA_CH_ON 1
#define DANUBE_DMA_CH_OFF 0
#define DANUBE_DMA_CH_DEFAULT_WEIGHT 100
#define IFXMIPS_DMA_CH_ON 1
#define IFXMIPS_DMA_CH_OFF 0
#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100
enum attr_t{
TX = 0,
@ -53,8 +53,8 @@ enum attr_t{
#define DMA_DROP_MASK (1<<31)
#define DANUBE_DMA_RX -1
#define DANUBE_DMA_TX 1
#define IFXMIPS_DMA_RX -1
#define IFXMIPS_DMA_TX 1
typedef struct dma_chan_map {
char dev_name[15];
@ -151,7 +151,7 @@ typedef struct dma_channel_info{
/*on or off of this channel*/
int control;
/**optional information for the upper layer devices*/
#if defined(CONFIG_DANUBE_ETHERNET_D2) || defined(CONFIG_DANUBE_PPA)
#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
void* opt[64];
#else
void* opt[25];

4
target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h
View File

@ -16,8 +16,8 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_GPIO_H__
#define _DANUBE_GPIO_H__
#ifndef _IFXMIPS_GPIO_H__
#define _IFXMIPS_GPIO_H__
extern int danube_port_reserve_pin (unsigned int port, unsigned int pin);
extern int danube_port_free_pin (unsigned int port, unsigned int pin);

24
target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h
View File

@ -16,8 +16,8 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_IOCTL_H__
#define _DANUBE_IOCTL_H__
#ifndef _IFXMIPS_IOCTL_H__
#define _IFXMIPS_IOCTL_H__
/*------------ LED */
@ -28,15 +28,15 @@ struct danube_port_ioctl_parm
int value;
};
#define DANUBE_PORT_IOC_MAGIC 0xbf
#define DANUBE_PORT_IOCOD _IOW(DANUBE_PORT_IOC_MAGIC,0,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCPUDSEL _IOW(DANUBE_PORT_IOC_MAGIC,1,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCPUDEN _IOW(DANUBE_PORT_IOC_MAGIC,2,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCSTOFF _IOW(DANUBE_PORT_IOC_MAGIC,3,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCDIR _IOW(DANUBE_PORT_IOC_MAGIC,4,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCOUTPUT _IOW(DANUBE_PORT_IOC_MAGIC,5,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCINPUT _IOWR(DANUBE_PORT_IOC_MAGIC,6,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCALTSEL0 _IOW(DANUBE_PORT_IOC_MAGIC,7,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCALTSEL1 _IOW(DANUBE_PORT_IOC_MAGIC,8,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOC_MAGIC 0xbf
#define IFXMIPS_PORT_IOCOD _IOW(IFXMIPS_PORT_IOC_MAGIC,0,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCPUDSEL _IOW(IFXMIPS_PORT_IOC_MAGIC,1,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCPUDEN _IOW(IFXMIPS_PORT_IOC_MAGIC,2,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCSTOFF _IOW(IFXMIPS_PORT_IOC_MAGIC,3,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCDIR _IOW(IFXMIPS_PORT_IOC_MAGIC,4,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCOUTPUT _IOW(IFXMIPS_PORT_IOC_MAGIC,5,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCINPUT _IOWR(IFXMIPS_PORT_IOC_MAGIC,6,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCALTSEL0 _IOW(IFXMIPS_PORT_IOC_MAGIC,7,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCALTSEL1 _IOW(IFXMIPS_PORT_IOC_MAGIC,8,struct danube_port_ioctl_parm)
#endif

58
target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h
View File

@ -17,8 +17,8 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_IRQ__
#define _DANUBE_IRQ__
#ifndef _IFXMIPS_IRQ__
#define _IFXMIPS_IRQ__
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
@ -28,38 +28,38 @@
#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
#define DANUBEASC1_TIR (INT_NUM_IM3_IRL0 + 7)
#define DANUBEASC1_RIR (INT_NUM_IM3_IRL0 + 9)
#define DANUBEASC1_EIR (INT_NUM_IM3_IRL0 + 10)
#define IFXMIPSASC1_TIR (INT_NUM_IM3_IRL0 + 7)
#define IFXMIPSASC1_RIR (INT_NUM_IM3_IRL0 + 9)
#define IFXMIPSASC1_EIR (INT_NUM_IM3_IRL0 + 10)
#define DANUBE_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
#define DANUBE_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
#define DANUBE_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
#define IFXMIPS_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
#define IFXMIPS_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
#define IFXMIPS_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
#define DANUBE_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
#define IFXMIPS_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
#define MIPS_CPU_TIMER_IRQ 7
#define DANUBE_DMA_CH0_INT (INT_NUM_IM2_IRL0)
#define DANUBE_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
#define DANUBE_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
#define DANUBE_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
#define DANUBE_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
#define DANUBE_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
#define DANUBE_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
#define DANUBE_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
#define DANUBE_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
#define DANUBE_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
#define DANUBE_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
#define DANUBE_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
#define DANUBE_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
#define DANUBE_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
#define DANUBE_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
#define DANUBE_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
#define DANUBE_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
#define DANUBE_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
#define DANUBE_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
#define DANUBE_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
#define IFXMIPS_DMA_CH0_INT (INT_NUM_IM2_IRL0)
#define IFXMIPS_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
#define IFXMIPS_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
#define IFXMIPS_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
#define IFXMIPS_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
#define IFXMIPS_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
#define IFXMIPS_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
#define IFXMIPS_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
#define IFXMIPS_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
#define IFXMIPS_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
#define IFXMIPS_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
#define IFXMIPS_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
#define IFXMIPS_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
#define IFXMIPS_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
#define IFXMIPS_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
#define IFXMIPS_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
#define IFXMIPS_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
#define IFXMIPS_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
#define IFXMIPS_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
#define IFXMIPS_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
extern void mask_and_ack_danube_irq (unsigned int irq_nr);

8
target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h
View File

@ -1,5 +1,5 @@
#ifndef DANUBE_SW_H
#define DANUBE_SW_H
#ifndef IFXMIPS_SW_H
#define IFXMIPS_SW_H
@ -138,7 +138,7 @@
#define PHY1_ADDR 1
#define P1M 0
#define DANUBE_SW_REG32(reg_num) *((volatile u32*)(reg_num))
#define IFXMIPS_SW_REG32(reg_num) *((volatile u32*)(reg_num))
#define OK 0;
@ -251,4 +251,4 @@ struct switch_priv {
enum duplex current_duplex;
};
#endif //DANUBE_SW_H
#endif //IFXMIPS_SW_H

2342
target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h
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File diff suppressed because it is too large Load Diff

14
target/linux/ifxmips/files/include/asm-mips/danube/danube_pmu.h
View File

@ -16,14 +16,14 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_PMU_H__
#define _DANUBE_PMU_H__
#ifndef _IFXMIPS_PMU_H__
#define _IFXMIPS_PMU_H__
#define DANUBE_PMU_PWDCR_DMA 0x20
#define DANUBE_PMU_PWDCR_LED 0x800
#define DANUBE_PMU_PWDCR_GPT 0x1000
#define DANUBE_PMU_PWDCR_PPE 0x2000
#define DANUBE_PMU_PWDCR_FPI 0x4000
#define IFXMIPS_PMU_PWDCR_DMA 0x20
#define IFXMIPS_PMU_PWDCR_LED 0x800
#define IFXMIPS_PMU_PWDCR_GPT 0x1000
#define IFXMIPS_PMU_PWDCR_PPE 0x2000
#define IFXMIPS_PMU_PWDCR_FPI 0x4000
void danube_pmu_enable (unsigned int module);
void danube_pmu_disable (unsigned int module);

36
target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h
View File

@ -1,7 +1,7 @@
/* incaAscSio.h - (DANUBE) ASC UART tty driver header */
/* incaAscSio.h - (IFXMIPS) ASC UART tty driver header */
#ifndef __DANUBE_ASC_H
#define __DANUBE_ASC_H
#ifndef __IFXMIPS_ASC_H
#define __IFXMIPS_ASC_H
/******************************************************************************
**
@ -41,29 +41,29 @@
/* ASC input select (0 or 1) */
#define CONSOLE_TTY 0
#define DANUBEASC_TXFIFO_FL 1
#define DANUBEASC_RXFIFO_FL 1
#define DANUBEASC_TXFIFO_FULL 16
#define IFXMIPSASC_TXFIFO_FL 1
#define IFXMIPSASC_RXFIFO_FL 1
#define IFXMIPSASC_TXFIFO_FULL 16
/* interrupt lines masks for the ASC device interrupts*/
/* change these macroses if it's necessary */
#define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
#define IFXMIPSASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
#define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
#define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
#define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
#define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
#define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
#define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
#define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
#define IFXMIPSASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
#define IFXMIPSASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
#define IFXMIPSASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
#define IFXMIPSASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
#define IFXMIPSASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
#define IFXMIPSASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
#define IFXMIPSASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
/* interrupt controller access macros */
#define ASC_INTERRUPTS_ENABLE(X) \
*((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X;
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) |= X;
#define ASC_INTERRUPTS_DISABLE(X) \
*((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X;
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) &= ~X;
#define ASC_INTERRUPTS_CLEAR(X) \
*((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X;
*((volatile unsigned int*) IFXMIPS_ICU_IM0_ISR) = X;
/* CLC register's bits and bitfields */
#define ASCCLC_DISR 0x00000001
@ -191,4 +191,4 @@
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
#endif /* __DANUBE_ASC_H */
#endif /* __IFXMIPS_ASC_H */

42
target/linux/ifxmips/files/include/asm-mips/danube/danube_wdt.h
View File

@ -18,31 +18,31 @@
*
*/
#ifndef DANUBE_WDT_H
#define DANUBE_WDT_H
#ifndef IFXMIPS_WDT_H
#define IFXMIPS_WDT_H
/* Danube wdt ioctl control */
#define DANUBE_WDT_IOC_MAGIC 0xc0
#define DANUBE_WDT_IOC_START _IOW(DANUBE_WDT_IOC_MAGIC, 0, int)
#define DANUBE_WDT_IOC_STOP _IO(DANUBE_WDT_IOC_MAGIC, 1)
#define DANUBE_WDT_IOC_PING _IO(DANUBE_WDT_IOC_MAGIC, 2)
#define DANUBE_WDT_IOC_SET_PWL _IOW(DANUBE_WDT_IOC_MAGIC, 3, int)
#define DANUBE_WDT_IOC_SET_DSEN _IOW(DANUBE_WDT_IOC_MAGIC, 4, int)
#define DANUBE_WDT_IOC_SET_LPEN _IOW(DANUBE_WDT_IOC_MAGIC, 5, int)
#define DANUBE_WDT_IOC_GET_STATUS _IOR(DANUBE_WDT_IOC_MAGIC, 6, int)
#define DANUBE_WDT_IOC_SET_CLKDIV _IOW(DANUBE_WDT_IOC_MAGIC, 7, int)
#define IFXMIPS_WDT_IOC_MAGIC 0xc0
#define IFXMIPS_WDT_IOC_START _IOW(IFXMIPS_WDT_IOC_MAGIC, 0, int)
#define IFXMIPS_WDT_IOC_STOP _IO(IFXMIPS_WDT_IOC_MAGIC, 1)
#define IFXMIPS_WDT_IOC_PING _IO(IFXMIPS_WDT_IOC_MAGIC, 2)
#define IFXMIPS_WDT_IOC_SET_PWL _IOW(IFXMIPS_WDT_IOC_MAGIC, 3, int)
#define IFXMIPS_WDT_IOC_SET_DSEN _IOW(IFXMIPS_WDT_IOC_MAGIC, 4, int)
#define IFXMIPS_WDT_IOC_SET_LPEN _IOW(IFXMIPS_WDT_IOC_MAGIC, 5, int)
#define IFXMIPS_WDT_IOC_GET_STATUS _IOR(IFXMIPS_WDT_IOC_MAGIC, 6, int)
#define IFXMIPS_WDT_IOC_SET_CLKDIV _IOW(IFXMIPS_WDT_IOC_MAGIC, 7, int)
/* password 1 and 2 */
#define DANUBE_WDT_PW1 0x000000BE
#define DANUBE_WDT_PW2 0x000000DC
#define IFXMIPS_WDT_PW1 0x000000BE
#define IFXMIPS_WDT_PW2 0x000000DC
#define DANUBE_WDT_CLKDIV0_VAL 1
#define DANUBE_WDT_CLKDIV1_VAL 64
#define DANUBE_WDT_CLKDIV2_VAL 4096
#define DANUBE_WDT_CLKDIV3_VAL 262144
#define DANUBE_WDT_CLKDIV0 0
#define DANUBE_WDT_CLKDIV1 1
#define DANUBE_WDT_CLKDIV2 2
#define DANUBE_WDT_CLKDIV3 3
#define IFXMIPS_WDT_CLKDIV0_VAL 1
#define IFXMIPS_WDT_CLKDIV1_VAL 64
#define IFXMIPS_WDT_CLKDIV2_VAL 4096
#define IFXMIPS_WDT_CLKDIV3_VAL 262144
#define IFXMIPS_WDT_CLKDIV0 0
#define IFXMIPS_WDT_CLKDIV1 1
#define IFXMIPS_WDT_CLKDIV2 2
#define IFXMIPS_WDT_CLKDIV3 3
#endif

4
target/linux/ifxmips/files/include/asm-mips/mach-danube/irq.h
View File

@ -1,5 +1,5 @@
#ifndef __DANUBE_IRQ_H
#define __DANUBE_IRQ_H
#ifndef __IFXMIPS_IRQ_H
#define __IFXMIPS_IRQ_H
#define NR_IRQS 256
#include_next <irq.h>

14
target/linux/ifxmips/patches/100-board.patch
View File

@ -6,7 +6,7 @@ Index: linux-2.6.23/arch/mips/Kconfig
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
+config DANUBE
+config IFXMIPS
+ bool "Danube support"
+ select DMA_NONCOHERENT
+ select IRQ_CPU
@ -37,11 +37,11 @@ Index: linux-2.6.23/arch/mips/Makefile
load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
+#
+# Infineon DANUBE
+# Infineon IFXMIPS
+#
+core-$(CONFIG_DANUBE) += arch/mips/danube/
+cflags-$(CONFIG_DANUBE) += -Iinclude/asm-mips/mach-danube
+load-$(CONFIG_DANUBE) += 0xffffffff80002000
+core-$(CONFIG_IFXMIPS) += arch/mips/danube/
+cflags-$(CONFIG_IFXMIPS) += -Iinclude/asm-mips/mach-danube
+load-$(CONFIG_IFXMIPS) += 0xffffffff80002000
+
#
# DECstation family
@ -57,8 +57,8 @@ Index: linux-2.6.23/include/asm-mips/bootinfo.h
+/*
+ * Valid machtype for group ATHEROS
+ */
+#define MACH_GROUP_DANUBE 29
+#define MACH_INFINEON_DANUBE 0
+#define MACH_GROUP_IFXMIPS 29
+#define MACH_INFINEON_IFXMIPS 0
+
+
#define CL_SIZE COMMAND_LINE_SIZE

28
target/linux/ifxmips/patches/110-drivers.patch
View File

@ -6,9 +6,9 @@ Index: linux-2.6.23/drivers/serial/Kconfig
Currently, only 8250 compatible ports are supported, but
others can easily be added.
+config SERIAL_DANUBE
+config SERIAL_IFXMIPS
+ bool "Danube serial driver"
+ depends on DANUBE
+ depends on IFXMIPS
+ help
+ Driver for the danubes built in ASC hardware
+
@ -21,7 +21,7 @@ Index: linux-2.6.23/drivers/serial/Makefile
obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
+obj-$(CONFIG_SERIAL_DANUBE) += danube_asc.o
+obj-$(CONFIG_SERIAL_IFXMIPS) += danube_asc.o
Index: linux-2.6.23/drivers/mtd/maps/Makefile
===================================================================
--- linux-2.6.23.orig/drivers/mtd/maps/Makefile 2007-12-13 20:41:42.000000000 +0100
@ -30,7 +30,7 @@ Index: linux-2.6.23/drivers/mtd/maps/Makefile
obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
obj-$(CONFIG_MTD_TQM834x) += tqm834x.o
+obj-$(CONFIG_MTD_DANUBE) += danube.o
+obj-$(CONFIG_MTD_IFXMIPS) += danube.o
Index: linux-2.6.23/drivers/net/Kconfig
===================================================================
--- linux-2.6.23.orig/drivers/net/Kconfig 2007-12-13 20:41:42.000000000 +0100
@ -39,15 +39,15 @@ Index: linux-2.6.23/drivers/net/Kconfig
source "drivers/net/arm/Kconfig"
+config DANUBE_MII0
+config IFXMIPS_MII0
+ tristate "Infineon Danube eth0 driver"
+ depends on DANUBE
+ depends on IFXMIPS
+ help
+ Support for the MII0 inside the Danube SOC
+
+config DANUBE_MII1
+config IFXMIPS_MII1
+ tristate "Infineon Danube eth1 driver"
+ depends on DANUBE
+ depends on IFXMIPS
+ help
+ Support for the MII1 inside the Danube SOC
+
@ -62,7 +62,7 @@ Index: linux-2.6.23/drivers/net/Makefile
obj-$(CONFIG_FEC_8XX) += fec_8xx/
obj-$(CONFIG_PASEMI_MAC) += pasemi_mac.o
obj-$(CONFIG_MLX4_CORE) += mlx4/
+obj-$(CONFIG_DANUBE_MII0) += danube_mii0.o
+obj-$(CONFIG_IFXMIPS_MII0) += danube_mii0.o
obj-$(CONFIG_MACB) += macb.o
@ -74,7 +74,7 @@ Index: linux-2.6.23/drivers/char/watchdog/Makefile
obj-$(CONFIG_INDYDOG) += indydog.o
obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
+obj-$(CONFIG_DANUBE_WDT) += danube_wdt.o
+obj-$(CONFIG_IFXMIPS_WDT) += danube_wdt.o
# PARISC Architecture
@ -87,7 +87,7 @@ Index: linux-2.6.23/drivers/char/Makefile
endif
+
+obj-$(CONFIG_DANUBE_LED) += danube_led.o
+obj-$(CONFIG_DANUBE_GPIO) += danube_gpio.o
+obj-$(CONFIG_DANUBE_SSC) += danube_ssc.o
+obj-$(CONFIG_DANUBE_EEPROM) += danube_eeprom.o
+obj-$(CONFIG_IFXMIPS_LED) += danube_led.o
+obj-$(CONFIG_IFXMIPS_GPIO) += danube_gpio.o
+obj-$(CONFIG_IFXMIPS_SSC) += danube_ssc.o
+obj-$(CONFIG_IFXMIPS_EEPROM) += danube_eeprom.o

2
target/linux/ifxmips/patches/160-cfi-swap.patch
View File

@ -7,7 +7,7 @@ Index: linux-2.6.23/drivers/mtd/chips/cfi_cmdset_0002.c
map_word oldd;
int retry_cnt = 0;
-
+#ifdef CONFIG_DANUBE
+#ifdef CONFIG_IFXMIPS
+ adr ^= 2;
+#endif
adr += chip->start;