1
0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-11-24 00:30:16 +02:00

[rdc] rework reboot mechanism with the new watchdog fixes

The fixing of the watchdog driver makes it generate a NMI so the reboot_fixup
can no longer be called from NMI context, instead, override the machine_retart
callback with our southrbridge reboot mechanism. Patch by Bernhard Loos.

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19977 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian 2010-03-04 08:28:20 +00:00
parent e1e080bae6
commit d34517dacf
3 changed files with 46 additions and 2 deletions

View File

@ -280,7 +280,7 @@ CONFIG_X86_MINIMUM_CPU_FAMILY=4
CONFIG_X86_POPAD_OK=y
# CONFIG_X86_PPRO_FENCE is not set
CONFIG_X86_RDC321X=y
CONFIG_X86_REBOOTFIXUPS=y
# CONFIG_X86_REBOOTFIXUPS is not set
# CONFIG_X86_RESERVE_LOW_64K is not set
# CONFIG_X86_UP_APIC is not set
# CONFIG_X86_VERBOSE_BOOTUP is not set

View File

@ -1,5 +1,5 @@
#
# Makefile for the RDC321x specific parts of the kernel
#
obj-$(CONFIG_X86_RDC321X) := gpio.o platform.o pci.o
obj-$(CONFIG_X86_RDC321X) := gpio.o platform.o pci.o reboot.o

View File

@ -0,0 +1,44 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*
*/
#include <asm/reboot.h>
#include <asm/io.h>
static void rdc321x_reset(void)
{
unsigned i;
/* write to southbridge config register 0x41
enable pci reset on cpu reset, make internal port 0x92 writeable
and switch port 0x92 to internal */
outl(0x80003840, 0xCF8);
i = inl(0xCFC);
i |= 0x1600;
outl(i, 0xCFC);
/* soft reset */
outb(1, 0x92);
}
static int __init rdc_setup_reset(void)
{
machine_ops.emergency_restart = rdc321x_reset;
return 0;
}
arch_initcall(rdc_setup_reset);