qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-07-07 14:27:39 +03:00
Code

bcm63xx: Fix SPI commands and register offsets for BCM6348

Browse Source 
In 240-spi.patch, spi registers for bcm6348 were all messed up. This patch fixes that.
It also fixes some spi commands for all bcm63xx.

Signed-off-by: Anthony Blakemore <stokie-ant@raverbaby.co.uk>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27774 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
jogo 2011-07-25 19:52:47 +00:00
parent a8907a6272
commit d983336e06
2 changed files with 30 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
target/linux/brcm63xx/patches-2.6.39/240-spi.patch
View File

@ -195,17 +195,17 @@
+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
+
+/* BCM 6348 SPI core */
+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x00
+#define SPI_BCM_6348_SPI_INT_STATUS 0x01
+#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
+#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
+#define SPI_BCM_6348_SPI_CLK_CFG 0x05
+#define SPI_BCM_6348_SPI_ST 0x06
+#define SPI_BCM_6348_SPI_INT_MASK 0x07
+#define SPI_BCM_6348_SPI_RX_TAIL 0x08
+#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
+#define SPI_BCM_6348_SPI_MSG_DATA 0x40
+#define SPI_BCM_6348_SPI_MSG_CTL 0x42
+#define SPI_BCM_6348_SPI_CMD 0x00 /* 16-bits register */
+#define SPI_BCM_6348_SPI_INT_STATUS 0x02
+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x03
+#define SPI_BCM_6348_SPI_INT_MASK 0x04
+#define SPI_BCM_6348_SPI_ST 0x05
+#define SPI_BCM_6348_SPI_CLK_CFG 0x06
+#define SPI_BCM_6348_SPI_FILL_BYTE 0x07
+#define SPI_BCM_6348_SPI_MSG_TAIL 0x09
+#define SPI_BCM_6348_SPI_RX_TAIL 0x0b
+#define SPI_BCM_6348_SPI_MSG_CTL 0x40
+#define SPI_BCM_6348_SPI_MSG_DATA 0x41
+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
+#define SPI_BCM_6348_SPI_RX_DATA 0x80
+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
@ -244,10 +244,10 @@
+#define SPI_MSG_TYPE_SHIFT 14
+
+/* Command */
+#define SPI_CMD_NOOP 0x01
+#define SPI_CMD_SOFT_RESET 0x02
+#define SPI_CMD_HARD_RESET 0x04
+#define SPI_CMD_START_IMMEDIATE 0x08
+#define SPI_CMD_NOOP 0x00
+#define SPI_CMD_SOFT_RESET 0x01
+#define SPI_CMD_HARD_RESET 0x02
+#define SPI_CMD_START_IMMEDIATE 0x03
+#define SPI_CMD_COMMAND_SHIFT 0
+#define SPI_CMD_COMMAND_MASK 0x000f
+#define SPI_CMD_DEVICE_ID_SHIFT 4

30
target/linux/brcm63xx/patches-3.0/240-spi.patch
View File

@ -195,17 +195,17 @@
+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
+
+/* BCM 6348 SPI core */
+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x00
+#define SPI_BCM_6348_SPI_INT_STATUS 0x01
+#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
+#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
+#define SPI_BCM_6348_SPI_CLK_CFG 0x05
+#define SPI_BCM_6348_SPI_ST 0x06
+#define SPI_BCM_6348_SPI_INT_MASK 0x07
+#define SPI_BCM_6348_SPI_RX_TAIL 0x08
+#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
+#define SPI_BCM_6348_SPI_MSG_DATA 0x40
+#define SPI_BCM_6348_SPI_MSG_CTL 0x42
+#define SPI_BCM_6348_SPI_CMD 0x00 /* 16-bits register */
+#define SPI_BCM_6348_SPI_INT_STATUS 0x02
+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x03
+#define SPI_BCM_6348_SPI_INT_MASK 0x04
+#define SPI_BCM_6348_SPI_ST 0x05
+#define SPI_BCM_6348_SPI_CLK_CFG 0x06
+#define SPI_BCM_6348_SPI_FILL_BYTE 0x07
+#define SPI_BCM_6348_SPI_MSG_TAIL 0x09
+#define SPI_BCM_6348_SPI_RX_TAIL 0x0b
+#define SPI_BCM_6348_SPI_MSG_CTL 0x40
+#define SPI_BCM_6348_SPI_MSG_DATA 0x41
+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
+#define SPI_BCM_6348_SPI_RX_DATA 0x80
+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
@ -244,10 +244,10 @@
+#define SPI_MSG_TYPE_SHIFT 14
+
+/* Command */
+#define SPI_CMD_NOOP 0x01
+#define SPI_CMD_SOFT_RESET 0x02
+#define SPI_CMD_HARD_RESET 0x04
+#define SPI_CMD_START_IMMEDIATE 0x08
+#define SPI_CMD_NOOP 0x00
+#define SPI_CMD_SOFT_RESET 0x01
+#define SPI_CMD_HARD_RESET 0x02
+#define SPI_CMD_START_IMMEDIATE 0x03
+#define SPI_CMD_COMMAND_SHIFT 0
+#define SPI_CMD_COMMAND_MASK 0x000f
+#define SPI_CMD_DEVICE_ID_SHIFT 4