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bcm63xx: Fix SPI commands and register offsets for BCM6348
In 240-spi.patch, spi registers for bcm6348 were all messed up. This patch fixes that. It also fixes some spi commands for all bcm63xx. Signed-off-by: Anthony Blakemore <stokie-ant@raverbaby.co.uk> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27774 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -195,17 +195,17 @@
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+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
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+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
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+
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+
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+/* BCM 6348 SPI core */
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+/* BCM 6348 SPI core */
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+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x00
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+#define SPI_BCM_6348_SPI_CMD 0x00 /* 16-bits register */
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+#define SPI_BCM_6348_SPI_INT_STATUS 0x01
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+#define SPI_BCM_6348_SPI_INT_STATUS 0x02
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+#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
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+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x03
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+#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
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+#define SPI_BCM_6348_SPI_INT_MASK 0x04
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+#define SPI_BCM_6348_SPI_CLK_CFG 0x05
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+#define SPI_BCM_6348_SPI_ST 0x05
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+#define SPI_BCM_6348_SPI_ST 0x06
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+#define SPI_BCM_6348_SPI_CLK_CFG 0x06
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+#define SPI_BCM_6348_SPI_INT_MASK 0x07
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+#define SPI_BCM_6348_SPI_FILL_BYTE 0x07
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+#define SPI_BCM_6348_SPI_RX_TAIL 0x08
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+#define SPI_BCM_6348_SPI_MSG_TAIL 0x09
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+#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
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+#define SPI_BCM_6348_SPI_RX_TAIL 0x0b
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+#define SPI_BCM_6348_SPI_MSG_DATA 0x40
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+#define SPI_BCM_6348_SPI_MSG_CTL 0x40
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+#define SPI_BCM_6348_SPI_MSG_CTL 0x42
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+#define SPI_BCM_6348_SPI_MSG_DATA 0x41
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+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
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+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
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+#define SPI_BCM_6348_SPI_RX_DATA 0x80
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+#define SPI_BCM_6348_SPI_RX_DATA 0x80
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+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
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+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
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@ -244,10 +244,10 @@
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+#define SPI_MSG_TYPE_SHIFT 14
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+#define SPI_MSG_TYPE_SHIFT 14
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+
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+
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+/* Command */
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+/* Command */
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+#define SPI_CMD_NOOP 0x01
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+#define SPI_CMD_NOOP 0x00
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+#define SPI_CMD_SOFT_RESET 0x02
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+#define SPI_CMD_SOFT_RESET 0x01
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+#define SPI_CMD_HARD_RESET 0x04
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+#define SPI_CMD_HARD_RESET 0x02
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+#define SPI_CMD_START_IMMEDIATE 0x08
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+#define SPI_CMD_START_IMMEDIATE 0x03
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+#define SPI_CMD_COMMAND_SHIFT 0
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+#define SPI_CMD_COMMAND_SHIFT 0
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+#define SPI_CMD_COMMAND_MASK 0x000f
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+#define SPI_CMD_COMMAND_MASK 0x000f
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+#define SPI_CMD_DEVICE_ID_SHIFT 4
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+#define SPI_CMD_DEVICE_ID_SHIFT 4
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@ -195,17 +195,17 @@
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+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
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+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
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+
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+
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+/* BCM 6348 SPI core */
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+/* BCM 6348 SPI core */
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+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x00
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+#define SPI_BCM_6348_SPI_CMD 0x00 /* 16-bits register */
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+#define SPI_BCM_6348_SPI_INT_STATUS 0x01
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+#define SPI_BCM_6348_SPI_INT_STATUS 0x02
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+#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
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+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x03
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+#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
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+#define SPI_BCM_6348_SPI_INT_MASK 0x04
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+#define SPI_BCM_6348_SPI_CLK_CFG 0x05
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+#define SPI_BCM_6348_SPI_ST 0x05
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+#define SPI_BCM_6348_SPI_ST 0x06
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+#define SPI_BCM_6348_SPI_CLK_CFG 0x06
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+#define SPI_BCM_6348_SPI_INT_MASK 0x07
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+#define SPI_BCM_6348_SPI_FILL_BYTE 0x07
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+#define SPI_BCM_6348_SPI_RX_TAIL 0x08
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+#define SPI_BCM_6348_SPI_MSG_TAIL 0x09
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+#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
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+#define SPI_BCM_6348_SPI_RX_TAIL 0x0b
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+#define SPI_BCM_6348_SPI_MSG_DATA 0x40
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+#define SPI_BCM_6348_SPI_MSG_CTL 0x40
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+#define SPI_BCM_6348_SPI_MSG_CTL 0x42
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+#define SPI_BCM_6348_SPI_MSG_DATA 0x41
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+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
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+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
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+#define SPI_BCM_6348_SPI_RX_DATA 0x80
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+#define SPI_BCM_6348_SPI_RX_DATA 0x80
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+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
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+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
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@ -244,10 +244,10 @@
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+#define SPI_MSG_TYPE_SHIFT 14
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+#define SPI_MSG_TYPE_SHIFT 14
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+
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+
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+/* Command */
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+/* Command */
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||||||
+#define SPI_CMD_NOOP 0x01
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+#define SPI_CMD_NOOP 0x00
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+#define SPI_CMD_SOFT_RESET 0x02
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+#define SPI_CMD_SOFT_RESET 0x01
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+#define SPI_CMD_HARD_RESET 0x04
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+#define SPI_CMD_HARD_RESET 0x02
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+#define SPI_CMD_START_IMMEDIATE 0x08
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+#define SPI_CMD_START_IMMEDIATE 0x03
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+#define SPI_CMD_COMMAND_SHIFT 0
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+#define SPI_CMD_COMMAND_SHIFT 0
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+#define SPI_CMD_COMMAND_MASK 0x000f
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+#define SPI_CMD_COMMAND_MASK 0x000f
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+#define SPI_CMD_DEVICE_ID_SHIFT 4
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+#define SPI_CMD_DEVICE_ID_SHIFT 4
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