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Code

ar71xx: optimize register access in ar71xx_pci.c

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20287 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg 2010-03-18 19:19:16 +00:00
parent 38acf445a9
commit dc4e55fa64
1 changed files with 50 additions and 44 deletions
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94
target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
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@ -1,7 +1,7 @@
/*
* Atheros AR71xx PCI host controller driver
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15 BSP
@ -46,16 +46,6 @@ static inline void ar71xx_pci_delay(void)
mdelay(AR71XX_PCI_DELAY);
}
static inline u32 ar71xx_pcicfg_rr(unsigned int reg)
{
return __raw_readl(ar71xx_pcicfg_base + reg);
}
static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
{
__raw_writel(val, ar71xx_pcicfg_base + reg);
}
/* Byte lane enable bits */
static u8 ble_table[4][4] = {
{0x0, 0xf, 0xf, 0xf},
@ -94,26 +84,27 @@ static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
int ar71xx_pci_be_handler(int is_fixup)
{
void __iomem *base = ar71xx_pcicfg_base;
u32 pci_err;
u32 ahb_err;
pci_err = ar71xx_pcicfg_rr(PCI_REG_PCI_ERR) & 3;
pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3;
if (pci_err) {
if (!is_fixup)
printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
pci_err,
ar71xx_pcicfg_rr(PCI_REG_PCI_ERR_ADDR));
__raw_readl(base + PCI_REG_PCI_ERR_ADDR));
ar71xx_pcicfg_wr(PCI_REG_PCI_ERR, pci_err);
__raw_writel(pci_err, base + PCI_REG_PCI_ERR);
}
ahb_err = ar71xx_pcicfg_rr(PCI_REG_AHB_ERR) & 1;
ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1;
if (ahb_err) {
if (!is_fixup)
printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
ar71xx_pcicfg_rr(PCI_REG_AHB_ERR_ADDR));
__raw_readl(base + PCI_REG_AHB_ERR_ADDR));
ar71xx_pcicfg_wr(PCI_REG_AHB_ERR, ahb_err);
__raw_writel(ahb_err, base + PCI_REG_AHB_ERR);
}
return ((ahb_err | pci_err) ? 1 : 0);
@ -122,6 +113,7 @@ int ar71xx_pci_be_handler(int is_fixup)
static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
unsigned int devfn, int where, int size, u32 cmd)
{
void __iomem *base = ar71xx_pcicfg_base;
u32 addr;
addr = ar71xx_pci_bus_addr(bus, devfn, where);
@ -130,9 +122,9 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
where, size, addr);
ar71xx_pcicfg_wr(PCI_REG_CFG_AD, addr);
ar71xx_pcicfg_wr(PCI_REG_CFG_CBE,
cmd | ar71xx_pci_get_ble(where, size, 0));
__raw_writel(addr, base + PCI_REG_CFG_AD);
__raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
base + PCI_REG_CFG_CBE);
return ar71xx_pci_be_handler(1);
}
@ -140,6 +132,7 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *value)
{
void __iomem *base = ar71xx_pcicfg_base;
static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
unsigned long flags;
u32 data;
@ -157,8 +150,8 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
t = PCI_CRP_CMD_READ | (where & ~3);
ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
data = ar71xx_pcicfg_rr(PCI_REG_CRP_RDDATA);
__raw_writel(t, base + PCI_REG_CRP_AD_CBE);
data = __raw_readl(base + PCI_REG_CRP_RDDATA);
DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
@ -169,7 +162,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
PCI_CFG_CMD_READ);
if (err == 0) {
data = ar71xx_pcicfg_rr(PCI_REG_CFG_RDDATA);
data = __raw_readl(base + PCI_REG_CFG_RDDATA);
} else {
ret = PCIBIOS_DEVICE_NOT_FOUND;
data = ~0;
@ -189,6 +182,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 value)
{
void __iomem *base = ar71xx_pcicfg_base;
unsigned long flags;
int ret;
@ -208,8 +202,8 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
ar71xx_pcicfg_wr(PCI_REG_CRP_WRDATA, value);
__raw_writel(t, base + PCI_REG_CRP_AD_CBE);
__raw_writel(value, base + PCI_REG_CRP_WRDATA);
} else {
int err;
@ -217,7 +211,7 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
PCI_CFG_CMD_WRITE);
if (err == 0)
ar71xx_pcicfg_wr(PCI_REG_CFG_WRDATA, value);
__raw_writel(value, base + PCI_REG_CFG_WRDATA);
else
ret = PCIBIOS_DEVICE_NOT_FOUND;
}
@ -303,10 +297,11 @@ static struct pci_controller ar71xx_pci_controller = {
static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
{
void __iomem *base = ar71xx_reset_base;
u32 pending;
pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
if (pending & PCI_INT_DEV0)
generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
@ -326,22 +321,30 @@ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
static void ar71xx_pci_irq_unmask(unsigned int irq)
{
void __iomem *base = ar71xx_reset_base;
u32 t;
irq -= AR71XX_PCI_IRQ_BASE;
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
/* flush write */
ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
(void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
}
static void ar71xx_pci_irq_mask(unsigned int irq)
{
void __iomem *base = ar71xx_reset_base;
u32 t;
irq -= AR71XX_PCI_IRQ_BASE;
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
/* flush write */
ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
(void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
}
static struct irq_chip ar71xx_pci_irq_chip = {
@ -353,10 +356,11 @@ static struct irq_chip ar71xx_pci_irq_chip = {
static void __init ar71xx_pci_irq_init(void)
{
void __iomem *base = ar71xx_reset_base;
int i;
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
for (i = AR71XX_PCI_IRQ_BASE;
i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
@ -370,6 +374,8 @@ static void __init ar71xx_pci_irq_init(void)
int __init ar71xx_pcibios_init(void)
{
void __iomem *ddr_base = ar71xx_ddr_base;
ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
ar71xx_pci_delay();
@ -379,14 +385,14 @@ int __init ar71xx_pcibios_init(void)
ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
AR71XX_PCI_CFG_SIZE);
ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
__raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
__raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
__raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
__raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
__raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
__raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
__raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
__raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);
ar71xx_pci_delay();